[RISCV] Remove RV64 test lines from umulo-128-legalisation-lowering.ll

The generated code is incorrect anyway, and this test adds noise to the
upcoming set of patches that flesh out RV64 support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343675 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll b/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
index 51c9a35..9f48a20 100644 (file)
--- a/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
+++ b/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
@@ -1,6 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32
-; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RISCV64
 
 define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; RISCV32-LABEL: muloti_test:
@@ -129,34 +128,6 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; RISCV32-NEXT:    lw ra, 76(sp)
 ; RISCV32-NEXT:    addi sp, sp, 80
 ; RISCV32-NEXT:    ret
-;
-; RISCV64-LABEL: muloti_test:
-; RISCV64:       # %bb.0: # %start
-; RISCV64-NEXT:    mul a6, a4, a1
-; RISCV64-NEXT:    mul a5, a2, a3
-; RISCV64-NEXT:    add a6, a5, a6
-; RISCV64-NEXT:    mul a5, a1, a3
-; RISCV64-NEXT:    sw a5, 0(a0)
-; RISCV64-NEXT:    mulhu a7, a1, a3
-; RISCV64-NEXT:    add a5, a7, a6
-; RISCV64-NEXT:    sw a5, 8(a0)
-; RISCV64-NEXT:    sltu a6, a5, a7
-; RISCV64-NEXT:    xor a5, a4, zero
-; RISCV64-NEXT:    snez a7, a5
-; RISCV64-NEXT:    xor a5, a2, zero
-; RISCV64-NEXT:    snez a5, a5
-; RISCV64-NEXT:    and a5, a5, a7
-; RISCV64-NEXT:    mulhu a2, a2, a3
-; RISCV64-NEXT:    xor a2, a2, zero
-; RISCV64-NEXT:    snez a2, a2
-; RISCV64-NEXT:    or a2, a5, a2
-; RISCV64-NEXT:    mulhu a1, a4, a1
-; RISCV64-NEXT:    xor a1, a1, zero
-; RISCV64-NEXT:    snez a1, a1
-; RISCV64-NEXT:    or a1, a2, a1
-; RISCV64-NEXT:    or a1, a1, a6
-; RISCV64-NEXT:    sb a1, 16(a0)
-; RISCV64-NEXT:    ret
 start:
   %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
   %1 = extractvalue { i128, i1 } %0, 0