drm/amdgpu: Add convert_error_address function for umc v8_10

Add convert_error_address for umc v8_10.

Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
index da394bc..293ba39 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
@@ -209,6 +209,45 @@ static int umc_v8_10_swizzle_mode_na_to_pa(struct amdgpu_device *adev,
        return 0;
 }
 
+void umc_v8_10_convert_error_address(struct amdgpu_device *adev,
+                                   struct ras_err_data *err_data, uint64_t err_addr,
+                                   uint32_t ch_inst, uint32_t umc_inst,
+                                   uint32_t node_inst, uint64_t mc_umc_status)
+{
+       uint64_t na_err_addr_base;
+       uint64_t na_err_addr, retired_page_addr;
+       uint32_t channel_index, addr_lsb, col = 0;
+       int ret = 0;
+
+       channel_index =
+               adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num *
+                                       adev->umc.channel_inst_num +
+                                       umc_inst * adev->umc.channel_inst_num +
+                                       ch_inst];
+
+       /* the lowest lsb bits should be ignored */
+       addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb);
+       err_addr &= ~((0x1ULL << addr_lsb) - 1);
+       na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT);
+
+       /* loop for all possibilities of [C6 C5] in normal address. */
+       for (col = 0; col < UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; col++) {
+               na_err_addr = na_err_addr_base | (col << UMC_V8_10_NA_C5_BIT);
+
+               /* Mapping normal error address to retired soc physical address. */
+               ret = umc_v8_10_swizzle_mode_na_to_pa(adev, channel_index,
+                                               na_err_addr, &retired_page_addr);
+               if (ret) {
+                       dev_err(adev->dev, "Failed to map pa from umc na.\n");
+                       break;
+               }
+               dev_info(adev->dev, "Error Address(PA): 0x%llx\n",
+                       retired_page_addr);
+               amdgpu_umc_fill_error_record(err_data, na_err_addr,
+                               retired_page_addr, channel_index, umc_inst);
+       }
+}
+
 static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
                                         struct ras_err_data *err_data,
                                         uint32_t umc_reg_offset,
@@ -218,10 +257,7 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
 {
        uint64_t mc_umc_status_addr;
        uint64_t mc_umc_status, err_addr;
-       uint64_t mc_umc_addrt0, na_err_addr_base;
-       uint64_t na_err_addr, retired_page_addr;
-       uint32_t channel_index, addr_lsb, col = 0;
-       int ret = 0;
+       uint64_t mc_umc_addrt0;
 
        mc_umc_status_addr =
                SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
@@ -236,12 +272,6 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
                return;
        }
 
-       channel_index =
-               adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num *
-                                       adev->umc.channel_inst_num +
-                                       umc_inst * adev->umc.channel_inst_num +
-                                       ch_inst];
-
        /* calculate error address if ue error is detected */
        if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
            REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&
@@ -251,27 +281,8 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
                err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
                err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
 
-               /* the lowest lsb bits should be ignored */
-               addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb);
-               err_addr &= ~((0x1ULL << addr_lsb) - 1);
-               na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT);
-
-               /* loop for all possibilities of [C6 C5] in normal address. */
-               for (col = 0; col < UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; col++) {
-                       na_err_addr = na_err_addr_base | (col << UMC_V8_10_NA_C5_BIT);
-
-                       /* Mapping normal error address to retired soc physical address. */
-                       ret = umc_v8_10_swizzle_mode_na_to_pa(adev, channel_index,
-                                                       na_err_addr, &retired_page_addr);
-                       if (ret) {
-                               dev_err(adev->dev, "Failed to map pa from umc na.\n");
-                               break;
-                       }
-                       dev_info(adev->dev, "Error Address(PA): 0x%llx\n",
-                               retired_page_addr);
-                       amdgpu_umc_fill_error_record(err_data, na_err_addr,
-                                       retired_page_addr, channel_index, umc_inst);
-               }
+               umc_v8_10_convert_error_address(adev, err_data, err_addr,
+                                       ch_inst, umc_inst, node_inst, mc_umc_status);
        }
 
        /* clear umc status */