staging: xillybus: Removed read barrier at beginning of ISR

The comment (also removed) explains why it was there in the first place, but
that doesn't make much sense.

Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/xillybus/xillybus_core.c b/drivers/staging/xillybus/xillybus_core.c
index 8de4fbd..d5a7202 100644 (file)
--- a/drivers/staging/xillybus/xillybus_core.c
+++ b/drivers/staging/xillybus/xillybus_core.c
@@ -133,17 +133,9 @@ irqreturn_t xillybus_isr(int irq, void *data)
        unsigned int msg_channel, msg_bufno, msg_data, msg_dir;
        struct xilly_channel *channel;
 
-       /*
-        * The endpoint structure is altered during periods when it's
-        * guaranteed no interrupt will occur, but in theory, the cache
-        * lines may not be updated. So a memory barrier is issued.
-        */
-       smp_rmb();
-
        buf = ep->msgbuf_addr;
        buf_size = ep->msg_buf_size/sizeof(u32);
 
-
        ep->ephw->hw_sync_sgl_for_cpu(ep,
                                      ep->msgbuf_dma_addr,
                                      ep->msg_buf_size,