* 04C4h : Parameter register
* 04C6h : Transfer control register.
*/
-
+ out_debug_log(_T("WRITE I/O: ADDR=%04X DATA=%02X"), address, data);
switch(address & 0x0f) {
case 0x00: // Master control register
{
val = d_cdrom->read_subq();
break;
}
+// out_debug_log(_T("READ I/O: ADDR=%04X VAL=%02X"), address, val);
return val;
}
if(d_cdrom != NULL) {
track = d_cdrom->get_track(lba1);
}
+ out_debug_log(_T("READ_CDROM TRACK=%d LBA1=%06X LBA2=%06X F1/S1/M1=%02X/%02X/%02X F2/S2/M2=%02X/%02X/%02X"), track, lba1, lba2, f1, s1, m1, f2, s2, m2);
if(track < 2) {
if(lba1 >= 150) {
lba1 = lba1 - 150;
{
switch(ch) {
case SIG_TOWNS_CDC_DRQ:
- if((dma_transfer) && ((data & mask) != 0)) {
- software_transfer_phase = false;
- write_signals(&output_dma_line, 0xffffffff); // Indirect call do_dma().
- } else if((pio_transfer) && ((data & mask) != 0)) {
- software_transfer_phase = true;
- } else if(!((data & mask) != 0)) {
- software_transfer_phase = false;
+ if((data & mask) != 0) {
+ if((dma_transfer) ) {
+ software_transfer_phase = false;
+// uint8_t val = d_scsi_host->read_dma_io8(0);
+ d_dmac->write_signal(SIG_UPD71071_CH3, data, mask);
+// write_signals(&output_dma_line, val); // Indirect call do_dma().
+ } else if((pio_transfer) ) {
+ software_transfer_phase = true;
+ } else {
+ software_transfer_phase = false;
+ }
}
break;
case SIG_TOWNS_CDC_CDROM_DONE:
dma->set_context_ch1(scsi_host);
//dma->set_context_ch2(printer);
dma->set_context_ch3(cdc);
+ //dma->set_context_ch3(cdc_scsi);
dma->set_context_child_dma(extra_dma);
floppy->set_context_fdc(fdc);
cdrom->scsi_id = 0;
cdrom->set_context_interface(cdc_scsi);
cdc_scsi->set_context_target(cdrom);
+ cdrom->set_context_done(cdc, SIG_TOWNS_CDC_CDROM_DONE, 1);
+
cdc->set_context_cdrom(cdrom);
cdc->set_context_scsi_host(cdc_scsi);
cdc->set_context_dmac(dma);