.addReg(MO.getReg(), (isLd ? getDefRegState(true)
: getKillRegState(MO.isKill())))
.cloneMemRefs(*MI);
+ (void)MIB;
LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
} else if (isLd) {
if (isAM2) {
.addImm(Pred)
.addReg(PredReg)
.cloneMemRefs(*MI);
+ (void)MIB;
LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
} else {
int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
.addImm(Imm)
.add(predOps(Pred, PredReg))
.cloneMemRefs(*MI);
+ (void)MIB;
LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
}
} else {
.addImm(Offset)
.add(predOps(Pred, PredReg))
.cloneMemRefs(*MI);
+ (void)MIB;
LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
}
} else {
.addImm(Imm)
.add(predOps(Pred, PredReg))
.cloneMemRefs(*MI);
+ (void)MIB;
LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
} else {
// t2STR_PRE, t2STR_POST
.addImm(Offset)
.add(predOps(Pred, PredReg))
.cloneMemRefs(*MI);
+ (void)MIB;
LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
}
}