[X86][SSE] Add computeNumSignBits test for sitofp of (extended) i64 extracted element

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298592 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/known-signbits-vector.ll b/test/CodeGen/X86/known-signbits-vector.ll
index 12dfdc0..6922bf0 100644 (file)
--- a/test/CodeGen/X86/known-signbits-vector.ll
+++ b/test/CodeGen/X86/known-signbits-vector.ll
@@ -71,3 +71,31 @@ define <4 x float> @signbits_sext_v4i64_sitofp_v4f32(i8 signext %a0, i16 signext
   %9 = sitofp <4 x i64> %8 to <4 x float>
   ret <4 x float> %9
 }
+
+define float @signbits_ashr_extract_sitofp(<2 x i64> %a0) nounwind {
+; X32-LABEL: signbits_ashr_extract_sitofp:
+; X32:       # BB#0:
+; X32-NEXT:    pushl %eax
+; X32-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X32-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X32-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; X32-NEXT:    vmovd %xmm0, %eax
+; X32-NEXT:    vcvtsi2ssl %eax, %xmm2, %xmm0
+; X32-NEXT:    vmovss %xmm0, (%esp)
+; X32-NEXT:    flds (%esp)
+; X32-NEXT:    popl %eax
+; X32-NEXT:    retl
+;
+; X64-LABEL: signbits_ashr_extract_sitofp:
+; X64:       # BB#0:
+; X64-NEXT:    vpsrad $31, %xmm0, %xmm1
+; X64-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X64-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; X64-NEXT:    vmovq %xmm0, %rax
+; X64-NEXT:    vcvtsi2ssl %eax, %xmm2, %xmm0
+; X64-NEXT:    retq
+  %1 = ashr <2 x i64> %a0, <i64 32, i64 32>
+  %2 = extractelement <2 x i64> %1, i32 0
+  %3 = sitofp i64 %2 to float
+  ret float %3
+}