[llvm-exegesis][NFC] Simplify code.

Summary:
What we're redoing already exists in the X86 backend, it's called
`X86II::getOperandBias`.

Reviewers: gchatelet

Subscribers: tschuett, mstojanovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73340

diff --git a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
index a76e590..4daf422 100644 (file)
--- a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
@@ -673,12 +673,7 @@ void ExegesisX86Target::fillMemoryOperands(InstructionTemplate &IT,
   int MemOpIdx = X86II::getMemoryOperandNo(IT.getInstr().Description.TSFlags);
   assert(MemOpIdx >= 0 && "invalid memory operand index");
   // getMemoryOperandNo() ignores tied operands, so we have to add them back.
-  for (unsigned I = 0; I <= static_cast<unsigned>(MemOpIdx); ++I) {
-    const auto &Op = IT.getInstr().Operands[I];
-    if (Op.isTied() && Op.getTiedToIndex() < I) {
-      ++MemOpIdx;
-    }
-  }
+  MemOpIdx += X86II::getOperandBias(IT.getInstr().Description);
   setMemOp(IT, MemOpIdx + 0, MCOperand::createReg(Reg));    // BaseReg
   setMemOp(IT, MemOpIdx + 1, MCOperand::createImm(1));      // ScaleAmt
   setMemOp(IT, MemOpIdx + 2, MCOperand::createReg(0));      // IndexReg