LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
- env->pc = value;
+ set_pc(env, value);
}
static vaddr loongarch_cpu_get_pc(CPUState *cs)
set_DERA:
env->CSR_DERA = env->pc;
env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
- env->pc = env->CSR_EENTRY + 0x480;
+ set_pc(env, env->CSR_EENTRY + 0x480);
break;
case EXCCODE_INT:
if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
/* Find the highest-priority interrupt. */
vector = 31 - clz32(pending);
- env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size;
+ set_pc(env, env->CSR_EENTRY + \
+ (EXCCODE_EXTERNAL_INT + vector) * vec_size);
qemu_log_mask(CPU_LOG_INT,
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
" cause %d\n" " A " TARGET_FMT_lx " D "
env->CSR_ECFG, env->CSR_ESTAT);
} else {
if (tlbfill) {
- env->pc = env->CSR_TLBRENTRY;
+ set_pc(env, env->CSR_TLBRENTRY);
} else {
- env->pc = env->CSR_EENTRY;
- env->pc += EXCODE_MCODE(cause) * vec_size;
+ set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size);
}
qemu_log_mask(CPU_LOG_INT,
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
CPULoongArchState *env = &cpu->env;
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
- env->pc = tb->pc;
+ set_pc(env, tb->pc);
}
static void loongarch_restore_state_to_opc(CPUState *cs,
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
- env->pc = data[0];
+ set_pc(env, data[0]);
}
#endif /* CONFIG_TCG */
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 0);
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 1);
- env->pc = env->CSR_TLBRERA;
+ set_pc(env, env->CSR_TLBRERA);
qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n",
__func__, env->CSR_TLBRERA);
} else {
csr_pplv = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PPLV);
csr_pie = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PIE);
- env->pc = env->CSR_ERA;
+ set_pc(env, env->CSR_ERA);
qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n",
__func__, env->CSR_ERA);
}