irq_n <= '0';\r
vga_clk <= vga_out_clk;\r
\r
- pcl_inst : counter_register generic map (14) port map\r
- (cpu_clk, rst_n, '0', '1', (others => '0'), addr(13 downto 0));\r
+ pcl_inst : counter_register generic map (16) port map\r
+ (cpu_clk, rst_n, '0', '1', (others => '0'), addr(15 downto 0));\r
\r
--- rom_inst : prg_rom generic map (15, 8) port map\r
--- ('0', '0', '1', addr(14 downto 0), d_io);\r
+-- rom_inst : prg_rom generic map (12, 8) port map\r
+-- ('0', '0', '1', addr(11 downto 0), d_io);\r
\r
- addr (15 downto 14) <= (others => '0');\r
+-- addr (15 downto 14) <= (others => '0');\r
\r
- rom_inst : single_port_rom generic map (8, 15) port map\r
- (base_clk, '0', addr(14 downto 0), d_io);\r
+ rom_inst : single_port_rom generic map (8, 12) port map\r
+ (base_clk, '0', addr(11 downto 0), d_io);\r
\r
dbg_addr <= addr;\r
dbg_d_io <= d_io;\r