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arm: mvebu: add Aurora L2 Cache Controller to the DT
authorGregory CLEMENT <gregory.clement@free-electrons.com>
Wed, 26 Sep 2012 16:02:49 +0000 (18:02 +0200)
committerJason Cooper <jason@lakedaemon.net>
Tue, 27 Nov 2012 15:35:34 +0000 (15:35 +0000)
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
arch/arm/boot/dts/armada-370.dtsi
arch/arm/boot/dts/armada-xp.dtsi

index 7fbac28..636cf7d 100644 (file)
 / {
        model = "Marvell Armada 370 family SoC";
        compatible = "marvell,armada370", "marvell,armada-370-xp";
+       L2: l2-cache {
+               compatible = "marvell,aurora-outer-cache";
+               reg = <0xd0008000 0x1000>;
+               cache-id-part = <0x100>;
+               wt-override;
+       };
 
        aliases {
                gpio0 = &gpio0;
index 45a567c..367aa3f 100644 (file)
        model = "Marvell Armada XP family SoC";
        compatible = "marvell,armadaxp", "marvell,armada-370-xp";
 
+       L2: l2-cache {
+               compatible = "marvell,aurora-system-cache";
+               reg = <0xd0008000 0x1000>;
+               cache-id-part = <0x100>;
+               wt-override;
+       };
+
        mpic: interrupt-controller@d0020000 {
              reg = <0xd0020a00 0x1d0>,
                    <0xd0021070 0x58>;