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target/riscv: optimize indirect branches
author
Emilio G. Cota
<cota@braap.org>
Sun, 29 Jul 2018 02:11:17 +0000
(22:11 -0400)
committer
Alistair Francis
<alistair.francis@wdc.com>
Wed, 5 Sep 2018 16:58:38 +0000
(09:58 -0700)
Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/translate.c
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diff --git
a/target/riscv/translate.c
b/target/riscv/translate.c
index
ec2988b
..
66a80ca
100644
(file)
--- a/
target/riscv/translate.c
+++ b/
target/riscv/translate.c
@@
-548,7
+548,7
@@
static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
if (rd != 0) {
tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
}
- tcg_gen_
exit_tb(NULL, 0
);
+ tcg_gen_
lookup_and_goto_ptr(
);
if (misaligned) {
gen_set_label(misaligned);