drm/i915/gen12: MBUS B credit change

Previously, the recommended B credit for all platforms was 24 / number
of pipes, which would give 6 for newer platforms with 4 pipes. However 6
is not enough and we need 12 on these cases.

We also need a different BW credit for these platforms.

Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-17-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0a15c08..79ae8f4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6423,8 +6423,14 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
        u32 val;
 
        val = MBUS_DBOX_A_CREDIT(2);
-       val |= MBUS_DBOX_BW_CREDIT(1);
-       val |= MBUS_DBOX_B_CREDIT(8);
+
+       if (INTEL_GEN(dev_priv) >= 12) {
+               val |= MBUS_DBOX_BW_CREDIT(2);
+               val |= MBUS_DBOX_B_CREDIT(12);
+       } else {
+               val |= MBUS_DBOX_BW_CREDIT(1);
+               val |= MBUS_DBOX_B_CREDIT(8);
+       }
 
        I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
 }