drm/i915: Drop unpin stall in atomic_prepare_commit

The core already does this in setup_commit(). With this we can also
remove the unpin_work_count since it's the last user, and also remove
the loop since that was only used for stalling against legacy flips.

v2: Amend commit message a bit (Chris).

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20170720175754.30751-8-daniel.vetter@ffwll.ch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 56bf900..9e89978 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11815,18 +11815,7 @@ static int intel_atomic_check(struct drm_device *dev,
 static int intel_atomic_prepare_commit(struct drm_device *dev,
                                       struct drm_atomic_state *state)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-       struct drm_crtc_state *crtc_state;
-       struct drm_crtc *crtc;
-       int i, ret;
-
-       for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
-               if (state->legacy_cursor_update)
-                       continue;
-
-               if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
-                       flush_workqueue(dev_priv->wq);
-       }
+       int ret;
 
        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 79009b7..021cc54 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -798,8 +798,6 @@ struct intel_crtc {
        unsigned long long enabled_power_domains;
        struct intel_overlay *overlay;
 
-       atomic_t unpin_work_count;
-
        /* Display surface base address adjustement for pageflips. Note that on
         * gen4+ this only adjusts up to a tile, offsets within a tile are
         * handled in the hw itself (with the TILEOFF register). */