moveq r0, #1 /* can't let setjmp() return zero! */
#if defined __UCLIBC_HAS_FLOATS__ && ! defined __UCLIBC_HAS_SOFT_FLOAT__
+# ifdef __MAVERICK__
+ cfldrd mvd4, [ip], #8 ; nop
+ cfldrd mvd5, [ip], #8 ; nop
+ cfldrd mvd6, [ip], #8 ; nop
+ cfldrd mvd7, [ip], #8 ; nop
+ cfldrd mvd8, [ip], #8 ; nop
+ cfldrd mvd9, [ip], #8 ; nop
+ cfldrd mvd10, [ip], #8 ; nop
+ cfldrd mvd11, [ip], #8 ; nop
+ cfldrd mvd12, [ip], #8 ; nop
+ cfldrd mvd13, [ip], #8 ; nop
+ cfldrd mvd14, [ip], #8 ; nop
+ cfldrd mvd15, [ip], #8
+# else
lfmfd f4, 4, [ip] ! /* load the floating point regs */
+# endif
#else
+# ifdef __MAVERICK__
+ add ip, ip, #96 /* skip the FP registers */
+# else
add ip, ip, #48 /* skip the FP registers */
+# endif
#endif
ldmia ip , {v1-v6, sl, fp, sp, pc}
/* FPA floating point units are always big-endian, irrespective of the
CPU endianness. VFP floating point units use the same endianness
as the rest of the system. */
-#ifdef __VFP_FP__
+#if defined __VFP_FP__ || defined __MAVERICK__
# define __FLOAT_WORD_ORDER __BYTE_ORDER
#else
# define __FLOAT_WORD_ORDER __BIG_ENDIAN
# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
#endif
+#ifdef __MAVERICK__
+
+/* Define bits representing exceptions in the FPU status word. */
+enum
+ {
+ FE_INVALID = 1,
+#define FE_INVALID FE_INVALID
+ FE_OVERFLOW = 4,
+#define FE_OVERFLOW FE_OVERFLOW
+ FE_UNDERFLOW = 8,
+#define FE_UNDERFLOW FE_UNDERFLOW
+ FE_INEXACT = 16,
+#define FE_INEXACT FE_INEXACT
+ };
+
+/* Amount to shift by to convert an exception to a mask bit. */
+#define FE_EXCEPT_SHIFT 5
+
+/* All supported exceptions. */
+#define FE_ALL_EXCEPT \
+ (FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW | FE_INEXACT)
+
+/* IEEE rounding modes. */
+enum
+ {
+ FE_TONEAREST = 0,
+#define FE_TONEAREST FE_TONEAREST
+ FE_TOWARDZERO = 0x400,
+#define FE_TOWARDZERO FE_TOWARDZERO
+ FE_DOWNWARD = 0x800,
+#define FE_DOWNWARD FE_DOWNWARD
+ FE_UPWARD = 0xc00,
+#define FE_UPWARD FE_UPWARD
+ };
+
+#define FE_ROUND_MASK (FE_UPWARD)
+
+#else /* !__MAVERICK__ */
+
/* Define bits representing exceptions in the FPU status word. */
enum
{
modes exist, but you have to encode them in the actual instruction. */
#define FE_TONEAREST 0
+#endif /* __MAVERICK__ */
+
/* Type representing exception flags. */
typedef unsigned long int fexcept_t;
#ifndef _ASM
/* Jump buffer contains v1-v6, sl, fp, sp and pc. Other registers are not
saved. */
+#ifdef __MAVERICK__
+typedef int __jmp_buf[34];
+#else
typedef int __jmp_buf[22];
#endif
+#endif
#define __JMP_BUF_SP 20
#ifndef _FPU_CONTROL_H
#define _FPU_CONTROL_H
+#ifdef __MAVERICK__
+
+/* DSPSC register: (from EP9312 User's Guide)
+ *
+ * bits 31..29 - DAID
+ * bits 28..26 - HVID
+ * bits 25..24 - RSVD
+ * bit 23 - ISAT
+ * bit 22 - UI
+ * bit 21 - INT
+ * bit 20 - AEXC
+ * bits 19..18 - SAT
+ * bits 17..16 - FCC
+ * bit 15 - V
+ * bit 14 - FWDEN
+ * bit 13 - Invalid
+ * bit 12 - Denorm
+ * bits 11..10 - RM
+ * bits 9..5 - IXE, UFE, OFE, RSVD, IOE
+ * bits 4..0 - IX, UF, OF, RSVD, IO
+ */
+
+/* masking of interrupts */
+#define _FPU_MASK_IM (1 << 5) /* invalid operation */
+#define _FPU_MASK_ZM 0 /* divide by zero */
+#define _FPU_MASK_OM (1 << 7) /* overflow */
+#define _FPU_MASK_UM (1 << 8) /* underflow */
+#define _FPU_MASK_PM (1 << 9) /* inexact */
+#define _FPU_MASK_DM 0 /* denormalized operation */
+
+#define _FPU_RESERVED 0xfffff000 /* These bits are reserved. */
+
+#define _FPU_DEFAULT 0x00b00000 /* Default value. */
+#define _FPU_IEEE 0x00b003a0 /* Default + exceptions enabled. */
+
+/* Type of the control word. */
+typedef unsigned int fpu_control_t;
+
+/* Macros for accessing the hardware control word. */
+#define _FPU_GETCW(cw) ({ \
+ register int __t1, __t2; \
+ \
+ __asm__ volatile ( \
+ "cfmvr64l %1, mvdx0\n\t" \
+ "cfmvr64h %2, mvdx0\n\t" \
+ "cfmv32sc mvdx0, dspsc\n\t" \
+ "cfmvr64l %0, mvdx0\n\t" \
+ "cfmv64lr mvdx0, %1\n\t" \
+ "cfmv64hr mvdx0, %2" \
+ : "=r" (cw), "=r" (__t1), "=r" (__t2) \
+ ); \
+})
+
+#define _FPU_SETCW(cw) ({ \
+ register int __t0, __t1, __t2; \
+ \
+ __asm__ volatile ( \
+ "cfmvr64l %1, mvdx0\n\t" \
+ "cfmvr64h %2, mvdx0\n\t" \
+ "cfmv64lr mvdx0, %0\n\t" \
+ "cfmvsc32 dspsc, mvdx0\n\t" \
+ "cfmv64lr mvdx0, %1\n\t" \
+ "cfmv64hr mvdx0, %2" \
+ : "=r" (__t0), "=r" (__t1), "=r" (__t2) \
+ : "0" (cw) \
+ ); \
+})
+
+#else /* !__MAVERICK__ */
+
/* We have a slight terminology confusion here. On the ARM, the register
* we're interested in is actually the FPU status word - the FPU control
* word is something different (which is implementation-defined and only
#define _FPU_GETCW(cw) __asm__ ("rfs %0" : "=r" (cw))
#define _FPU_SETCW(cw) __asm__ ("wfs %0" : : "r" (cw))
+#endif /* __MAVERICK__ */
+
/* Default control word set at startup. */
extern fpu_control_t __fpu_control;
__sigsetjmp:
/* Save registers */
#if defined __UCLIBC_HAS_FLOATS__ && ! defined __UCLIBC_HAS_SOFT_FLOAT__
+# ifdef __MAVERICK__
+ cfstrd mvd4, [r0], #8 ; nop
+ cfstrd mvd5, [r0], #8 ; nop
+ cfstrd mvd6, [r0], #8 ; nop
+ cfstrd mvd7, [r0], #8 ; nop
+ cfstrd mvd8, [r0], #8 ; nop
+ cfstrd mvd9, [r0], #8 ; nop
+ cfstrd mvd10, [r0], #8 ; nop
+ cfstrd mvd11, [r0], #8 ; nop
+ cfstrd mvd12, [r0], #8 ; nop
+ cfstrd mvd13, [r0], #8 ; nop
+ cfstrd mvd14, [r0], #8 ; nop
+ cfstrd mvd15, [r0], #8
+# else
sfmea f4, 4, [r0]!
+# endif
#else
+# ifdef __MAVERICK__
+ add r0, r0, #96 /* skip the FP registers */
+# else
add r0, r0, #48 /* skip the FP registers */
+# endif
#endif
stmia r0, {v1-v6, sl, fp, sp, lr}
/* Restore pointer to jmp_buf */
+#ifdef __MAVERICK__
+ sub r0, r0, #96
+#else
sub r0, r0, #48
+#endif
/* Make a tail call to __sigjmp_save; it takes the same args. */
#ifdef __PIC__
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