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[PATCH] ppc64: use c99 initialisers in cputable code
authorAnton Blanchard <anton@samba.org>
Fri, 8 Jul 2005 00:56:11 +0000 (17:56 -0700)
committerLinus Torvalds <torvalds@g5.osdl.org>
Fri, 8 Jul 2005 01:23:36 +0000 (18:23 -0700)
Use c99 initialisers in the cputable code.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
arch/ppc64/kernel/cputable.c patch | blob | history

diff --git a/arch/ppc64/kernel/cputable.c b/arch/ppc64/kernel/cputable.c
index 1d162c7..c301366 100644 (file)
--- a/arch/ppc64/kernel/cputable.c
+++ b/arch/ppc64/kernel/cputable.c
@@ -49,160 +49,219 @@ extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
 #endif
 
 struct cpu_spec        cpu_specs[] = {
-    {  /* Power3 */
-           0xffff0000, 0x00400000, "POWER3 (630)",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_IABR | CPU_FTR_PMC8,
-           COMMON_USER_PPC64,
-           128, 128,
-           __setup_cpu_power3,
-           COMMON_PPC64_FW
-    },
-    {  /* Power3+ */
-           0xffff0000, 0x00410000, "POWER3 (630+)",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_IABR | CPU_FTR_PMC8,
-           COMMON_USER_PPC64,
-           128, 128,
-           __setup_cpu_power3,
-           COMMON_PPC64_FW
-    },
-    {  /* Northstar */
-           0xffff0000, 0x00330000, "RS64-II (northstar)",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-           COMMON_USER_PPC64,
-           128, 128,
-           __setup_cpu_power3,
-           COMMON_PPC64_FW
-    },
-    {  /* Pulsar */
-           0xffff0000, 0x00340000, "RS64-III (pulsar)",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-           COMMON_USER_PPC64,
-           128, 128,
-           __setup_cpu_power3,
-           COMMON_PPC64_FW
-    },
-    {  /* I-star */
-           0xffff0000, 0x00360000, "RS64-III (icestar)",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-           COMMON_USER_PPC64,
-           128, 128,
-           __setup_cpu_power3,
-           COMMON_PPC64_FW
-    },
-    {  /* S-star */
-           0xffff0000, 0x00370000, "RS64-IV (sstar)",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-           COMMON_USER_PPC64,
-           128, 128,
-           __setup_cpu_power3,
-           COMMON_PPC64_FW
-    },
-    {  /* Power4 */
-           0xffff0000, 0x00350000, "POWER4 (gp)",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-           COMMON_USER_PPC64,
-           128, 128,
-           __setup_cpu_power4,
-           COMMON_PPC64_FW
-    },
-    {  /* Power4+ */
-           0xffff0000, 0x00380000, "POWER4+ (gq)",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-           COMMON_USER_PPC64,
-           128, 128,
-           __setup_cpu_power4,
-           COMMON_PPC64_FW
-    },
-    {  /* PPC970 */
-           0xffff0000, 0x00390000, "PPC970",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
-                   CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-           COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
-           128, 128,
-           __setup_cpu_ppc970,
-           COMMON_PPC64_FW
-    },
-    {  /* PPC970FX */
-           0xffff0000, 0x003c0000, "PPC970FX",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
-                   CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-           COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
-           128, 128,
-           __setup_cpu_ppc970,
-           COMMON_PPC64_FW
-    },
-    {  /* Power5 */
-           0xffff0000, 0x003a0000, "POWER5 (gr)",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
-                   CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
-                   CPU_FTR_MMCRA_SIHV,
-           COMMON_USER_PPC64,
-           128, 128,
-           __setup_cpu_power4,
-           COMMON_PPC64_FW
-    },
-    {  /* Power5 */
-           0xffff0000, 0x003b0000, "POWER5 (gs)",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
-                   CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
-                   CPU_FTR_MMCRA_SIHV,
-           COMMON_USER_PPC64,
-           128, 128,
-           __setup_cpu_power4,
-           COMMON_PPC64_FW
-    },
-    {  /* BE DD1.x  */
-           0xffff0000, 0x00700000, "Broadband Engine",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
-                   CPU_FTR_SMT,
-           COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
-           128, 128,
-           __setup_cpu_be,
-           COMMON_PPC64_FW
-    },
-    {  /* default match */
-           0x00000000, 0x00000000, "POWER4 (compatible)",
-           CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                   CPU_FTR_PPCAS_ARCH_V2,
-           COMMON_USER_PPC64,
-           128, 128,
-           __setup_cpu_power4,
-           COMMON_PPC64_FW
-    }
+       {       /* Power3 */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x00400000,
+               .cpu_name               = "POWER3 (630)",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
+                       CPU_FTR_PMC8,
+               .cpu_user_features = COMMON_USER_PPC64,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_power3,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* Power3+ */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x00410000,
+               .cpu_name               = "POWER3 (630+)",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
+                       CPU_FTR_PMC8,
+               .cpu_user_features      = COMMON_USER_PPC64,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_power3,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* Northstar */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x00330000,
+               .cpu_name               = "RS64-II (northstar)",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
+                       CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+               .cpu_user_features      = COMMON_USER_PPC64,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_power3,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* Pulsar */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x00340000,
+               .cpu_name               = "RS64-III (pulsar)",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
+                       CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+               .cpu_user_features      = COMMON_USER_PPC64,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_power3,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* I-star */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x00360000,
+               .cpu_name               = "RS64-III (icestar)",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
+                       CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+               .cpu_user_features      = COMMON_USER_PPC64,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_power3,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* S-star */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x00370000,
+               .cpu_name               = "RS64-IV (sstar)",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
+                       CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+               .cpu_user_features      = COMMON_USER_PPC64,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_power3,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* Power4 */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x00350000,
+               .cpu_name               = "POWER4 (gp)",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                       CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+               .cpu_user_features      = COMMON_USER_PPC64,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_power4,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* Power4+ */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x00380000,
+               .cpu_name               = "POWER4+ (gq)",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                       CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+               .cpu_user_features      = COMMON_USER_PPC64,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_power4,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* PPC970 */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x00390000,
+               .cpu_name               = "PPC970",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                       CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
+                       CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+               .cpu_user_features      = COMMON_USER_PPC64 |
+                       PPC_FEATURE_HAS_ALTIVEC_COMP,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_ppc970,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* PPC970FX */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x003c0000,
+               .cpu_name               = "PPC970FX",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                       CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
+                       CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+               .cpu_user_features      = COMMON_USER_PPC64 |
+                       PPC_FEATURE_HAS_ALTIVEC_COMP,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_ppc970,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* Power5 */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x003a0000,
+               .cpu_name               = "POWER5 (gr)",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                       CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
+                       CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+                       CPU_FTR_MMCRA_SIHV,
+               .cpu_user_features      = COMMON_USER_PPC64,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_power4,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* Power5 */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x003b0000,
+               .cpu_name               = "POWER5 (gs)",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                       CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
+                       CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+                       CPU_FTR_MMCRA_SIHV,
+               .cpu_user_features      = COMMON_USER_PPC64,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_power4,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* BE DD1.x */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x00700000,
+               .cpu_name               = "Broadband Engine",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                       CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
+                       CPU_FTR_SMT,
+               .cpu_user_features      = COMMON_USER_PPC64 |
+                       PPC_FEATURE_HAS_ALTIVEC_COMP,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_be,
+               .firmware_features      = COMMON_PPC64_FW,
+       },
+       {       /* default match */
+               .pvr_mask               = 0x00000000,
+               .pvr_value              = 0x00000000,
+               .cpu_name               = "POWER4 (compatible)",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                       CPU_FTR_PPCAS_ARCH_V2,
+               .cpu_user_features      = COMMON_USER_PPC64,
+               .icache_bsize           = 128,
+               .dcache_bsize           = 128,
+               .cpu_setup              = __setup_cpu_power4,
+               .firmware_features      = COMMON_PPC64_FW,
+       }
 };
 
 firmware_feature_t firmware_features_table[FIRMWARE_MAX_FEATURES] = {
-    {FW_FEATURE_PFT,           "hcall-pft"},
-    {FW_FEATURE_TCE,           "hcall-tce"},
-    {FW_FEATURE_SPRG0,         "hcall-sprg0"},
-    {FW_FEATURE_DABR,          "hcall-dabr"},
-    {FW_FEATURE_COPY,          "hcall-copy"},
-    {FW_FEATURE_ASR,           "hcall-asr"},
-    {FW_FEATURE_DEBUG,         "hcall-debug"},
-    {FW_FEATURE_PERF,          "hcall-perf"},
-    {FW_FEATURE_DUMP,          "hcall-dump"},
-    {FW_FEATURE_INTERRUPT,     "hcall-interrupt"},
-    {FW_FEATURE_MIGRATE,       "hcall-migrate"},
-    {FW_FEATURE_PERFMON,       "hcall-perfmon"},
-    {FW_FEATURE_CRQ,           "hcall-crq"},
-    {FW_FEATURE_VIO,           "hcall-vio"},
-    {FW_FEATURE_RDMA,          "hcall-rdma"},
-    {FW_FEATURE_LLAN,          "hcall-lLAN"},
-    {FW_FEATURE_BULK,          "hcall-bulk"},
-    {FW_FEATURE_XDABR,         "hcall-xdabr"},
-    {FW_FEATURE_MULTITCE,      "hcall-multi-tce"},
-    {FW_FEATURE_SPLPAR,                "hcall-splpar"},
+       {FW_FEATURE_PFT,                "hcall-pft"},
+       {FW_FEATURE_TCE,                "hcall-tce"},
+       {FW_FEATURE_SPRG0,              "hcall-sprg0"},
+       {FW_FEATURE_DABR,               "hcall-dabr"},
+       {FW_FEATURE_COPY,               "hcall-copy"},
+       {FW_FEATURE_ASR,                "hcall-asr"},
+       {FW_FEATURE_DEBUG,              "hcall-debug"},
+       {FW_FEATURE_PERF,               "hcall-perf"},
+       {FW_FEATURE_DUMP,               "hcall-dump"},
+       {FW_FEATURE_INTERRUPT,          "hcall-interrupt"},
+       {FW_FEATURE_MIGRATE,            "hcall-migrate"},
+       {FW_FEATURE_PERFMON,            "hcall-perfmon"},
+       {FW_FEATURE_CRQ,                "hcall-crq"},
+       {FW_FEATURE_VIO,                "hcall-vio"},
+       {FW_FEATURE_RDMA,               "hcall-rdma"},
+       {FW_FEATURE_LLAN,               "hcall-lLAN"},
+       {FW_FEATURE_BULK,               "hcall-bulk"},
+       {FW_FEATURE_XDABR,              "hcall-xdabr"},
+       {FW_FEATURE_MULTITCE,           "hcall-multi-tce"},
+       {FW_FEATURE_SPLPAR,             "hcall-splpar"},
 };
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