radeon: add wait rendering API

diff --git a/linux-core/radeon_gem.c b/linux-core/radeon_gem.c
index ce33979..f5d6b94 100644 (file)
--- a/linux-core/radeon_gem.c
+++ b/linux-core/radeon_gem.c
@@ -416,14 +416,33 @@ int radeon_gem_busy(struct drm_device *dev, void *data,
        return 0;
 }
 
-int radeon_gem_execbuffer(struct drm_device *dev, void *data,
-                         struct drm_file *file_priv)
+int radeon_gem_wait_rendering(struct drm_device *dev, void *data,
+                             struct drm_file *file_priv)
 {
-       return -ENOSYS;
+       struct drm_radeon_gem_wait_rendering *args = data;
+       struct drm_gem_object *obj;
+       struct drm_radeon_gem_object *obj_priv;
+       int ret;
+
+
+       obj = drm_gem_object_lookup(dev, file_priv, args->handle);
+       if (obj == NULL)
+               return -EINVAL;
 
+       obj_priv = obj->driver_private;
 
+       mutex_lock(&obj_priv->bo->mutex);
+       ret = drm_bo_wait(obj_priv->bo, 0, 1, 1, 0);
+       mutex_unlock(&obj_priv->bo->mutex);
+       
+       mutex_lock(&dev->struct_mutex);
+       drm_gem_object_unreference(obj);
+       mutex_unlock(&dev->struct_mutex);
+       return ret;
 }
 
+
+
 /*
  * Depending on card genertation, chipset bugs, etc... the amount of vram
  * accessible to the CPU can vary. This function is our best shot at figuring

diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h
index 0780eb7..002e400 100644 (file)
--- a/shared-core/radeon_drm.h
+++ b/shared-core/radeon_drm.h
@@ -511,6 +511,7 @@ typedef struct {
 #define DRM_RADEON_GEM_PREAD  0x21
 #define DRM_RADEON_GEM_PWRITE 0x22
 #define DRM_RADEON_GEM_SET_DOMAIN 0x23
+#define DRM_RADEON_GEM_WAIT_RENDERING 0x24
 
 #define DRM_RADEON_CS           0x25
 #define DRM_RADEON_CS2       0x26
@@ -551,7 +552,7 @@ typedef struct {
 #define DRM_IOCTL_RADEON_GEM_PREAD   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
 #define DRM_IOCTL_RADEON_GEM_PWRITE   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
 #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN  DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
-
+#define DRM_IOCTL_RADEON_GEM_WAIT_RENDERING DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_RENDERING, struct drm_radeon_gem_wait_rendering) 
 #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
 #define DRM_IOCTL_RADEON_CS2 DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS2, struct drm_radeon_cs2)
 
@@ -820,7 +821,8 @@ struct drm_radeon_gem_set_domain {
        uint32_t write_domain;
 };
 
-struct drm_radeon_gem_exec_buffer {
+struct drm_radeon_gem_wait_rendering {
+       uint32_t handle;
 };
 
 struct drm_radeon_gem_pin {

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 85a22e9..aa178d4 100644 (file)
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1695,6 +1695,8 @@ int radeon_gem_object_pin(struct drm_gem_object *obj,
 int radeon_gem_object_unpin(struct drm_gem_object *obj);
 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
                                struct drm_file *file_priv);
+int radeon_gem_wait_rendering(struct drm_device *dev, void *data,
+                             struct drm_file *file_priv);
 struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, int alignment,
                                               int initial_domain, bool discardable);
 int radeon_modeset_init(struct drm_device *dev);

diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index 40ecf1c..ada9136 100644 (file)
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -3288,6 +3288,7 @@ struct drm_ioctl_desc radeon_ioctls[] = {
        DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
        DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
        DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH),
+       DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_RENDERING, radeon_gem_wait_rendering, DRM_AUTH),
        DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH),
        DRM_IOCTL_DEF(DRM_RADEON_CS2, radeon_cs2_ioctl, DRM_AUTH),
 };