+Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
+ David Mosberger <davidm@hpl.hp.com>
+ Timothy Wall <twall@cygnus.com>
+ Jim Wilson <wilson@cygnus.com>
+
+ * Makefile.am (ALL_MACHINES): Add cpu-ia64.lo.
+ (ALL_MACHINES_CFILES): Add cpu-ia64.c.
+ (BFD64_BACKENDS): Add elf64-ia64.lo.
+ (BFD64_BACKENDS_CFILES): Add elf64-ia64.c.
+ (cpu-ia64.lo, elf64-ia64.lo): New rules.
+ * Makefile.in: Rebuild.
+ * archures.c (enum bfd_architecture): Add bfd_arch_ia64.
+ (bfd_ia64_arch): Declare.
+ (bfd_archures_list): Add bfd_ia64_arch.
+ * bfd-in2.h: Rebuild.
+ * config.bfd: (ia64*-*-linux-gnu*, ia64*-*-elf*): New targets.
+ * configure: Rebuild.
+ * configure.host: (ia64-*-linux*): New host.
+ * configure.in (bfd_elf64_ia64_little_vec, bfd_elf64_ia64_big_vec,
+ bfd_efi_app_ia64_vec, bfd_efi_app_ia64_vec): New vectors.
+ * elf.c (prep_headers): Add bfd_arch_ia64.
+ * libbfd.h: Rebuild.
+ * reloc.c: Add IA-64 relocations.
+ * targets.c (bfd_elf64_ia64_little_vec, bfd_elf64_ia64_big_vec):
+ Declare.
+ (bfd_target_vect): Add bfd_elf64_ia64_little_vec.
+ * cpu-ia64-opc.c, cpu-ia64.c, elf64-ia64.c: New files.
+
2000-04-21 Richard Henderson <rth@cygnus.com>
* elf32-d30v.c (bfd_elf_d30v_reloc): Don't modify section
cpu-h8300.lo \
cpu-h8500.lo \
cpu-hppa.lo \
+ cpu-ia64.lo \
cpu-i370.lo \
cpu-i386.lo \
cpu-i860.lo \
cpu-h8300.c \
cpu-h8500.c \
cpu-hppa.c \
+ cpu-ia64.c \
cpu-i370.c \
cpu-i386.c \
cpu-i860.c \
coff-ia64.lo \
demo64.lo \
elf64-alpha.lo \
+ elf64-ia64.lo \
elf64-gen.lo \
elf64-mips.lo \
elf64-sparc.lo \
coff-ia64.c \
demo64.c \
elf64-alpha.c \
+ elf64-ia64.c \
elf64-gen.c \
elf64-mips.c \
elf64-sparc.c \
$(SHELL) ./config.status --recheck
+cpu-ia64.lo: cpu-ia64.c cpu-ia64-opc.c $(srcdir)/../opcodes/ia64-opc.h
+elf64-ia64.lo: elf64-ia64.c elf-bfd.h $(INCDIR)/opcode/ia64.h \
+ $(INCDIR)/elf/ia64.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/reloc-macros.h \
+ elf64-target.h
elfarm-oabi.lo: elfarm-oabi.c elf32-arm.h elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
$(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h elf32-target.h
cpu-h8300.lo \
cpu-h8500.lo \
cpu-hppa.lo \
+ cpu-ia64.lo \
cpu-i370.lo \
cpu-i386.lo \
cpu-i860.lo \
cpu-h8300.c \
cpu-h8500.c \
cpu-hppa.c \
+ cpu-ia64.c \
cpu-i370.c \
cpu-i386.c \
cpu-i860.c \
coff-ia64.lo \
demo64.lo \
elf64-alpha.lo \
+ elf64-ia64.lo \
elf64-gen.lo \
elf64-mips.lo \
elf64-sparc.lo \
coff-ia64.c \
demo64.c \
elf64-alpha.c \
+ elf64-ia64.c \
elf64-gen.c \
elf64-mips.c \
elf64-sparc.c \
config.status: $(srcdir)/configure $(srcdir)/config.bfd $(srcdir)/configure.host
$(SHELL) ./config.status --recheck
+cpu-ia64.lo: cpu-ia64.c cpu-ia64-opc.c $(srcdir)/../opcodes/ia64-opc.h
+elf64-ia64.lo: elf64-ia64.c elf-bfd.h $(INCDIR)/opcode/ia64.h \
+ $(INCDIR)/elf/ia64.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/reloc-macros.h \
+ elf64-target.h
elfarm-oabi.lo: elfarm-oabi.c elf32-arm.h elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
$(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h elf32-target.h
. bfd_arch_fr30,
.#define bfd_mach_fr30 0x46523330
. bfd_arch_mcore,
+. bfd_arch_ia64, {* HP/Intel ia64 *}
. bfd_arch_pj,
. bfd_arch_avr, {* Atmel AVR microcontrollers *}
.#define bfd_mach_avr1 1
extern const bfd_arch_info_type bfd_fr30_arch;
extern const bfd_arch_info_type bfd_mcore_arch;
extern const bfd_arch_info_type bfd_avr_arch;
+extern const bfd_arch_info_type bfd_ia64_arch;
static const bfd_arch_info_type * const bfd_archures_list[] =
{
&bfd_fr30_arch,
&bfd_mcore_arch,
&bfd_avr_arch,
+ &bfd_ia64_arch,
#endif
0
};
bfd_arch_fr30,
#define bfd_mach_fr30 0x46523330
bfd_arch_mcore,
+ bfd_arch_ia64, /* HP/Intel ia64 */
bfd_arch_pj,
bfd_arch_avr, /* Atmel AVR microcontrollers */
#define bfd_mach_avr1 1
this offset in the reloc's section offset. */
BFD_RELOC_VTABLE_INHERIT,
BFD_RELOC_VTABLE_ENTRY,
+
+/* Intel IA64 Relocations. */
+ BFD_RELOC_IA64_IMM14,
+ BFD_RELOC_IA64_IMM22,
+ BFD_RELOC_IA64_IMM64,
+ BFD_RELOC_IA64_DIR32MSB,
+ BFD_RELOC_IA64_DIR32LSB,
+ BFD_RELOC_IA64_DIR64MSB,
+ BFD_RELOC_IA64_DIR64LSB,
+ BFD_RELOC_IA64_GPREL22,
+ BFD_RELOC_IA64_GPREL64I,
+ BFD_RELOC_IA64_GPREL32MSB,
+ BFD_RELOC_IA64_GPREL32LSB,
+ BFD_RELOC_IA64_GPREL64MSB,
+ BFD_RELOC_IA64_GPREL64LSB,
+ BFD_RELOC_IA64_LTOFF22,
+ BFD_RELOC_IA64_LTOFF64I,
+ BFD_RELOC_IA64_PLTOFF22,
+ BFD_RELOC_IA64_PLTOFF64I,
+ BFD_RELOC_IA64_PLTOFF64MSB,
+ BFD_RELOC_IA64_PLTOFF64LSB,
+ BFD_RELOC_IA64_FPTR64I,
+ BFD_RELOC_IA64_FPTR32MSB,
+ BFD_RELOC_IA64_FPTR32LSB,
+ BFD_RELOC_IA64_FPTR64MSB,
+ BFD_RELOC_IA64_FPTR64LSB,
+ BFD_RELOC_IA64_PCREL21B,
+ BFD_RELOC_IA64_PCREL21M,
+ BFD_RELOC_IA64_PCREL21F,
+ BFD_RELOC_IA64_PCREL32MSB,
+ BFD_RELOC_IA64_PCREL32LSB,
+ BFD_RELOC_IA64_PCREL64MSB,
+ BFD_RELOC_IA64_PCREL64LSB,
+ BFD_RELOC_IA64_LTOFF_FPTR22,
+ BFD_RELOC_IA64_LTOFF_FPTR64I,
+ BFD_RELOC_IA64_LTOFF_FPTR64MSB,
+ BFD_RELOC_IA64_LTOFF_FPTR64LSB,
+ BFD_RELOC_IA64_SEGBASE,
+ BFD_RELOC_IA64_SEGREL32MSB,
+ BFD_RELOC_IA64_SEGREL32LSB,
+ BFD_RELOC_IA64_SEGREL64MSB,
+ BFD_RELOC_IA64_SEGREL64LSB,
+ BFD_RELOC_IA64_SECREL32MSB,
+ BFD_RELOC_IA64_SECREL32LSB,
+ BFD_RELOC_IA64_SECREL64MSB,
+ BFD_RELOC_IA64_SECREL64LSB,
+ BFD_RELOC_IA64_REL32MSB,
+ BFD_RELOC_IA64_REL32LSB,
+ BFD_RELOC_IA64_REL64MSB,
+ BFD_RELOC_IA64_REL64LSB,
+ BFD_RELOC_IA64_LTV32MSB,
+ BFD_RELOC_IA64_LTV32LSB,
+ BFD_RELOC_IA64_LTV64MSB,
+ BFD_RELOC_IA64_LTV64LSB,
+ BFD_RELOC_IA64_IPLTMSB,
+ BFD_RELOC_IA64_IPLTLSB,
+ BFD_RELOC_IA64_EPLTMSB,
+ BFD_RELOC_IA64_EPLTLSB,
+ BFD_RELOC_IA64_COPY,
+ BFD_RELOC_IA64_TPREL22,
+ BFD_RELOC_IA64_TPREL64MSB,
+ BFD_RELOC_IA64_TPREL64LSB,
+ BFD_RELOC_IA64_LTOFF_TP22,
+ BFD_RELOC_IA64_LTOFF22X,
+ BFD_RELOC_IA64_LDXMOV,
BFD_RELOC_UNUSED };
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
reloc_howto_type *
alpha*-*-*)
targ_defvec=ecoffalpha_little_vec
;;
+ ia64*-*-linux-gnu* | ia64*-*-elf*)
+ targ_defvec=bfd_elf64_ia64_little_vec
+ targ_selvecs="bfd_elf64_ia64_big_vec bfd_efi_app_ia64_vec"
+ ;;
#endif /* BFD64 */
arc-*-elf*)
target64=true ;;
bfd_elf64_alpha_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"
target64=true ;;
+ bfd_elf64_ia64_little_vec) tb="$tb elf64-ia64.lo elf64.lo $elf"
+ target64=true ;;
+ bfd_elf64_ia64_big_vec) tb="$tb elf64-ia64.lo elf64.lo $elf"
+ target64=true ;;
+ bfd_efi_app_ia32_vec) tb="$tb efi-app-ia32.lo cofflink.lo" ;;
+ bfd_efi_app_ia64_vec) tb="$tb efi-app-ia64.lo cofflink.lo"
+ target64=true ;;
bfd_elf32_avr_vec) tb="$tb elf32-avr.lo elf32.lo $elf" ;;
bfd_elf32_littlearc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
bfd_elf32_littlearm_vec) tb="$tb elfarm-nabi.lo elf32.lo $elf" ;;
hppa*-*-bsd*) HDEFINES=-DHOST_HPPABSD ;;
hppa*-*-osf*) HDEFINES=-DHOST_HPPAOSF ;;
+ia64-*-linux*) host64=true; HOST_64BIT_TYPE=long ;;
+
i[3456]86-sequent-bsd*) HDEFINES=-Dshared=genshared ;;
i[3456]86-sequent-sysv4*) ;;
i[3456]86-sequent-sysv*) HDEFINES=-Dshared=genshared ;;
target64=true ;;
bfd_elf64_alpha_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"
target64=true ;;
+ bfd_elf64_ia64_little_vec) tb="$tb elf64-ia64.lo elf64.lo $elf"
+ target64=true ;;
+ bfd_elf64_ia64_big_vec) tb="$tb elf64-ia64.lo elf64.lo $elf"
+ target64=true ;;
+ bfd_efi_app_ia32_vec) tb="$tb efi-app-ia32.lo cofflink.lo" ;;
+ bfd_efi_app_ia64_vec) tb="$tb efi-app-ia64.lo cofflink.lo"
+ target64=true ;;
bfd_elf32_avr_vec) tb="$tb elf32-avr.lo elf32.lo $elf" ;;
bfd_elf32_littlearc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
bfd_elf32_littlearm_vec) tb="$tb elfarm-nabi.lo elf32.lo $elf" ;;
--- /dev/null
+/* Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+
+/* Logically, this code should be part of libopcode but since some of
+ the operand insertion/extraction functions help bfd to implement
+ relocations, this code is included as part of elf64-ia64.c. This
+ avoids circular dependencies between libopcode and libbfd and also
+ obviates the need for applications to link in libopcode when all
+ they really want is libbfd.
+
+ --davidm Mon Apr 13 22:14:02 1998 */
+
+#include "../opcodes/ia64-opc.h"
+
+#define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0])))
+
+static const char*
+ins_rsvd (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ return "internal error---this shouldn't happen";
+}
+
+static const char*
+ext_rsvd (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ return "internal error---this shouldn't happen";
+}
+
+static const char*
+ins_const (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ return 0;
+}
+
+static const char*
+ext_const (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ return 0;
+}
+
+static const char*
+ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ if (value >= 1u << self->field[0].bits)
+ return "register number out of range";
+
+ *code |= value << self->field[0].shift;
+ return 0;
+}
+
+static const char*
+ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ *valuep = ((code >> self->field[0].shift)
+ & ((1u << self->field[0].bits) - 1));
+ return 0;
+}
+
+static const char*
+ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ ia64_insn new = 0;
+ int i;
+
+ for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
+ {
+ new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
+ << self->field[i].shift);
+ value >>= self->field[i].bits;
+ }
+ if (value)
+ return "integer operand out of range";
+
+ *code |= new;
+ return 0;
+}
+
+static const char*
+ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ BFD_HOST_U_64_BIT value = 0;
+ int i, bits = 0, total = 0;
+
+ for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
+ {
+ bits = self->field[i].bits;
+ value |= ((code >> self->field[i].shift)
+ & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
+ total += bits;
+ }
+ *valuep = value;
+ return 0;
+}
+
+static const char*
+ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ if (value & 0x7)
+ return "value not an integer multiple of 8";
+ return ins_immu (self, value >> 3, code);
+}
+
+static const char*
+ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ const char *result;
+
+ result = ext_immu (self, code, valuep);
+ if (result)
+ return result;
+
+ *valuep = *valuep << 3;
+ return 0;
+}
+
+static const char*
+ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
+ ia64_insn *code, int scale)
+{
+ BFD_HOST_64_BIT svalue = value, sign_bit;
+ ia64_insn new = 0;
+ int i;
+
+ svalue >>= scale;
+
+ for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
+ {
+ new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
+ << self->field[i].shift);
+ sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
+ svalue >>= self->field[i].bits;
+ }
+ if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
+ return "integer operand out of range";
+
+ *code |= new;
+ return 0;
+}
+
+static const char*
+ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
+ ia64_insn *valuep, int scale)
+{
+ int i, bits = 0, total = 0, shift;
+ BFD_HOST_64_BIT val = 0;
+
+ for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
+ {
+ bits = self->field[i].bits;
+ val |= ((code >> self->field[i].shift)
+ & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
+ total += bits;
+ }
+ /* sign extend: */
+ shift = 8*sizeof (val) - total;
+ val = (val << shift) >> shift;
+
+ *valuep = (val << scale);
+ return 0;
+}
+
+static const char*
+ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ return ins_imms_scaled (self, value, code, 0);
+}
+
+static const char*
+ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ if (value == (BFD_HOST_U_64_BIT) 0x100000000)
+ value = 0;
+ else
+ value = (((BFD_HOST_64_BIT)value << 32) >> 32);
+
+ return ins_imms_scaled (self, value, code, 0);
+}
+
+static const char*
+ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ return ext_imms_scaled (self, code, valuep, 0);
+}
+
+static const char*
+ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ --value;
+ return ins_imms_scaled (self, value, code, 0);
+}
+
+static const char*
+ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
+ ia64_insn *code)
+{
+ if (value == (BFD_HOST_U_64_BIT) 0x100000000)
+ value = 0;
+ else
+ value = (((BFD_HOST_64_BIT)value << 32) >> 32);
+
+ --value;
+ return ins_imms_scaled (self, value, code, 0);
+}
+
+static const char*
+ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ const char *res = ext_imms_scaled (self, code, valuep, 0);
+
+ ++*valuep;
+ return res;
+}
+
+static const char*
+ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ return ins_imms_scaled (self, value, code, 1);
+}
+
+static const char*
+ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ return ext_imms_scaled (self, code, valuep, 1);
+}
+
+static const char*
+ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ return ins_imms_scaled (self, value, code, 4);
+}
+
+static const char*
+ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ return ext_imms_scaled (self, code, valuep, 4);
+}
+
+static const char*
+ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ return ins_imms_scaled (self, value, code, 16);
+}
+
+static const char*
+ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ return ext_imms_scaled (self, code, valuep, 16);
+}
+
+static const char*
+ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
+ return ins_immu (self, value ^ mask, code);
+}
+
+static const char*
+ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ const char *result;
+ ia64_insn mask;
+
+ mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
+ result = ext_immu (self, code, valuep);
+ if (!result)
+ {
+ mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
+ *valuep ^= mask;
+ }
+ return result;
+}
+
+static const char*
+ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ --value;
+ if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
+ return "count out of range";
+
+ *code |= value << self->field[0].shift;
+ return 0;
+}
+
+static const char*
+ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ *valuep = ((code >> self->field[0].shift)
+ & ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
+ return 0;
+}
+
+static const char*
+ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ --value;
+
+ if (value > 2)
+ return "count must be in range 1..3";
+
+ *code |= value << self->field[0].shift;
+ return 0;
+}
+
+static const char*
+ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ *valuep = ((code >> self->field[0].shift) & 0x3) + 1;
+ return 0;
+}
+
+static const char*
+ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ switch (value)
+ {
+ case 0: value = 0; break;
+ case 7: value = 1; break;
+ case 15: value = 2; break;
+ case 16: value = 3; break;
+ default: return "count must be 0, 7, 15, or 16";
+ }
+ *code |= value << self->field[0].shift;
+ return 0;
+}
+
+static const char*
+ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ ia64_insn value;
+
+ value = (code >> self->field[0].shift) & 0x3;
+ switch (value)
+ {
+ case 0: value = 0; break;
+ case 1: value = 7; break;
+ case 2: value = 15; break;
+ case 3: value = 16; break;
+ }
+ *valuep = value;
+ return 0;
+}
+
+static const char*
+ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+ BFD_HOST_64_BIT val = value;
+ BFD_HOST_U_64_BIT sign = 0;
+
+ if (val < 0)
+ {
+ sign = 0x4;
+ value = -value;
+ }
+ switch (value)
+ {
+ case 1: value = 3; break;
+ case 4: value = 2; break;
+ case 8: value = 1; break;
+ case 16: value = 0; break;
+ default: return "count must be +/- 1, 4, 8, or 16";
+ }
+ *code |= (sign | value) << self->field[0].shift;
+ return 0;
+}
+
+static const char*
+ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+ BFD_HOST_64_BIT val;
+ int negate;
+
+ val = (code >> self->field[0].shift) & 0x7;
+ negate = val & 0x4;
+ switch (val & 0x3)
+ {
+ case 0: val = 16; break;
+ case 1: val = 8; break;
+ case 2: val = 4; break;
+ case 3: val = 1; break;
+ }
+ if (negate)
+ val = -val;
+
+ *valuep = val;
+ return 0;
+}
+
+#define CST IA64_OPND_CLASS_CST
+#define REG IA64_OPND_CLASS_REG
+#define IND IA64_OPND_CLASS_IND
+#define ABS IA64_OPND_CLASS_ABS
+#define REL IA64_OPND_CLASS_REL
+
+#define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED
+#define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED
+
+const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
+ {
+ /* constants: */
+ { CST, ins_const, ext_const, "NIL", {{ 0, }}, 0, "<none>" },
+ { CST, ins_const, ext_const, "ar.ccv", {{ 0, }}, 0, "ar.ccv" },
+ { CST, ins_const, ext_const, "ar.pfs", {{ 0, }}, 0, "ar.pfs" },
+ { CST, ins_const, ext_const, "1", {{ 0, }}, 0, "1" },
+ { CST, ins_const, ext_const, "8", {{ 0, }}, 0, "1" },
+ { CST, ins_const, ext_const, "16", {{ 0, }}, 0, "16" },
+ { CST, ins_const, ext_const, "r0", {{ 0, }}, 0, "r0" },
+ { CST, ins_const, ext_const, "ip", {{ 0, }}, 0, "ip" },
+ { CST, ins_const, ext_const, "pr", {{ 0, }}, 0, "pr" },
+ { CST, ins_const, ext_const, "pr.rot", {{ 0, }}, 0, "pr.rot" },
+ { CST, ins_const, ext_const, "psr", {{ 0, }}, 0, "psr" },
+ { CST, ins_const, ext_const, "psr.l", {{ 0, }}, 0, "psr.l" },
+ { CST, ins_const, ext_const, "psr.um", {{ 0, }}, 0, "psr.um" },
+
+ /* register operands: */
+ { REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
+ "an application register" },
+ { REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
+ "a branch register" },
+ { REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
+ "a branch register"},
+ { REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
+ "a control register"},
+ { REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
+ "a floating-point register" },
+ { REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
+ "a floating-point register" },
+ { REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
+ "a floating-point register" },
+ { REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
+ "a floating-point register" },
+ { REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
+ "a predicate register" },
+ { REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */
+ "a predicate register" },
+ { REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */
+ "a general register" },
+ { REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */
+ "a general register" },
+ { REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */
+ "a general register" },
+ { REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
+ "a general register r0-r3" },
+
+ /* indirect operands: */
+ { IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */
+ "a cpuid register" },
+ { IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */
+ "a dbr register" },
+ { IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */
+ "a dtr register" },
+ { IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */
+ "an itr register" },
+ { IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */
+ "an ibr register" },
+ { IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
+ "an indirect memory address" },
+ { IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */
+ "an msr register" },
+ { IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */
+ "a pkr register" },
+ { IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */
+ "a pmc register" },
+ { IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */
+ "a pmd register" },
+ { IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */
+ "an rr register" },
+
+ /* immediate operands: */
+ { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */
+ "a 5-bit count (0-31)" },
+ { ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */
+ "a 2-bit count (1-4)" },
+ { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */
+ "a 2-bit count (1-3)" },
+ { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */
+ "a count (0, 7, 15, or 16)" },
+ { ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */
+ "a 5-bit count (0-31)" },
+ { ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */
+ "a 6-bit count (0-63)" },
+ { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */
+ "a 6-bit bit pos (0-63)" },
+ { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */
+ "a 6-bit bit pos (0-63)" },
+ { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */
+ "a 6-bit bit pos (0-63)" },
+ { ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */
+ "a 1-bit integer (-1, 0)" },
+ { ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
+ "a 2-bit unsigned (0-3)" },
+ { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
+ "a 7-bit unsigned (0-127)" },
+ { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */
+ "a 7-bit unsigned (0-127)" },
+ { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */
+ "a frame size (register count)" },
+ { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */
+ "a local register count" },
+ { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */
+ "a rotating register count (integer multiple of 8)" },
+ { ABS, ins_imms, ext_imms, 0, /* IMM8 */
+ {{ 7, 13}, { 1, 36}}, SDEC,
+ "an 8-bit integer (-128-127)" },
+ { ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */
+ {{ 7, 13}, { 1, 36}}, SDEC,
+ "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
+ { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */
+ {{ 7, 13}, { 1, 36}}, SDEC,
+ "an 8-bit integer (-127-128)" },
+ { ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */
+ {{ 7, 13}, { 1, 36}}, SDEC,
+ "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
+ { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */
+ {{ 7, 13}, { 1, 36}}, SDEC,
+ "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
+ { ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */
+ "a 9-bit unsigned (0-511)" },
+ { ABS, ins_imms, ext_imms, 0, /* IMM9a */
+ {{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC,
+ "a 9-bit integer (-256-255)" },
+ { ABS, ins_imms, ext_imms, 0, /* IMM9b */
+ {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
+ "a 9-bit integer (-256-255)" },
+ { ABS, ins_imms, ext_imms, 0, /* IMM14 */
+ {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
+ "a 14-bit integer (-8192-8191)" },
+ { ABS, ins_imms1, ext_imms1, 0, /* IMM17 */
+ {{ 7, 6}, { 8, 24}, { 1, 36}}, 0,
+ "a 17-bit integer (-65536-65535)" },
+ { ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */
+ "a 21-bit unsigned" },
+ { ABS, ins_imms, ext_imms, 0, /* IMM22 */
+ {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
+ "a 22-bit integer" },
+ { ABS, ins_immu, ext_immu, 0, /* IMMU24 */
+ {{21, 6}, { 2, 31}, { 1, 36}}, 0,
+ "a 24-bit unsigned" },
+ { ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */
+ "a 44-bit unsigned (least 16 bits ignored/zeroes)" },
+ { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */
+ "a 62-bit unsigned" },
+ { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */
+ "a 64-bit unsigned" },
+ { ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */
+ "an increment (+/- 1, 4, 8, or 16)" },
+ { ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */
+ "a 4-bit length (1-16)" },
+ { ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */
+ "a 6-bit length (1-64)" },
+ { ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */
+ "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
+ { ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */
+ "an 8-bit mix type" },
+ { ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */
+ "a 6-bit bit pos (0-63)" },
+ { REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */
+ "a branch tag" },
+ { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */
+ "a branch tag" },
+ { REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */
+ "a branch target" },
+ { REL, ins_imms4, ext_imms4, 0, /* TGT25b */
+ {{ 7, 6}, {13, 20}, { 1, 36}}, 0,
+ "a branch target" },
+ { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */
+ "a branch target" },
+ { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */
+ "a branch target" },
+ };
--- /dev/null
+/* BFD support for the ia64 architecture.
+ Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+
+const bfd_arch_info_type bfd_ia64_arch =
+ {
+ 64, /* 64 bits in a word */
+ 64, /* 64 bits in an address */
+ 8, /* 8 bits in a byte */
+ bfd_arch_ia64,
+ 0, /* only 1 machine */
+ "ia64",
+ "ia64",
+ 3, /* log2 of section alignment */
+ true, /* the one and only */
+ bfd_default_compatible,
+ bfd_default_scan ,
+ 0,
+ };
+
+#include "cpu-ia64-opc.c"
case bfd_arch_i386:
i_ehdrp->e_machine = EM_386;
break;
+ case bfd_arch_ia64:
+ i_ehdrp->e_machine = EM_IA_64;
+ break;
case bfd_arch_m68k:
i_ehdrp->e_machine = EM_68K;
break;
--- /dev/null
+/* IA-64 support for 64-bit ELF
+ Copyright 1998, 1999 Free Software Foundation, Inc.
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "opcode/ia64.h"
+#include "elf/ia64.h"
+
+/*
+ * THE RULES for all the stuff the linker creates --
+ *
+ * GOT Entries created in response to LTOFF or LTOFF_FPTR
+ * relocations. Dynamic relocs created for dynamic
+ * symbols in an application; REL relocs for locals
+ * in a shared library.
+ *
+ * FPTR The canonical function descriptor. Created for local
+ * symbols in applications. Descriptors for dynamic symbols
+ * and local symbols in shared libraries are created by
+ * ld.so. Thus there are no dynamic relocs against these
+ * objects. The FPTR relocs for such _are_ passed through
+ * to the dynamic relocation tables.
+ *
+ * FULL_PLT Created for a PCREL21B relocation against a dynamic symbol.
+ * Requires the creation of a PLTOFF entry. This does not
+ * require any dynamic relocations.
+ *
+ * PLTOFF Created by PLTOFF relocations. For local symbols, this
+ * is an alternate function descriptor, and in shared libraries
+ * requires two REL relocations. Note that this cannot be
+ * transformed into an FPTR relocation, since it must be in
+ * range of the GP. For dynamic symbols, this is a function
+ * descriptor for a MIN_PLT entry, and requires one IPLT reloc.
+ *
+ * MIN_PLT Created by PLTOFF entries against dynamic symbols. This
+ * does not reqire dynamic relocations.
+ */
+
+#define USE_RELA /* we want RELA relocs, not REL */
+
+#define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0])))
+
+typedef struct bfd_hash_entry *(*new_hash_entry_func)
+ PARAMS ((struct bfd_hash_entry *, struct bfd_hash_table *, const char *));
+
+/* In dynamically (linker-) created sections, we generally need to keep track
+ of the place a symbol or expression got allocated to. This is done via hash
+ tables that store entries of the following type. */
+
+struct elf64_ia64_dyn_sym_info
+{
+ /* The addend for which this entry is relevant. */
+ bfd_vma addend;
+
+ /* Next addend in the list. */
+ struct elf64_ia64_dyn_sym_info *next;
+
+ bfd_vma got_offset;
+ bfd_vma fptr_offset;
+ bfd_vma pltoff_offset;
+ bfd_vma plt_offset;
+ bfd_vma plt2_offset;
+
+ /* The symbol table entry, if any, that this was derrived from. */
+ struct elf_link_hash_entry *h;
+
+ /* Used to count non-got, non-plt relocations for delayed sizing
+ of relocation sections. */
+ struct elf64_ia64_dyn_reloc_entry
+ {
+ struct elf64_ia64_dyn_reloc_entry *next;
+ asection *srel;
+ int type;
+ int count;
+ } *reloc_entries;
+
+ /* True when the section contents have been updated. */
+ unsigned got_done : 1;
+ unsigned fptr_done : 1;
+ unsigned pltoff_done : 1;
+
+ /* True for the different kinds of linker data we want created. */
+ unsigned want_got : 1;
+ unsigned want_fptr : 1;
+ unsigned want_ltoff_fptr : 1;
+ unsigned want_plt : 1;
+ unsigned want_plt2 : 1;
+ unsigned want_pltoff : 1;
+};
+
+struct elf64_ia64_local_hash_entry
+{
+ struct bfd_hash_entry root;
+ struct elf64_ia64_dyn_sym_info *info;
+};
+
+struct elf64_ia64_local_hash_table
+{
+ struct bfd_hash_table root;
+ /* No additional fields for now. */
+};
+
+struct elf64_ia64_link_hash_entry
+{
+ struct elf_link_hash_entry root;
+ struct elf64_ia64_dyn_sym_info *info;
+};
+
+struct elf64_ia64_link_hash_table
+{
+ /* The main hash table */
+ struct elf_link_hash_table root;
+
+ asection *got_sec; /* the linkage table section (or NULL) */
+ asection *rel_got_sec; /* dynamic relocation section for same */
+ asection *fptr_sec; /* function descriptor table (or NULL) */
+ asection *plt_sec; /* the primary plt section (or NULL) */
+ asection *pltoff_sec; /* private descriptors for plt (or NULL) */
+ asection *rel_pltoff_sec; /* dynamic relocation section for same */
+
+ bfd_size_type minplt_entries; /* number of minplt entries */
+
+ struct elf64_ia64_local_hash_table loc_hash_table;
+};
+
+#define elf64_ia64_hash_table(p) \
+ ((struct elf64_ia64_link_hash_table *) ((p)->hash))
+
+static bfd_reloc_status_type elf64_ia64_reloc
+ PARAMS ((bfd *abfd, arelent *reloc, asymbol *sym, PTR data,
+ asection *input_section, bfd *output_bfd, char **error_message));
+static reloc_howto_type * lookup_howto
+ PARAMS ((unsigned int rtype));
+static reloc_howto_type *elf64_ia64_reloc_type_lookup
+ PARAMS ((bfd *abfd, bfd_reloc_code_real_type bfd_code));
+static void elf64_ia64_info_to_howto
+ PARAMS ((bfd *abfd, arelent *bfd_reloc, Elf64_Internal_Rela *elf_reloc));
+static boolean elf64_ia64_section_from_shdr
+ PARAMS ((bfd *, Elf64_Internal_Shdr *, char *));
+static boolean elf64_ia64_fake_sections
+ PARAMS ((bfd *abfd, Elf64_Internal_Shdr *hdr, asection *sec));
+static boolean elf64_ia64_add_symbol_hook
+ PARAMS ((bfd *abfd, struct bfd_link_info *info, const Elf_Internal_Sym *sym,
+ const char **namep, flagword *flagsp, asection **secp,
+ bfd_vma *valp));
+static int elf64_ia64_additional_program_headers
+ PARAMS ((bfd *abfd));
+static boolean elf64_ia64_is_local_label_name
+ PARAMS ((bfd *abfd, const char *name));
+static boolean elf64_ia64_dynamic_symbol_p
+ PARAMS ((struct elf_link_hash_entry *h, struct bfd_link_info *info));
+static boolean elf64_ia64_local_hash_table_init
+ PARAMS ((struct elf64_ia64_local_hash_table *ht, bfd *abfd,
+ new_hash_entry_func new));
+static struct bfd_hash_entry *elf64_ia64_new_loc_hash_entry
+ PARAMS ((struct bfd_hash_entry *entry, struct bfd_hash_table *table,
+ const char *string));
+static struct bfd_hash_entry *elf64_ia64_new_elf_hash_entry
+ PARAMS ((struct bfd_hash_entry *entry, struct bfd_hash_table *table,
+ const char *string));
+static struct bfd_link_hash_table *elf64_ia64_hash_table_create
+ PARAMS ((bfd *abfd));
+static struct elf64_ia64_local_hash_entry *elf64_ia64_local_hash_lookup
+ PARAMS ((struct elf64_ia64_local_hash_table *table, const char *string,
+ boolean create, boolean copy));
+static void elf64_ia64_dyn_sym_traverse
+ PARAMS ((struct elf64_ia64_link_hash_table *ia64_info,
+ boolean (*func)(struct elf64_ia64_dyn_sym_info *, PTR),
+ PTR info));
+static boolean elf64_ia64_create_dynamic_sections
+ PARAMS ((bfd *abfd, struct bfd_link_info *info));
+static struct elf64_ia64_dyn_sym_info * get_dyn_sym_info
+ PARAMS ((struct elf64_ia64_link_hash_table *ia64_info,
+ struct elf_link_hash_entry *h,
+ bfd *abfd, const Elf_Internal_Rela *rel, boolean create));
+static asection *get_got
+ PARAMS ((bfd *abfd, struct bfd_link_info *info,
+ struct elf64_ia64_link_hash_table *ia64_info));
+static asection *get_fptr
+ PARAMS ((bfd *abfd, struct bfd_link_info *info,
+ struct elf64_ia64_link_hash_table *ia64_info));
+static asection *get_pltoff
+ PARAMS ((bfd *abfd, struct bfd_link_info *info,
+ struct elf64_ia64_link_hash_table *ia64_info));
+static asection *get_reloc_section
+ PARAMS ((bfd *abfd, struct elf64_ia64_link_hash_table *ia64_info,
+ asection *sec, boolean create));
+static boolean count_dyn_reloc
+ PARAMS ((bfd *abfd, struct elf64_ia64_dyn_sym_info *dyn_i,
+ asection *srel, int type));
+static boolean elf64_ia64_check_relocs
+ PARAMS ((bfd *abfd, struct bfd_link_info *info, asection *sec,
+ const Elf_Internal_Rela *relocs));
+static boolean elf64_ia64_adjust_dynamic_symbol
+ PARAMS ((struct bfd_link_info *info, struct elf_link_hash_entry *h));
+static unsigned long global_sym_index
+ PARAMS ((struct elf_link_hash_entry *h));
+static boolean allocate_fptr
+ PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_global_data_got
+ PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_global_fptr_got
+ PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_local_got
+ PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_pltoff_entries
+ PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_plt_entries
+ PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_plt2_entries
+ PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_dynrel_entries
+ PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean elf64_ia64_size_dynamic_sections
+ PARAMS ((bfd *output_bfd, struct bfd_link_info *info));
+static bfd_reloc_status_type elf64_ia64_install_value
+ PARAMS ((bfd *abfd, bfd_byte *hit_addr, bfd_vma val, unsigned int r_type));
+static void elf64_ia64_install_dyn_reloc
+ PARAMS ((bfd *abfd, struct bfd_link_info *info, asection *sec,
+ asection *srel, bfd_vma offset, unsigned int type,
+ long dynindx, bfd_vma addend));
+static bfd_vma set_got_entry
+ PARAMS ((bfd *abfd, struct bfd_link_info *info,
+ struct elf64_ia64_dyn_sym_info *dyn_i, long dynindx,
+ bfd_vma addend, bfd_vma value, unsigned int dyn_r_type));
+static bfd_vma set_fptr_entry
+ PARAMS ((bfd *abfd, struct bfd_link_info *info,
+ struct elf64_ia64_dyn_sym_info *dyn_i,
+ bfd_vma value));
+static bfd_vma set_pltoff_entry
+ PARAMS ((bfd *abfd, struct bfd_link_info *info,
+ struct elf64_ia64_dyn_sym_info *dyn_i,
+ bfd_vma value, boolean));
+static boolean elf64_ia64_final_link
+ PARAMS ((bfd *abfd, struct bfd_link_info *info));
+static boolean elf64_ia64_relocate_section
+ PARAMS ((bfd *output_bfd, struct bfd_link_info *info, bfd *input_bfd,
+ asection *input_section, bfd_byte *contents,
+ Elf_Internal_Rela *relocs, Elf_Internal_Sym *local_syms,
+ asection **local_sections));
+static boolean elf64_ia64_finish_dynamic_symbol
+ PARAMS ((bfd *output_bfd, struct bfd_link_info *info,
+ struct elf_link_hash_entry *h, Elf_Internal_Sym *sym));
+static boolean elf64_ia64_finish_dynamic_sections
+ PARAMS ((bfd *abfd, struct bfd_link_info *info));
+static boolean elf64_ia64_set_private_flags
+ PARAMS ((bfd *abfd, flagword flags));
+static boolean elf64_ia64_copy_private_bfd_data
+ PARAMS ((bfd *ibfd, bfd *obfd));
+static boolean elf64_ia64_merge_private_bfd_data
+ PARAMS ((bfd *ibfd, bfd *obfd));
+static boolean elf64_ia64_print_private_bfd_data
+ PARAMS ((bfd *abfd, PTR ptr));
+
+\f
+/* ia64-specific relocation */
+
+/* Perform a relocation. Not much to do here as all the hard work is
+ done in elf64_ia64_final_link_relocate. */
+static bfd_reloc_status_type
+elf64_ia64_reloc (abfd, reloc, sym, data, input_section,
+ output_bfd, error_message)
+ bfd *abfd;
+ arelent *reloc;
+ asymbol *sym;
+ PTR data;
+ asection *input_section;
+ bfd *output_bfd;
+ char **error_message;
+{
+ if (output_bfd)
+ {
+ reloc->address += input_section->output_offset;
+ return bfd_reloc_ok;
+ }
+ *error_message = "Unsupported call to elf64_ia64_reloc";
+ return bfd_reloc_notsupported;
+}
+
+#define IA64_HOWTO(TYPE, NAME, SIZE, PCREL, IN) \
+ HOWTO (TYPE, 0, SIZE, 0, PCREL, 0, complain_overflow_signed, \
+ elf64_ia64_reloc, NAME, false, 0, 0, IN)
+
+/* This table has to be sorted according to increasing number of the
+ TYPE field. */
+static reloc_howto_type ia64_howto_table[] =
+ {
+ IA64_HOWTO (R_IA64_NONE, "NONE", 0, false, true),
+
+ IA64_HOWTO (R_IA64_IMM14, "IMM14", 0, false, true),
+ IA64_HOWTO (R_IA64_IMM22, "IMM22", 0, false, true),
+ IA64_HOWTO (R_IA64_IMM64, "IMM64", 0, false, true),
+ IA64_HOWTO (R_IA64_DIR32MSB, "DIR32MSB", 2, false, true),
+ IA64_HOWTO (R_IA64_DIR32LSB, "DIR32LSB", 2, false, true),
+ IA64_HOWTO (R_IA64_DIR64MSB, "DIR64MSB", 4, false, true),
+ IA64_HOWTO (R_IA64_DIR64LSB, "DIR64LSB", 4, false, true),
+
+ IA64_HOWTO (R_IA64_GPREL22, "GPREL22", 0, false, true),
+ IA64_HOWTO (R_IA64_GPREL64I, "GPREL64I", 0, false, true),
+ IA64_HOWTO (R_IA64_GPREL32MSB, "GPREL32MSB", 2, false, true),
+ IA64_HOWTO (R_IA64_GPREL32LSB, "GPREL32LSB", 2, false, true),
+ IA64_HOWTO (R_IA64_GPREL64MSB, "GPREL64MSB", 4, false, true),
+ IA64_HOWTO (R_IA64_GPREL64LSB, "GPREL64LSB", 4, false, true),
+
+ IA64_HOWTO (R_IA64_LTOFF22, "LTOFF22", 0, false, true),
+ IA64_HOWTO (R_IA64_LTOFF64I, "LTOFF64I", 0, false, true),
+
+ IA64_HOWTO (R_IA64_PLTOFF22, "PLTOFF22", 0, false, true),
+ IA64_HOWTO (R_IA64_PLTOFF64I, "PLTOFF64I", 0, false, true),
+ IA64_HOWTO (R_IA64_PLTOFF64MSB, "PLTOFF64MSB", 4, false, true),
+ IA64_HOWTO (R_IA64_PLTOFF64LSB, "PLTOFF64LSB", 4, false, true),
+
+ IA64_HOWTO (R_IA64_FPTR64I, "FPTR64I", 4, false, true),
+ IA64_HOWTO (R_IA64_FPTR32MSB, "FPTR32MSB", 2, false, true),
+ IA64_HOWTO (R_IA64_FPTR32LSB, "FPTR32LSB", 2, false, true),
+ IA64_HOWTO (R_IA64_FPTR64MSB, "FPTR64MSB", 4, false, true),
+ IA64_HOWTO (R_IA64_FPTR64LSB, "FPTR64LSB", 4, false, true),
+
+ IA64_HOWTO (R_IA64_PCREL21B, "PCREL21B", 0, true, true),
+ IA64_HOWTO (R_IA64_PCREL21M, "PCREL21M", 0, true, true),
+ IA64_HOWTO (R_IA64_PCREL21F, "PCREL21F", 0, true, true),
+ IA64_HOWTO (R_IA64_PCREL32MSB, "PCREL32MSB", 2, true, true),
+ IA64_HOWTO (R_IA64_PCREL32LSB, "PCREL32LSB", 2, true, true),
+ IA64_HOWTO (R_IA64_PCREL64MSB, "PCREL64MSB", 4, true, true),
+ IA64_HOWTO (R_IA64_PCREL64LSB, "PCREL64LSB", 4, true, true),
+
+ IA64_HOWTO (R_IA64_LTOFF_FPTR22, "LTOFF_FPTR22", 4, false, true),
+ IA64_HOWTO (R_IA64_LTOFF_FPTR64I, "LTOFF_FPTR64I", 4, false, true),
+ IA64_HOWTO (R_IA64_LTOFF_FPTR64MSB, "LTOFF_FPTR64MSB", 4, false, true),
+ IA64_HOWTO (R_IA64_LTOFF_FPTR64LSB, "LTOFF_FPTR64LSB", 4, false, true),
+
+ IA64_HOWTO (R_IA64_SEGBASE, "SEGBASE", 4, false, true),
+ IA64_HOWTO (R_IA64_SEGREL32MSB, "SEGREL32MSB", 2, false, true),
+ IA64_HOWTO (R_IA64_SEGREL32LSB, "SEGREL32LSB", 2, false, true),
+ IA64_HOWTO (R_IA64_SEGREL64MSB, "SEGREL64MSB", 4, false, true),
+ IA64_HOWTO (R_IA64_SEGREL64LSB, "SEGREL64LSB", 4, false, true),
+
+ IA64_HOWTO (R_IA64_SECREL32MSB, "SECREL32MSB", 2, false, true),
+ IA64_HOWTO (R_IA64_SECREL32LSB, "SECREL32LSB", 2, false, true),
+ IA64_HOWTO (R_IA64_SECREL64MSB, "SECREL64MSB", 4, false, true),
+ IA64_HOWTO (R_IA64_SECREL64LSB, "SECREL64LSB", 4, false, true),
+
+ IA64_HOWTO (R_IA64_REL32MSB, "REL32MSB", 2, false, true),
+ IA64_HOWTO (R_IA64_REL32LSB, "REL32LSB", 2, false, true),
+ IA64_HOWTO (R_IA64_REL64MSB, "REL64MSB", 4, false, true),
+ IA64_HOWTO (R_IA64_REL64LSB, "REL64LSB", 4, false, true),
+
+ IA64_HOWTO (R_IA64_LTV32MSB, "LTV32MSB", 2, false, true),
+ IA64_HOWTO (R_IA64_LTV32LSB, "LTV32LSB", 2, false, true),
+ IA64_HOWTO (R_IA64_LTV64MSB, "LTV64MSB", 4, false, true),
+ IA64_HOWTO (R_IA64_LTV64LSB, "LTV64LSB", 4, false, true),
+
+ IA64_HOWTO (R_IA64_IPLTMSB, "IPLTMSB", 4, false, true),
+ IA64_HOWTO (R_IA64_IPLTLSB, "IPLTLSB", 4, false, true),
+ IA64_HOWTO (R_IA64_EPLTMSB, "EPLTMSB", 4, false, true),
+ IA64_HOWTO (R_IA64_EPLTLSB, "EPLTLSB", 4, false, true),
+ IA64_HOWTO (R_IA64_COPY, "COPY", 4, false, true),
+ IA64_HOWTO (R_IA64_LTOFF22X, "LTOFF22X", 0, false, true),
+ IA64_HOWTO (R_IA64_LDXMOV, "LDXMOV", 0, false, true),
+
+ IA64_HOWTO (R_IA64_TPREL22, "TPREL22", 4, false, false),
+ IA64_HOWTO (R_IA64_TPREL64MSB, "TPREL64MSB", 8, false, false),
+ IA64_HOWTO (R_IA64_TPREL64LSB, "TPREL64LSB", 8, false, false),
+ IA64_HOWTO (R_IA64_LTOFF_TP22, "LTOFF_TP22", 4, false, false),
+ };
+
+static unsigned char elf_code_to_howto_index[R_IA64_MAX_RELOC_CODE + 1];
+
+/* Given a BFD reloc type, return the matching HOWTO structure. */
+
+static reloc_howto_type*
+lookup_howto (rtype)
+ unsigned int rtype;
+{
+ static int inited = 0;
+ int i;
+
+ if (!inited)
+ {
+ inited = 1;
+
+ memset (elf_code_to_howto_index, 0xff, sizeof (elf_code_to_howto_index));
+ for (i = 0; i < NELEMS (ia64_howto_table); ++i)
+ elf_code_to_howto_index[ia64_howto_table[i].type] = i;
+ }
+
+ BFD_ASSERT (rtype <= R_IA64_MAX_RELOC_CODE);
+ i = elf_code_to_howto_index[rtype];
+ if (i >= NELEMS (ia64_howto_table))
+ return 0;
+ return ia64_howto_table + i;
+}
+
+static reloc_howto_type*
+elf64_ia64_reloc_type_lookup (abfd, bfd_code)
+ bfd *abfd;
+ bfd_reloc_code_real_type bfd_code;
+{
+ unsigned int rtype;
+
+ switch (bfd_code)
+ {
+ case BFD_RELOC_NONE: rtype = R_IA64_NONE; break;
+
+ case BFD_RELOC_IA64_IMM14: rtype = R_IA64_IMM14; break;
+ case BFD_RELOC_IA64_IMM22: rtype = R_IA64_IMM22; break;
+ case BFD_RELOC_IA64_IMM64: rtype = R_IA64_IMM64; break;
+
+ case BFD_RELOC_IA64_DIR32MSB: rtype = R_IA64_DIR32MSB; break;
+ case BFD_RELOC_IA64_DIR32LSB: rtype = R_IA64_DIR32LSB; break;
+ case BFD_RELOC_IA64_DIR64MSB: rtype = R_IA64_DIR64MSB; break;
+ case BFD_RELOC_IA64_DIR64LSB: rtype = R_IA64_DIR64LSB; break;
+
+ case BFD_RELOC_IA64_GPREL22: rtype = R_IA64_GPREL22; break;
+ case BFD_RELOC_IA64_GPREL64I: rtype = R_IA64_GPREL64I; break;
+ case BFD_RELOC_IA64_GPREL32MSB: rtype = R_IA64_GPREL32MSB; break;
+ case BFD_RELOC_IA64_GPREL32LSB: rtype = R_IA64_GPREL32LSB; break;
+ case BFD_RELOC_IA64_GPREL64MSB: rtype = R_IA64_GPREL64MSB; break;
+ case BFD_RELOC_IA64_GPREL64LSB: rtype = R_IA64_GPREL64LSB; break;
+
+ case BFD_RELOC_IA64_LTOFF22: rtype = R_IA64_LTOFF22; break;
+ case BFD_RELOC_IA64_LTOFF64I: rtype = R_IA64_LTOFF64I; break;
+
+ case BFD_RELOC_IA64_PLTOFF22: rtype = R_IA64_PLTOFF22; break;
+ case BFD_RELOC_IA64_PLTOFF64I: rtype = R_IA64_PLTOFF64I; break;
+ case BFD_RELOC_IA64_PLTOFF64MSB: rtype = R_IA64_PLTOFF64MSB; break;
+ case BFD_RELOC_IA64_PLTOFF64LSB: rtype = R_IA64_PLTOFF64LSB; break;
+ case BFD_RELOC_IA64_FPTR64I: rtype = R_IA64_FPTR64I; break;
+ case BFD_RELOC_IA64_FPTR32MSB: rtype = R_IA64_FPTR32MSB; break;
+ case BFD_RELOC_IA64_FPTR32LSB: rtype = R_IA64_FPTR32LSB; break;
+ case BFD_RELOC_IA64_FPTR64MSB: rtype = R_IA64_FPTR64MSB; break;
+ case BFD_RELOC_IA64_FPTR64LSB: rtype = R_IA64_FPTR64LSB; break;
+
+ case BFD_RELOC_IA64_PCREL21B: rtype = R_IA64_PCREL21B; break;
+ case BFD_RELOC_IA64_PCREL21M: rtype = R_IA64_PCREL21M; break;
+ case BFD_RELOC_IA64_PCREL21F: rtype = R_IA64_PCREL21F; break;
+ case BFD_RELOC_IA64_PCREL32MSB: rtype = R_IA64_PCREL32MSB; break;
+ case BFD_RELOC_IA64_PCREL32LSB: rtype = R_IA64_PCREL32LSB; break;
+ case BFD_RELOC_IA64_PCREL64MSB: rtype = R_IA64_PCREL64MSB; break;
+ case BFD_RELOC_IA64_PCREL64LSB: rtype = R_IA64_PCREL64LSB; break;
+
+ case BFD_RELOC_IA64_LTOFF_FPTR22: rtype = R_IA64_LTOFF_FPTR22; break;
+ case BFD_RELOC_IA64_LTOFF_FPTR64I: rtype = R_IA64_LTOFF_FPTR64I; break;
+ case BFD_RELOC_IA64_LTOFF_FPTR64MSB: rtype = R_IA64_LTOFF_FPTR64MSB; break;
+ case BFD_RELOC_IA64_LTOFF_FPTR64LSB: rtype = R_IA64_LTOFF_FPTR64LSB; break;
+
+ case BFD_RELOC_IA64_SEGBASE: rtype = R_IA64_SEGBASE; break;
+ case BFD_RELOC_IA64_SEGREL32MSB: rtype = R_IA64_SEGREL32MSB; break;
+ case BFD_RELOC_IA64_SEGREL32LSB: rtype = R_IA64_SEGREL32LSB; break;
+ case BFD_RELOC_IA64_SEGREL64MSB: rtype = R_IA64_SEGREL64MSB; break;
+ case BFD_RELOC_IA64_SEGREL64LSB: rtype = R_IA64_SEGREL64LSB; break;
+
+ case BFD_RELOC_IA64_SECREL32MSB: rtype = R_IA64_SECREL32MSB; break;
+ case BFD_RELOC_IA64_SECREL32LSB: rtype = R_IA64_SECREL32LSB; break;
+ case BFD_RELOC_IA64_SECREL64MSB: rtype = R_IA64_SECREL64MSB; break;
+ case BFD_RELOC_IA64_SECREL64LSB: rtype = R_IA64_SECREL64LSB; break;
+
+ case BFD_RELOC_IA64_REL32MSB: rtype = R_IA64_REL32MSB; break;
+ case BFD_RELOC_IA64_REL32LSB: rtype = R_IA64_REL32LSB; break;
+ case BFD_RELOC_IA64_REL64MSB: rtype = R_IA64_REL64MSB; break;
+ case BFD_RELOC_IA64_REL64LSB: rtype = R_IA64_REL64LSB; break;
+
+ case BFD_RELOC_IA64_LTV32MSB: rtype = R_IA64_LTV32MSB; break;
+ case BFD_RELOC_IA64_LTV32LSB: rtype = R_IA64_LTV32LSB; break;
+ case BFD_RELOC_IA64_LTV64MSB: rtype = R_IA64_LTV64MSB; break;
+ case BFD_RELOC_IA64_LTV64LSB: rtype = R_IA64_LTV64LSB; break;
+
+ case BFD_RELOC_IA64_IPLTMSB: rtype = R_IA64_IPLTMSB; break;
+ case BFD_RELOC_IA64_IPLTLSB: rtype = R_IA64_IPLTLSB; break;
+ case BFD_RELOC_IA64_EPLTMSB: rtype = R_IA64_EPLTMSB; break;
+ case BFD_RELOC_IA64_EPLTLSB: rtype = R_IA64_EPLTLSB; break;
+ case BFD_RELOC_IA64_COPY: rtype = R_IA64_COPY; break;
+ case BFD_RELOC_IA64_LTOFF22X: rtype = R_IA64_LTOFF22X; break;
+ case BFD_RELOC_IA64_LDXMOV: rtype = R_IA64_LDXMOV; break;
+
+ case BFD_RELOC_IA64_TPREL22: rtype = R_IA64_TPREL22; break;
+ case BFD_RELOC_IA64_TPREL64MSB: rtype = R_IA64_TPREL64MSB; break;
+ case BFD_RELOC_IA64_TPREL64LSB: rtype = R_IA64_TPREL64LSB; break;
+ case BFD_RELOC_IA64_LTOFF_TP22: rtype = R_IA64_LTOFF_TP22; break;
+
+ default: return 0;
+ }
+ return lookup_howto (rtype);
+}
+
+/* Given a ELF reloc, return the matching HOWTO structure. */
+
+static void
+elf64_ia64_info_to_howto (abfd, bfd_reloc, elf_reloc)
+ bfd *abfd;
+ arelent *bfd_reloc;
+ Elf64_Internal_Rela *elf_reloc;
+{
+ bfd_reloc->howto = lookup_howto (ELF64_R_TYPE (elf_reloc->r_info));
+}
+\f
+#define PLT_HEADER_SIZE (3 * 16)
+#define PLT_MIN_ENTRY_SIZE (1 * 16)
+#define PLT_FULL_ENTRY_SIZE (2 * 16)
+#define PLT_RESERVED_WORDS 3
+
+static const bfd_byte plt_header[PLT_HEADER_SIZE] =
+{
+ 0x0b, 0x10, 0x00, 0x1c, 0x00, 0x21, /* [MMI] mov r2=r14;; */
+ 0xe0, 0x00, 0x08, 0x00, 0x48, 0x00, /* addl r14=0,r2 */
+ 0x00, 0x00, 0x04, 0x00, /* nop.i 0x0;; */
+ 0x0b, 0x80, 0x20, 0x1c, 0x18, 0x14, /* [MMI] ld8 r16=[r14],8;; */
+ 0x10, 0x41, 0x38, 0x30, 0x28, 0x00, /* ld8 r17=[r14],8 */
+ 0x00, 0x00, 0x04, 0x00, /* nop.i 0x0;; */
+ 0x11, 0x08, 0x00, 0x1c, 0x18, 0x10, /* [MIB] ld8 r1=[r14] */
+ 0x60, 0x88, 0x04, 0x80, 0x03, 0x00, /* mov b6=r17 */
+ 0x60, 0x00, 0x80, 0x00 /* br.few b6;; */
+};
+
+static const bfd_byte plt_min_entry[PLT_MIN_ENTRY_SIZE] =
+{
+ 0x11, 0x78, 0x00, 0x00, 0x00, 0x24, /* [MIB] mov r15=0 */
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, /* nop.i 0x0 */
+ 0x00, 0x00, 0x00, 0x40 /* br.few 0 <PLT0>;; */
+};
+
+static const bfd_byte plt_full_entry[PLT_FULL_ENTRY_SIZE] =
+{
+ 0x0b, 0x78, 0x00, 0x02, 0x00, 0x24, /* [MMI] addl r15=0,r1;; */
+ 0x00, 0x41, 0x3c, 0x30, 0x28, 0xc0, /* ld8 r16=[r15],8 */
+ 0x01, 0x08, 0x00, 0x84, /* mov r14=r1;; */
+ 0x11, 0x08, 0x00, 0x1e, 0x18, 0x10, /* [MIB] ld8 r1=[r15] */
+ 0x60, 0x80, 0x04, 0x80, 0x03, 0x00, /* mov b6=r16 */
+ 0x60, 0x00, 0x80, 0x00 /* br.few b6;; */
+};
+
+#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
+\f
+/* Handle an IA-64 specific section when reading an object file. This
+ is called when elfcode.h finds a section with an unknown type. */
+
+static boolean
+elf64_ia64_section_from_shdr (abfd, hdr, name)
+ bfd *abfd;
+ Elf64_Internal_Shdr *hdr;
+ char *name;
+{
+ asection *newsect;
+
+ /* There ought to be a place to keep ELF backend specific flags, but
+ at the moment there isn't one. We just keep track of the
+ sections by their name, instead. Fortunately, the ABI gives
+ suggested names for all the MIPS specific sections, so we will
+ probably get away with this. */
+ switch (hdr->sh_type)
+ {
+ case SHT_IA_64_UNWIND:
+ if (strcmp (name, ELF_STRING_ia64_unwind) != 0)
+ return false;
+ break;
+
+ case SHT_IA_64_EXT:
+ if (strcmp (name, ELF_STRING_ia64_archext) != 0)
+ return false;
+ break;
+
+ default:
+ return false;
+ }
+
+ if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name))
+ return false;
+ newsect = hdr->bfd_section;
+
+ if (hdr->sh_flags & SHF_IA_64_SHORT)
+ newsect->flags |= SEC_SMALL_DATA;
+
+ return true;
+}
+
+/* Set the correct type for an IA-64 ELF section. We do this by the
+ section name, which is a hack, but ought to work. */
+
+static boolean
+elf64_ia64_fake_sections (abfd, hdr, sec)
+ bfd *abfd;
+ Elf64_Internal_Shdr *hdr;
+ asection *sec;
+{
+ register const char *name;
+
+ name = bfd_get_section_name (abfd, sec);
+
+ if (strcmp (name, ELF_STRING_ia64_unwind) == 0)
+ hdr->sh_type = SHT_IA_64_UNWIND;
+ else if (strcmp (name, ELF_STRING_ia64_archext) == 0)
+ hdr->sh_type = SHT_IA_64_EXT;
+ else if (strcmp (name, ".reloc") == 0)
+ /*
+ * This is an ugly, but unfortunately necessary hack that is
+ * needed when producing EFI binaries on IA-64. It tells
+ * elf.c:elf_fake_sections() not to consider ".reloc" as a section
+ * containing ELF relocation info. We need this hack in order to
+ * be able to generate ELF binaries that can be translated into
+ * EFI applications (which are essentially COFF objects). Those
+ * files contain a COFF ".reloc" section inside an ELF64 object,
+ * which would normally cause BFD to segfault because it would
+ * attempt to interpret this section as containing relocation
+ * entries for section "oc". With this hack enabled, ".reloc"
+ * will be treated as a normal data section, which will avoid the
+ * segfault. However, you won't be able to create an ELF64 binary
+ * with a section named "oc" that needs relocations, but that's
+ * the kind of ugly side-effects you get when detecting section
+ * types based on their names... In practice, this limitation is
+ * unlikely to bite.
+ */
+ hdr->sh_type = SHT_PROGBITS;
+
+ if (sec->flags & SEC_SMALL_DATA)
+ hdr->sh_flags |= SHF_IA_64_SHORT;
+
+ return true;
+}
+
+/* Hook called by the linker routine which adds symbols from an object
+ file. We use it to put .comm items in .sbss, and not .bss. */
+
+static boolean
+elf64_ia64_add_symbol_hook (abfd, info, sym, namep, flagsp, secp, valp)
+ bfd *abfd;
+ struct bfd_link_info *info;
+ const Elf_Internal_Sym *sym;
+ const char **namep;
+ flagword *flagsp;
+ asection **secp;
+ bfd_vma *valp;
+{
+ if (sym->st_shndx == SHN_COMMON
+ && !info->relocateable
+ && sym->st_size <= bfd_get_gp_size (abfd))
+ {
+ /* Common symbols less than or equal to -G nn bytes are
+ automatically put into .sbss. */
+
+ asection *scomm = bfd_get_section_by_name (abfd, ".scommon");
+
+ if (scomm == NULL)
+ {
+ scomm = bfd_make_section (abfd, ".scommon");
+ if (scomm == NULL
+ || !bfd_set_section_flags (abfd, scomm, (SEC_ALLOC
+ | SEC_IS_COMMON
+ | SEC_LINKER_CREATED)))
+ return false;
+ }
+
+ *secp = scomm;
+ *valp = sym->st_size;
+ }
+
+ return true;
+}
+
+/* Return the number of additional phdrs we will need. */
+
+static int
+elf64_ia64_additional_program_headers (abfd)
+ bfd *abfd;
+{
+ asection *s;
+ int ret = 0;
+
+ /* See if we need a PT_IA_64_ARCHEXT segment. */
+ s = bfd_get_section_by_name (abfd, ELF_STRING_ia64_archext);
+ if (s && (s->flags & SEC_LOAD))
+ ++ret;
+
+ /* See if we need a PT_IA_64_UNWIND segment. */
+ s = bfd_get_section_by_name (abfd, ELF_STRING_ia64_unwind);
+ if (s && (s->flags & SEC_LOAD))
+ ++ret;
+
+ return ret;
+}
+
+static boolean
+elf64_ia64_modify_segment_map (abfd)
+ bfd *abfd;
+{
+ struct elf_segment_map *m, **pm;
+ asection *s;
+
+ /* If we need a PT_IA_64_ARCHEXT segment, it must come before
+ all PT_LOAD segments. */
+ s = bfd_get_section_by_name (abfd, ELF_STRING_ia64_archext);
+ if (s && (s->flags & SEC_LOAD))
+ {
+ for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next)
+ if (m->p_type == PT_IA_64_ARCHEXT)
+ break;
+ if (m == NULL)
+ {
+ m = (struct elf_segment_map *) bfd_zalloc (abfd, sizeof *m);
+ if (m == NULL)
+ return false;
+
+ m->p_type = PT_IA_64_ARCHEXT;
+ m->count = 1;
+ m->sections[0] = s;
+
+ /* We want to put it after the PHDR and INTERP segments. */
+ pm = &elf_tdata (abfd)->segment_map;
+ while (*pm != NULL
+ && ((*pm)->p_type == PT_PHDR
+ || (*pm)->p_type == PT_INTERP))
+ pm = &(*pm)->next;
+
+ m->next = *pm;
+ *pm = m;
+ }
+ }
+
+ /* Install the PT_IA_64_UNWIND segment, if needed. */
+ s = bfd_get_section_by_name (abfd, ELF_STRING_ia64_unwind);
+ if (s && (s->flags & SEC_LOAD))
+ {
+ for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next)
+ if (m->p_type == PT_IA_64_UNWIND)
+ break;
+ if (m == NULL)
+ {
+ m = (struct elf_segment_map *) bfd_zalloc (abfd, sizeof *m);
+ if (m == NULL)
+ return false;
+
+ m->p_type = PT_IA_64_UNWIND;
+ m->count = 1;
+ m->sections[0] = s;
+ m->next = NULL;
+
+ /* We want to put it last. */
+ pm = &elf_tdata (abfd)->segment_map;
+ while (*pm != NULL)
+ pm = &(*pm)->next;
+ *pm = m;
+ }
+ }
+
+ /* Turn on PF_IA_64_NORECOV if needed. This involves traversing all of
+ the input sections for each output section in the segment and testing
+ for SHF_IA_64_NORECOV on each. */
+ for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next)
+ if (m->p_type == PT_LOAD)
+ {
+ int i;
+ for (i = m->count - 1; i >= 0; --i)
+ {
+ struct bfd_link_order *order = m->sections[i]->link_order_head;
+ while (order)
+ {
+ if (order->type == bfd_indirect_link_order)
+ {
+ asection *is = order->u.indirect.section;
+ bfd_vma flags = elf_section_data(is)->this_hdr.sh_flags;
+ if (flags & SHF_IA_64_NORECOV)
+ {
+ m->p_flags |= PF_IA_64_NORECOV;
+ goto found;
+ }
+ }
+ order = order->next;
+ }
+ }
+ found:;
+ }
+
+ return true;
+}
+
+
+/* According to the Tahoe assembler spec, all labels starting with a
+ '.' are local. */
+
+static boolean
+elf64_ia64_is_local_label_name (abfd, name)
+ bfd *abfd;
+ const char *name;
+{
+ return name[0] == '.';
+}
+
+/* Should we do dynamic things to this symbol? */
+
+static boolean
+elf64_ia64_dynamic_symbol_p (h, info)
+ struct elf_link_hash_entry *h;
+ struct bfd_link_info *info;
+{
+ if (h == NULL)
+ return false;
+
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+ if (h->dynindx == -1)
+ return false;
+
+ if (h->root.type == bfd_link_hash_undefweak
+ || h->root.type == bfd_link_hash_defweak)
+ return true;
+
+ if ((info->shared && !info->symbolic)
+ || ((h->elf_link_hash_flags
+ & (ELF_LINK_HASH_DEF_DYNAMIC | ELF_LINK_HASH_REF_REGULAR))
+ == (ELF_LINK_HASH_DEF_DYNAMIC | ELF_LINK_HASH_REF_REGULAR)))
+ return true;
+
+ return false;
+}
+\f
+static boolean
+elf64_ia64_local_hash_table_init (ht, abfd, new)
+ struct elf64_ia64_local_hash_table *ht;
+ bfd *abfd;
+ new_hash_entry_func new;
+{
+ memset (ht, 0, sizeof(*ht));
+ return bfd_hash_table_init (&ht->root, new);
+}
+
+static struct bfd_hash_entry*
+elf64_ia64_new_loc_hash_entry (entry, table, string)
+ struct bfd_hash_entry *entry;
+ struct bfd_hash_table *table;
+ const char *string;
+{
+ struct elf64_ia64_local_hash_entry *ret;
+ ret = (struct elf64_ia64_local_hash_entry *) entry;
+
+ /* Allocate the structure if it has not already been allocated by a
+ subclass. */
+ if (!ret)
+ ret = bfd_hash_allocate (table, sizeof (*ret));
+
+ if (!ret)
+ return 0;
+
+ /* Initialize our local data. All zeros, and definitely easier
+ than setting a handful of bit fields. */
+ memset (ret, 0, sizeof(*ret));
+
+ /* Call the allocation method of the superclass. */
+ ret = ((struct elf64_ia64_local_hash_entry *)
+ bfd_hash_newfunc ((struct bfd_hash_entry *) ret, table, string));
+
+ return (struct bfd_hash_entry *) ret;
+}
+
+static struct bfd_hash_entry*
+elf64_ia64_new_elf_hash_entry (entry, table, string)
+ struct bfd_hash_entry *entry;
+ struct bfd_hash_table *table;
+ const char *string;
+{
+ struct elf64_ia64_link_hash_entry *ret;
+ ret = (struct elf64_ia64_link_hash_entry *) entry;
+
+ /* Allocate the structure if it has not already been allocated by a
+ subclass. */
+ if (!ret)
+ ret = bfd_hash_allocate (table, sizeof (*ret));
+
+ if (!ret)
+ return 0;
+
+ /* Initialize our local data. All zeros, and definitely easier
+ than setting a handful of bit fields. */
+ memset (ret, 0, sizeof(*ret));
+
+ /* Call the allocation method of the superclass. */
+ ret = ((struct elf64_ia64_link_hash_entry *)
+ _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
+ table, string));
+
+ return (struct bfd_hash_entry *) ret;
+}
+
+static void
+elf64_ia64_hash_copy_indirect (xdir, xind)
+ struct elf_link_hash_entry *xdir, *xind;
+{
+ struct elf64_ia64_link_hash_entry *dir, *ind;
+
+ dir = (struct elf64_ia64_link_hash_entry *)xdir;
+ ind = (struct elf64_ia64_link_hash_entry *)xind;
+
+ /* Copy down any references that we may have already seen to the
+ symbol which just became indirect. */
+
+ dir->root.elf_link_hash_flags |=
+ (ind->root.elf_link_hash_flags
+ & (ELF_LINK_HASH_REF_DYNAMIC
+ | ELF_LINK_HASH_REF_REGULAR
+ | ELF_LINK_HASH_REF_REGULAR_NONWEAK));
+
+ /* Copy over the got and plt data. This would have been done
+ by check_relocs. */
+
+ if (dir->info == NULL)
+ {
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+
+ dir->info = dyn_i = ind->info;
+ ind->info = NULL;
+
+ /* Fix up the dyn_sym_info pointers to the global symbol. */
+ for (; dyn_i; dyn_i = dyn_i->next)
+ dyn_i->h = &dir->root;
+ }
+ BFD_ASSERT (ind->info == NULL);
+
+ /* Copy over the dynindx. */
+
+ if (dir->root.dynindx == -1)
+ {
+ dir->root.dynindx = ind->root.dynindx;
+ dir->root.dynstr_index = ind->root.dynstr_index;
+ ind->root.dynindx = -1;
+ ind->root.dynstr_index = 0;
+ }
+ BFD_ASSERT (ind->root.dynindx == -1);
+}
+
+static void
+elf64_ia64_hash_hide_symbol (xh)
+ struct elf_link_hash_entry *xh;
+{
+ struct elf64_ia64_link_hash_entry *h;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+
+ h = (struct elf64_ia64_link_hash_entry *)xh;
+
+ h->root.elf_link_hash_flags &= ~ELF_LINK_HASH_NEEDS_PLT;
+ h->root.dynindx = -1;
+
+ for (dyn_i = h->info; dyn_i; dyn_i = dyn_i->next)
+ dyn_i->want_plt2 = 0;
+}
+
+/* Create the derived linker hash table. The IA-64 ELF port uses this
+ derived hash table to keep information specific to the IA-64 ElF
+ linker (without using static variables). */
+
+static struct bfd_link_hash_table*
+elf64_ia64_hash_table_create (abfd)
+ bfd *abfd;
+{
+ struct elf64_ia64_link_hash_table *ret;
+
+ ret = bfd_alloc (abfd, sizeof (*ret));
+ if (!ret)
+ return 0;
+ if (!_bfd_elf_link_hash_table_init (&ret->root, abfd,
+ elf64_ia64_new_elf_hash_entry))
+ {
+ bfd_release (abfd, ret);
+ return 0;
+ }
+
+ if (!elf64_ia64_local_hash_table_init (&ret->loc_hash_table, abfd,
+ elf64_ia64_new_loc_hash_entry))
+ return 0;
+ return &ret->root.root;
+}
+
+/* Look up an entry in a Alpha ELF linker hash table. */
+
+static INLINE struct elf64_ia64_local_hash_entry *
+elf64_ia64_local_hash_lookup(table, string, create, copy)
+ struct elf64_ia64_local_hash_table *table;
+ const char *string;
+ boolean create, copy;
+{
+ return ((struct elf64_ia64_local_hash_entry *)
+ bfd_hash_lookup (&table->root, string, create, copy));
+}
+
+/* Traverse both local and global hash tables. */
+
+struct elf64_ia64_dyn_sym_traverse_data
+{
+ boolean (*func) PARAMS ((struct elf64_ia64_dyn_sym_info *, PTR));
+ PTR data;
+};
+
+static boolean
+elf64_ia64_global_dyn_sym_thunk (xentry, xdata)
+ struct bfd_hash_entry *xentry;
+ PTR xdata;
+{
+ struct elf64_ia64_link_hash_entry *entry
+ = (struct elf64_ia64_link_hash_entry *) xentry;
+ struct elf64_ia64_dyn_sym_traverse_data *data
+ = (struct elf64_ia64_dyn_sym_traverse_data *) xdata;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+
+ for (dyn_i = entry->info; dyn_i; dyn_i = dyn_i->next)
+ if (! (*data->func) (dyn_i, data->data))
+ return false;
+ return true;
+}
+
+static boolean
+elf64_ia64_local_dyn_sym_thunk (xentry, xdata)
+ struct bfd_hash_entry *xentry;
+ PTR xdata;
+{
+ struct elf64_ia64_local_hash_entry *entry
+ = (struct elf64_ia64_local_hash_entry *) xentry;
+ struct elf64_ia64_dyn_sym_traverse_data *data
+ = (struct elf64_ia64_dyn_sym_traverse_data *) xdata;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+
+ for (dyn_i = entry->info; dyn_i; dyn_i = dyn_i->next)
+ if (! (*data->func) (dyn_i, data->data))
+ return false;
+ return true;
+}
+
+static void
+elf64_ia64_dyn_sym_traverse (ia64_info, func, data)
+ struct elf64_ia64_link_hash_table *ia64_info;
+ boolean (*func) PARAMS ((struct elf64_ia64_dyn_sym_info *, PTR));
+ PTR data;
+{
+ struct elf64_ia64_dyn_sym_traverse_data xdata;
+
+ xdata.func = func;
+ xdata.data = data;
+
+ elf_link_hash_traverse (&ia64_info->root,
+ elf64_ia64_global_dyn_sym_thunk, &xdata);
+ bfd_hash_traverse (&ia64_info->loc_hash_table.root,
+ elf64_ia64_local_dyn_sym_thunk, &xdata);
+}
+\f
+static boolean
+elf64_ia64_create_dynamic_sections (abfd, info)
+ bfd *abfd;
+ struct bfd_link_info *info;
+{
+ struct elf64_ia64_link_hash_table *ia64_info;
+ struct elf_link_hash_entry *h;
+ asection *s;
+
+ if (! _bfd_elf_create_dynamic_sections (abfd, info))
+ return false;
+
+ ia64_info = elf64_ia64_hash_table (info);
+
+ ia64_info->plt_sec = bfd_get_section_by_name (abfd, ".plt");
+ ia64_info->got_sec = bfd_get_section_by_name (abfd, ".got");
+
+ {
+ flagword flags = bfd_get_section_flags (abfd, ia64_info->got_sec);
+ bfd_set_section_flags (abfd, ia64_info->got_sec, SEC_SMALL_DATA | flags);
+ }
+
+ if (!get_pltoff (abfd, info, ia64_info))
+ return false;
+
+ s = bfd_make_section(abfd, ".rela.IA_64.pltoff");
+ if (s == NULL
+ || !bfd_set_section_flags (abfd, s, (SEC_ALLOC | SEC_LOAD
+ | SEC_HAS_CONTENTS
+ | SEC_IN_MEMORY
+ | SEC_LINKER_CREATED
+ | SEC_READONLY))
+ || !bfd_set_section_alignment (abfd, s, 3))
+ return false;
+ ia64_info->rel_pltoff_sec = s;
+
+ s = bfd_make_section(abfd, ".rela.got");
+ if (s == NULL
+ || !bfd_set_section_flags (abfd, s, (SEC_ALLOC | SEC_LOAD
+ | SEC_HAS_CONTENTS
+ | SEC_IN_MEMORY
+ | SEC_LINKER_CREATED
+ | SEC_READONLY))
+ || !bfd_set_section_alignment (abfd, s, 3))
+ return false;
+ ia64_info->rel_got_sec = s;
+
+ return true;
+}
+
+/* Find and/or create a descriptor for dynamic symbol info. This will
+ vary based on global or local symbol, and the addend to the reloc. */
+
+static struct elf64_ia64_dyn_sym_info *
+get_dyn_sym_info (ia64_info, h, abfd, rel, create)
+ struct elf64_ia64_link_hash_table *ia64_info;
+ struct elf_link_hash_entry *h;
+ bfd *abfd;
+ const Elf_Internal_Rela *rel;
+ boolean create;
+{
+ struct elf64_ia64_dyn_sym_info **pp;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ bfd_vma addend = rel ? rel->r_addend : 0;
+
+ if (h)
+ pp = &((struct elf64_ia64_link_hash_entry *)h)->info;
+ else
+ {
+ struct elf64_ia64_local_hash_entry *loc_h;
+ char *addr_name;
+ size_t len;
+
+ /* Construct a string for use in the elf64_ia64_local_hash_table.
+ The name describes what was once anonymous memory. */
+
+ len = sizeof(void*)*2 + 1 + sizeof(bfd_vma)*4 + 1 + 1;
+ len += 10; /* %p slop */
+
+ addr_name = alloca (len);
+ sprintf (addr_name, "%p:%lx", abfd, ELF64_R_SYM (rel->r_info));
+
+ /* Collect the canonical entry data for this address. */
+ loc_h = elf64_ia64_local_hash_lookup (&ia64_info->loc_hash_table,
+ addr_name, create, create);
+ BFD_ASSERT (loc_h);
+
+ pp = &loc_h->info;
+ }
+
+ for (dyn_i = *pp; dyn_i && dyn_i->addend != addend; dyn_i = *pp)
+ pp = &dyn_i->next;
+
+ if (dyn_i == NULL && create)
+ {
+ dyn_i = (struct elf64_ia64_dyn_sym_info *)
+ bfd_zalloc (abfd, sizeof *dyn_i);
+ *pp = dyn_i;
+ dyn_i->addend = addend;
+ }
+
+ return dyn_i;
+}
+
+static asection *
+get_got (abfd, info, ia64_info)
+ bfd *abfd;
+ struct bfd_link_info *info;
+ struct elf64_ia64_link_hash_table *ia64_info;
+{
+ asection *got, *srel;
+ bfd *dynobj;
+
+ got = ia64_info->got_sec;
+ if (!got)
+ {
+ flagword flags;
+
+ dynobj = ia64_info->root.dynobj;
+ if (!dynobj)
+ ia64_info->root.dynobj = dynobj = abfd;
+ if (!_bfd_elf_create_got_section (dynobj, info))
+ return 0;
+
+ got = bfd_get_section_by_name (dynobj, ".got");
+ BFD_ASSERT (got);
+ ia64_info->got_sec = got;
+
+ flags = bfd_get_section_flags (abfd, got);
+ bfd_set_section_flags (abfd, got, SEC_SMALL_DATA | flags);
+ }
+
+ return got;
+}
+
+/* Create function descriptor section (.opd). This section is called .opd
+ because it contains "official prodecure descriptors". The "official"
+ refers to the fact that these descriptors are used when taking the address
+ of a procedure, thus ensuring a unique address for each procedure. */
+
+static asection *
+get_fptr (abfd, info, ia64_info)
+ bfd *abfd;
+ struct bfd_link_info *info;
+ struct elf64_ia64_link_hash_table *ia64_info;
+{
+ asection *fptr;
+ bfd *dynobj;
+
+ fptr = ia64_info->fptr_sec;
+ if (!fptr)
+ {
+ dynobj = ia64_info->root.dynobj;
+ if (!dynobj)
+ ia64_info->root.dynobj = dynobj = abfd;
+
+ fptr = bfd_make_section (dynobj, ".opd");
+ if (!fptr
+ || !bfd_set_section_flags (dynobj, fptr,
+ (SEC_ALLOC
+ | SEC_LOAD
+ | SEC_HAS_CONTENTS
+ | SEC_IN_MEMORY
+ | SEC_READONLY
+ | SEC_LINKER_CREATED))
+ || !bfd_set_section_alignment (abfd, fptr, 4))
+ {
+ BFD_ASSERT (0);
+ return NULL;
+ }
+
+ ia64_info->fptr_sec = fptr;
+ }
+
+ return fptr;
+}
+
+static asection *
+get_pltoff (abfd, info, ia64_info)
+ bfd *abfd;
+ struct bfd_link_info *info;
+ struct elf64_ia64_link_hash_table *ia64_info;
+{
+ asection *pltoff;
+ bfd *dynobj;
+
+ pltoff = ia64_info->pltoff_sec;
+ if (!pltoff)
+ {
+ dynobj = ia64_info->root.dynobj;
+ if (!dynobj)
+ ia64_info->root.dynobj = dynobj = abfd;
+
+ pltoff = bfd_make_section (dynobj, ELF_STRING_ia64_pltoff);
+ if (!pltoff
+ || !bfd_set_section_flags (dynobj, pltoff,
+ (SEC_ALLOC
+ | SEC_LOAD
+ | SEC_HAS_CONTENTS
+ | SEC_IN_MEMORY
+ | SEC_SMALL_DATA
+ | SEC_LINKER_CREATED))
+ || !bfd_set_section_alignment (abfd, pltoff, 4))
+ {
+ BFD_ASSERT (0);
+ return NULL;
+ }
+
+ ia64_info->pltoff_sec = pltoff;
+ }
+
+ return pltoff;
+}
+
+static asection *
+get_reloc_section (abfd, ia64_info, sec, create)
+ bfd *abfd;
+ struct elf64_ia64_link_hash_table *ia64_info;
+ asection *sec;
+ boolean create;
+{
+ const char *srel_name;
+ asection *srel;
+ bfd *dynobj;
+
+ srel_name = (bfd_elf_string_from_elf_section
+ (abfd, elf_elfheader(abfd)->e_shstrndx,
+ elf_section_data(sec)->rel_hdr.sh_name));
+ if (srel_name == NULL)
+ return NULL;
+
+ BFD_ASSERT ((strncmp (srel_name, ".rela", 5) == 0
+ && strcmp (bfd_get_section_name (abfd, sec),
+ srel_name+5) == 0)
+ || (strncmp (srel_name, ".rel", 4) == 0
+ && strcmp (bfd_get_section_name (abfd, sec),
+ srel_name+4) == 0));
+
+ dynobj = ia64_info->root.dynobj;
+ if (!dynobj)
+ ia64_info->root.dynobj = dynobj = abfd;
+
+ srel = bfd_get_section_by_name (dynobj, srel_name);
+ if (srel == NULL && create)
+ {
+ srel = bfd_make_section (dynobj, srel_name);
+ if (srel == NULL
+ || !bfd_set_section_flags (dynobj, srel,
+ (SEC_ALLOC
+ | SEC_LOAD
+ | SEC_HAS_CONTENTS
+ | SEC_IN_MEMORY
+ | SEC_LINKER_CREATED
+ | SEC_READONLY))
+ || !bfd_set_section_alignment (dynobj, srel, 3))
+ return NULL;
+ }
+
+ return srel;
+}
+
+static boolean
+count_dyn_reloc (abfd, dyn_i, srel, type)
+ bfd *abfd;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ asection *srel;
+ int type;
+{
+ struct elf64_ia64_dyn_reloc_entry *rent;
+
+ for (rent = dyn_i->reloc_entries; rent; rent = rent->next)
+ if (rent->srel == srel && rent->type == type)
+ break;
+
+ if (!rent)
+ {
+ rent = (struct elf64_ia64_dyn_reloc_entry *)
+ bfd_alloc (abfd, sizeof (*rent));
+ if (!rent)
+ return false;
+
+ rent->next = dyn_i->reloc_entries;
+ rent->srel = srel;
+ rent->type = type;
+ rent->count = 0;
+ dyn_i->reloc_entries = rent;
+ }
+ rent->count++;
+
+ return true;
+}
+
+static boolean
+elf64_ia64_check_relocs (abfd, info, sec, relocs)
+ bfd *abfd;
+ struct bfd_link_info *info;
+ asection *sec;
+ const Elf_Internal_Rela *relocs;
+{
+ struct elf64_ia64_link_hash_table *ia64_info;
+ const Elf_Internal_Rela *relend;
+ Elf_Internal_Shdr *symtab_hdr;
+ const Elf_Internal_Rela *rel;
+ asection *got, *fptr, *srel;
+
+ if (info->relocateable)
+ return true;
+
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+ ia64_info = elf64_ia64_hash_table (info);
+
+ got = fptr = srel = NULL;
+
+ relend = relocs + sec->reloc_count;
+ for (rel = relocs; rel < relend; ++rel)
+ {
+ enum {
+ NEED_GOT = 1,
+ NEED_FPTR = 2,
+ NEED_PLTOFF = 4,
+ NEED_MIN_PLT = 8,
+ NEED_FULL_PLT = 16,
+ NEED_DYNREL = 32,
+ NEED_LTOFF_FPTR = 64,
+ };
+
+ struct elf_link_hash_entry *h = NULL;
+ unsigned long r_symndx = ELF64_R_SYM (rel->r_info);
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ int need_entry;
+ boolean maybe_dynamic;
+ int dynrel_type;
+
+ if (r_symndx >= symtab_hdr->sh_info)
+ {
+ /* We're dealing with a global symbol -- find its hash entry
+ and mark it as being referenced. */
+ long indx = r_symndx - symtab_hdr->sh_info;
+ h = elf_sym_hashes (abfd)[indx];
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+ h->elf_link_hash_flags |= ELF_LINK_HASH_REF_REGULAR;
+ }
+
+ /* We can only get preliminary data on whether a symbol is
+ locally or externally defined, as not all of the input files
+ have yet been processed. Do something with what we know, as
+ this may help reduce memory usage and processing time later. */
+ maybe_dynamic = false;
+ if (h && ((info->shared && ! info->symbolic)
+ || ! (h->elf_link_hash_flags & ELF_LINK_HASH_DEF_REGULAR)
+ || h->root.type == bfd_link_hash_defweak))
+ maybe_dynamic = true;
+
+ need_entry = 0;
+ switch (ELF64_R_TYPE (rel->r_info))
+ {
+ case R_IA64_TPREL22:
+ case R_IA64_TPREL64MSB:
+ case R_IA64_TPREL64LSB:
+ case R_IA64_LTOFF_TP22:
+ return false;
+
+ case R_IA64_LTOFF_FPTR22:
+ case R_IA64_LTOFF_FPTR64I:
+ case R_IA64_LTOFF_FPTR64MSB:
+ case R_IA64_LTOFF_FPTR64LSB:
+ need_entry = NEED_FPTR | NEED_GOT | NEED_LTOFF_FPTR;
+ break;
+
+ case R_IA64_FPTR64I:
+ case R_IA64_FPTR32MSB:
+ case R_IA64_FPTR32LSB:
+ case R_IA64_FPTR64MSB:
+ case R_IA64_FPTR64LSB:
+ if (info->shared || h)
+ need_entry = NEED_FPTR | NEED_DYNREL;
+ else
+ need_entry = NEED_FPTR;
+ dynrel_type = R_IA64_FPTR64LSB;
+ break;
+
+ case R_IA64_LTOFF22:
+ case R_IA64_LTOFF22X:
+ case R_IA64_LTOFF64I:
+ need_entry = NEED_GOT;
+ break;
+
+ case R_IA64_PLTOFF22:
+ case R_IA64_PLTOFF64I:
+ case R_IA64_PLTOFF64MSB:
+ case R_IA64_PLTOFF64LSB:
+ need_entry = NEED_PLTOFF;
+ if (h)
+ {
+ if (maybe_dynamic)
+ need_entry |= NEED_MIN_PLT;
+ }
+ else
+ {
+ (*info->callbacks->warning)
+ (info, _("@pltoff reloc against local symbol"), 0,
+ abfd, 0, 0);
+ }
+ break;
+
+ case R_IA64_PCREL21B:
+ /* Depending on where this symbol is defined, we may or may not
+ need a full plt entry. Only skip if we know we'll not need
+ the entry -- static or symbolic, and the symbol definition
+ has already been seen. */
+ if (maybe_dynamic && rel->r_addend == 0)
+ need_entry = NEED_FULL_PLT;
+ break;
+
+ case R_IA64_IMM14:
+ case R_IA64_IMM22:
+ case R_IA64_IMM64:
+ case R_IA64_DIR32MSB:
+ case R_IA64_DIR32LSB:
+ case R_IA64_DIR64MSB:
+ case R_IA64_DIR64LSB:
+ /* Shared objects will always need at least a REL relocation. */
+ if (info->shared || maybe_dynamic)
+ need_entry = NEED_DYNREL;
+ dynrel_type = R_IA64_DIR64LSB;
+ break;
+
+ case R_IA64_PCREL32MSB:
+ case R_IA64_PCREL32LSB:
+ case R_IA64_PCREL64MSB:
+ case R_IA64_PCREL64LSB:
+ if (maybe_dynamic)
+ need_entry = NEED_DYNREL;
+ dynrel_type = R_IA64_PCREL64LSB;
+ break;
+ }
+
+ if (!need_entry)
+ continue;
+
+ if ((need_entry & NEED_FPTR) != 0
+ && rel->r_addend)
+ {
+ (*info->callbacks->warning)
+ (info, _("non-zero addend in @fptr reloc"), 0,
+ abfd, 0, 0);
+ }
+
+ dyn_i = get_dyn_sym_info (ia64_info, h, abfd, rel, true);
+
+ /* Record whether or not this is a local symbol. */
+ dyn_i->h = h;
+
+ /* Create what's needed. */
+ if (need_entry & NEED_GOT)
+ {
+ if (!got)
+ {
+ got = get_got (abfd, info, ia64_info);
+ if (!got)
+ return false;
+ }
+ dyn_i->want_got = 1;
+ }
+ if (need_entry & NEED_FPTR)
+ {
+ if (!fptr)
+ {
+ fptr = get_fptr (abfd, info, ia64_info);
+ if (!fptr)
+ return false;
+ }
+
+ /* FPTRs for shared libraries are allocated by the dynamic
+ linker. Make sure this local symbol will appear in the
+ dynamic symbol table. */
+ if (!h && info->shared)
+ {
+ if (! (_bfd_elf64_link_record_local_dynamic_symbol
+ (info, abfd, r_symndx)))
+ return false;
+ }
+
+ dyn_i->want_fptr = 1;
+ }
+ if (need_entry & NEED_LTOFF_FPTR)
+ dyn_i->want_ltoff_fptr = 1;
+ if (need_entry & (NEED_MIN_PLT | NEED_FULL_PLT))
+ {
+ if (!ia64_info->root.dynobj)
+ ia64_info->root.dynobj = abfd;
+ h->elf_link_hash_flags |= ELF_LINK_HASH_NEEDS_PLT;
+ dyn_i->want_plt = 1;
+ }
+ if (need_entry & NEED_FULL_PLT)
+ dyn_i->want_plt2 = 1;
+ if (need_entry & NEED_PLTOFF)
+ dyn_i->want_pltoff = 1;
+ if ((need_entry & NEED_DYNREL) && (sec->flags & SEC_ALLOC))
+ {
+ if (!srel)
+ {
+ srel = get_reloc_section (abfd, ia64_info, sec, true);
+ if (!srel)
+ return false;
+ }
+ if (!count_dyn_reloc (abfd, dyn_i, srel, dynrel_type))
+ return false;
+ }
+ }
+
+ return true;
+}
+
+struct elf64_ia64_allocate_data
+{
+ struct bfd_link_info *info;
+ bfd_size_type ofs;
+};
+
+/* For cleanliness, and potentially faster dynamic loading, allocate
+ external GOT entries first. */
+
+static boolean
+allocate_global_data_got (dyn_i, data)
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ PTR data;
+{
+ struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+ if (dyn_i->want_got
+ && ! dyn_i->want_fptr
+ && elf64_ia64_dynamic_symbol_p (dyn_i->h, x->info))
+ {
+ dyn_i->got_offset = x->ofs;
+ x->ofs += 8;
+ }
+ return true;
+}
+
+/* Next, allocate all the GOT entries used by LTOFF_FPTR relocs. */
+
+static boolean
+allocate_global_fptr_got (dyn_i, data)
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ PTR data;
+{
+ struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+ if (dyn_i->want_got
+ && dyn_i->want_fptr
+ && elf64_ia64_dynamic_symbol_p (dyn_i->h, x->info))
+ {
+ dyn_i->got_offset = x->ofs;
+ x->ofs += 8;
+ }
+ return true;
+}
+
+/* Lastly, allocate all the GOT entries for local data. */
+
+static boolean
+allocate_local_got (dyn_i, data)
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ PTR data;
+{
+ struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+ if (dyn_i->want_got
+ && ! elf64_ia64_dynamic_symbol_p (dyn_i->h, x->info))
+ {
+ dyn_i->got_offset = x->ofs;
+ x->ofs += 8;
+ }
+ return true;
+}
+
+/* Search for the index of a global symbol in it's defining object file. */
+
+static unsigned long
+global_sym_index (h)
+ struct elf_link_hash_entry *h;
+{
+ struct elf_link_hash_entry **p;
+ bfd *obj;
+
+ BFD_ASSERT (h->root.type == bfd_link_hash_defined
+ || h->root.type == bfd_link_hash_defweak);
+
+ obj = h->root.u.def.section->owner;
+ for (p = elf_sym_hashes (obj); *p != h; ++p)
+ continue;
+
+ return p - elf_sym_hashes (obj) + elf_tdata (obj)->symtab_hdr.sh_info;
+}
+
+/* Allocate function descriptors. We can do these for every function
+ in a main executable that is not exported. */
+
+static boolean
+allocate_fptr (dyn_i, data)
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ PTR data;
+{
+ struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+ if (dyn_i->want_fptr)
+ {
+ struct elf_link_hash_entry *h = dyn_i->h;
+
+ if (h)
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+ if (x->info->shared)
+ {
+ if (h && h->dynindx == -1)
+ {
+ BFD_ASSERT ((h->root.type == bfd_link_hash_defined)
+ || (h->root.type == bfd_link_hash_defweak));
+
+ if (!_bfd_elf64_link_record_local_dynamic_symbol
+ (x->info, h->root.u.def.section->owner,
+ global_sym_index (h)))
+ return false;
+ }
+
+ dyn_i->want_fptr = 0;
+ }
+ else if (h == NULL || h->dynindx == -1)
+ {
+ dyn_i->fptr_offset = x->ofs;
+ x->ofs += 16;
+ }
+ else
+ dyn_i->want_fptr = 0;
+ }
+ return true;
+}
+
+/* Allocate all the minimal PLT entries. */
+
+static boolean
+allocate_plt_entries (dyn_i, data)
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ PTR data;
+{
+ struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+ if (dyn_i->want_plt)
+ {
+ struct elf_link_hash_entry *h = dyn_i->h;
+
+ if (h)
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+ /* ??? Versioned symbols seem to lose ELF_LINK_HASH_NEEDS_PLT. */
+ if (elf64_ia64_dynamic_symbol_p (h, x->info))
+ {
+ bfd_size_type offset = x->ofs;
+ if (offset == 0)
+ offset = PLT_HEADER_SIZE;
+ dyn_i->plt_offset = offset;
+ x->ofs = offset + PLT_MIN_ENTRY_SIZE;
+
+ dyn_i->want_pltoff = 1;
+ }
+ else
+ {
+ dyn_i->want_plt = 0;
+ dyn_i->want_plt2 = 0;
+ }
+ }
+ return true;
+}
+
+/* Allocate all the full PLT entries. */
+
+static boolean
+allocate_plt2_entries (dyn_i, data)
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ PTR data;
+{
+ struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+ if (dyn_i->want_plt2)
+ {
+ struct elf_link_hash_entry *h = dyn_i->h;
+ bfd_size_type ofs = x->ofs;
+
+ dyn_i->plt2_offset = ofs;
+ x->ofs = ofs + PLT_FULL_ENTRY_SIZE;
+
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+ dyn_i->h->plt.offset = ofs;
+ }
+ return true;
+}
+
+/* Allocate all the PLTOFF entries requested by relocations and
+ plt entries. We can't share space with allocated FPTR entries,
+ because the latter are not necessarily addressable by the GP.
+ ??? Relaxation might be able to determine that they are. */
+
+static boolean
+allocate_pltoff_entries (dyn_i, data)
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ PTR data;
+{
+ struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+ if (dyn_i->want_pltoff)
+ {
+ dyn_i->pltoff_offset = x->ofs;
+ x->ofs += 16;
+ }
+ return true;
+}
+
+/* Allocate dynamic relocations for those symbols that turned out
+ to be dynamic. */
+
+static boolean
+allocate_dynrel_entries (dyn_i, data)
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ PTR data;
+{
+ struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+ struct elf64_ia64_link_hash_table *ia64_info;
+ struct elf64_ia64_dyn_reloc_entry *rent;
+ boolean dynamic_symbol, shared;
+
+ ia64_info = elf64_ia64_hash_table (x->info);
+ dynamic_symbol = elf64_ia64_dynamic_symbol_p (dyn_i->h, x->info);
+ shared = x->info->shared;
+
+ /* Take care of the normal data relocations. */
+
+ for (rent = dyn_i->reloc_entries; rent; rent = rent->next)
+ {
+ switch (rent->type)
+ {
+ case R_IA64_FPTR64LSB:
+ /* Allocate one iff !want_fptr, which by this point will
+ be true only if we're actually allocating one statically
+ in the main executable. */
+ if (dyn_i->want_fptr)
+ continue;
+ break;
+ case R_IA64_PCREL64LSB:
+ if (!dynamic_symbol)
+ continue;
+ break;
+ case R_IA64_DIR64LSB:
+ if (!dynamic_symbol && !shared)
+ continue;
+ break;
+ }
+ rent->srel->_raw_size += sizeof (Elf64_External_Rela) * rent->count;
+ }
+
+ /* Take care of the GOT and PLT relocations. */
+
+ if (((dynamic_symbol || shared) && dyn_i->want_got)
+ || (dyn_i->want_ltoff_fptr && dyn_i->h && dyn_i->h->dynindx != -1))
+ ia64_info->rel_got_sec->_raw_size += sizeof (Elf64_External_Rela);
+
+ if (dyn_i->want_pltoff)
+ {
+ bfd_size_type t = 0;
+
+ /* Dynamic symbols get one IPLT relocation. Local symbols in
+ shared libraries get two REL relocations. Local symbols in
+ main applications get nothing. */
+ if (dynamic_symbol)
+ t = sizeof (Elf64_External_Rela);
+ else if (shared)
+ t = 2 * sizeof (Elf64_External_Rela);
+
+ ia64_info->rel_pltoff_sec->_raw_size += t;
+ }
+
+ return true;
+}
+
+static boolean
+elf64_ia64_adjust_dynamic_symbol (info, h)
+ struct bfd_link_info *info;
+ struct elf_link_hash_entry *h;
+{
+ /* ??? Undefined symbols with PLT entries should be re-defined
+ to be the PLT entry. */
+
+ /* If this is a weak symbol, and there is a real definition, the
+ processor independent code will have arranged for us to see the
+ real definition first, and we can just use the same value. */
+ if (h->weakdef != NULL)
+ {
+ BFD_ASSERT (h->weakdef->root.type == bfd_link_hash_defined
+ || h->weakdef->root.type == bfd_link_hash_defweak);
+ h->root.u.def.section = h->weakdef->root.u.def.section;
+ h->root.u.def.value = h->weakdef->root.u.def.value;
+ return true;
+ }
+
+ /* If this is a reference to a symbol defined by a dynamic object which
+ is not a function, we might allocate the symbol in our .dynbss section
+ and allocate a COPY dynamic relocation.
+
+ But IA-64 code is canonically PIC, so as a rule we can avoid this sort
+ of hackery. */
+
+ return true;
+}
+
+static boolean
+elf64_ia64_size_dynamic_sections (output_bfd, info)
+ bfd *output_bfd;
+ struct bfd_link_info *info;
+{
+ struct elf64_ia64_allocate_data data;
+ struct elf64_ia64_link_hash_table *ia64_info;
+ asection *sec;
+ bfd *dynobj;
+ boolean reltext = false;
+ boolean relplt = false;
+
+ dynobj = elf_hash_table(info)->dynobj;
+ ia64_info = elf64_ia64_hash_table (info);
+ BFD_ASSERT(dynobj != NULL);
+ data.info = info;
+
+ /* Set the contents of the .interp section to the interpreter. */
+ if (ia64_info->root.dynamic_sections_created
+ && !info->shared)
+ {
+ sec = bfd_get_section_by_name (dynobj, ".interp");
+ BFD_ASSERT (sec != NULL);
+ sec->contents = (bfd_byte *) ELF_DYNAMIC_INTERPRETER;
+ sec->_raw_size = strlen (ELF_DYNAMIC_INTERPRETER) + 1;
+ }
+
+ /* DT_INIT and DT_FINI get function descriptors not raw code addresses.
+ Force their symbols to have pltoff entries so we can use those. */
+ if (ia64_info->root.dynamic_sections_created)
+ {
+ struct elf_link_hash_entry *h;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+
+ if (info->init_function
+ && (h = elf_link_hash_lookup (elf_hash_table (info),
+ info->init_function, false,
+ false, false))
+ && (h->elf_link_hash_flags & (ELF_LINK_HASH_REF_REGULAR
+ | ELF_LINK_HASH_DEF_REGULAR)) != 0)
+ {
+ dyn_i = get_dyn_sym_info (ia64_info, h, output_bfd, NULL, true);
+ dyn_i->want_pltoff = 1;
+ }
+
+ if (info->fini_function
+ && (h = elf_link_hash_lookup (elf_hash_table (info),
+ info->fini_function, false,
+ false, false))
+ && (h->elf_link_hash_flags & (ELF_LINK_HASH_REF_REGULAR
+ | ELF_LINK_HASH_DEF_REGULAR)) != 0)
+ {
+ dyn_i = get_dyn_sym_info (ia64_info, h, output_bfd, NULL, true);
+ dyn_i->want_pltoff = 1;
+ }
+ }
+
+ /* Allocate the GOT entries. */
+
+ if (ia64_info->got_sec)
+ {
+ data.ofs = 0;
+ elf64_ia64_dyn_sym_traverse (ia64_info, allocate_global_data_got, &data);
+ elf64_ia64_dyn_sym_traverse (ia64_info, allocate_global_fptr_got, &data);
+ elf64_ia64_dyn_sym_traverse (ia64_info, allocate_local_got, &data);
+ ia64_info->got_sec->_raw_size = data.ofs;
+ }
+
+ /* Allocate the FPTR entries. */
+
+ if (ia64_info->fptr_sec)
+ {
+ data.ofs = 0;
+ elf64_ia64_dyn_sym_traverse (ia64_info, allocate_fptr, &data);
+ ia64_info->fptr_sec->_raw_size = data.ofs;
+ }
+
+ /* Now that we've seen all of the input files, we can decide which
+ symbols need plt entries. Allocate the minimal PLT entries first.
+ We do this even though dynamic_sections_created may be false, because
+ this has the side-effect of clearing want_plt and want_plt2. */
+
+ data.ofs = 0;
+ elf64_ia64_dyn_sym_traverse (ia64_info, allocate_plt_entries, &data);
+
+ ia64_info->minplt_entries = 0;
+ if (data.ofs)
+ {
+ ia64_info->minplt_entries
+ = (data.ofs - PLT_HEADER_SIZE) / PLT_MIN_ENTRY_SIZE;
+ }
+
+ /* Align the pointer for the plt2 entries. */
+ data.ofs = (data.ofs + 31) & -32;
+
+ elf64_ia64_dyn_sym_traverse (ia64_info, allocate_plt2_entries, &data);
+ if (data.ofs != 0)
+ {
+ BFD_ASSERT (ia64_info->root.dynamic_sections_created);
+
+ ia64_info->plt_sec->_raw_size = data.ofs;
+
+ /* If we've got a .plt, we need some extra memory for the dynamic
+ linker. We stuff these in .got.plt. */
+ sec = bfd_get_section_by_name (dynobj, ".got.plt");
+ sec->_raw_size = 8 * PLT_RESERVED_WORDS;
+ }
+
+ /* Allocate the PLTOFF entries. */
+
+ if (ia64_info->pltoff_sec)
+ {
+ data.ofs = 0;
+ elf64_ia64_dyn_sym_traverse (ia64_info, allocate_pltoff_entries, &data);
+ ia64_info->pltoff_sec->_raw_size = data.ofs;
+ }
+
+ if (ia64_info->root.dynamic_sections_created)
+ {
+ /* Allocate space for the dynamic relocations that turned out to be
+ required. */
+
+ elf64_ia64_dyn_sym_traverse (ia64_info, allocate_dynrel_entries, &data);
+ }
+
+ /* We have now determined the sizes of the various dynamic sections.
+ Allocate memory for them. */
+ for (sec = dynobj->sections; sec != NULL; sec = sec->next)
+ {
+ boolean strip;
+
+ if (!(sec->flags & SEC_LINKER_CREATED))
+ continue;
+
+ /* If we don't need this section, strip it from the output file.
+ There were several sections primarily related to dynamic
+ linking that must be create before the linker maps input
+ sections to output sections. The linker does that before
+ bfd_elf_size_dynamic_sections is called, and it is that
+ function which decides whether anything needs to go into
+ these sections. */
+
+ strip = (sec->_raw_size == 0);
+
+ if (sec == ia64_info->got_sec)
+ strip = false;
+ else if (sec == ia64_info->rel_got_sec)
+ {
+ if (strip)
+ ia64_info->rel_got_sec = NULL;
+ else
+ /* We use the reloc_count field as a counter if we need to
+ copy relocs into the output file. */
+ sec->reloc_count = 0;
+ }
+ else if (sec == ia64_info->fptr_sec)
+ {
+ if (strip)
+ ia64_info->fptr_sec = NULL;
+ }
+ else if (sec == ia64_info->plt_sec)
+ {
+ if (strip)
+ ia64_info->plt_sec = NULL;
+ }
+ else if (sec == ia64_info->pltoff_sec)
+ {
+ if (strip)
+ ia64_info->pltoff_sec = NULL;
+ }
+ else if (sec == ia64_info->rel_pltoff_sec)
+ {
+ if (strip)
+ ia64_info->rel_pltoff_sec = NULL;
+ else
+ {
+ relplt = true;
+ /* We use the reloc_count field as a counter if we need to
+ copy relocs into the output file. */
+ sec->reloc_count = 0;
+ }
+ }
+ else
+ {
+ const char *name;
+
+ /* It's OK to base decisions on the section name, because none
+ of the dynobj section names depend upon the input files. */
+ name = bfd_get_section_name (dynobj, sec);
+
+ if (strcmp (name, ".got.plt") == 0)
+ strip = false;
+ else if (strncmp (name, ".rel", 4) == 0)
+ {
+ if (!strip)
+ {
+ const char *outname;
+ asection *target;
+
+ /* If this relocation section applies to a read only
+ section, then we probably need a DT_TEXTREL entry. */
+ outname = bfd_get_section_name (output_bfd,
+ sec->output_section);
+ if (outname[4] == 'a')
+ outname += 5;
+ else
+ outname += 4;
+
+ target = bfd_get_section_by_name (output_bfd, outname);
+ if (target != NULL
+ && (target->flags & SEC_READONLY) != 0
+ && (target->flags & SEC_ALLOC) != 0)
+ reltext = true;
+
+ /* We use the reloc_count field as a counter if we need to
+ copy relocs into the output file. */
+ sec->reloc_count = 0;
+ }
+ }
+ else
+ continue;
+ }
+
+ if (strip)
+ _bfd_strip_section_from_output (info, sec);
+ else
+ {
+ /* Allocate memory for the section contents. */
+ sec->contents = (bfd_byte *) bfd_zalloc(dynobj, sec->_raw_size);
+ if (sec->contents == NULL && sec->_raw_size != 0)
+ return false;
+ }
+ }
+
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Add some entries to the .dynamic section. We fill in the values
+ later (in finish_dynamic_sections) but we must add the entries now
+ so that we get the correct size for the .dynamic section. */
+
+ if (!info->shared)
+ {
+ /* The DT_DEBUG entry is filled in by the dynamic linker and used
+ by the debugger. */
+ if (!bfd_elf64_add_dynamic_entry (info, DT_DEBUG, 0))
+ return false;
+ }
+
+ if (! bfd_elf64_add_dynamic_entry (info, DT_IA_64_PLT_RESERVE, 0))
+ return false;
+ if (! bfd_elf64_add_dynamic_entry (info, DT_PLTGOT, 0))
+ return false;
+
+ if (relplt)
+ {
+ if (! bfd_elf64_add_dynamic_entry (info, DT_PLTRELSZ, 0)
+ || ! bfd_elf64_add_dynamic_entry (info, DT_PLTREL, DT_RELA)
+ || ! bfd_elf64_add_dynamic_entry (info, DT_JMPREL, 0))
+ return false;
+ }
+
+ if (! bfd_elf64_add_dynamic_entry (info, DT_RELA, 0)
+ || ! bfd_elf64_add_dynamic_entry (info, DT_RELASZ, 0)
+ || ! bfd_elf64_add_dynamic_entry (info, DT_RELAENT,
+ sizeof(Elf64_External_Rela)))
+ return false;
+
+ if (reltext)
+ {
+ if (! bfd_elf64_add_dynamic_entry (info, DT_TEXTREL, 0))
+ return false;
+ }
+ }
+
+ /* ??? Perhaps force __gp local. */
+
+ return true;
+}
+
+static bfd_reloc_status_type
+elf64_ia64_install_value (abfd, hit_addr, val, r_type)
+ bfd *abfd;
+ bfd_byte *hit_addr;
+ bfd_vma val;
+ unsigned int r_type;
+{
+ const struct ia64_operand *op;
+ int bigendian = 0, shift = 0;
+ bfd_vma t0, t1, insn, dword;
+ enum ia64_opnd opnd;
+ const char *err;
+ size_t size = 8;
+
+ opnd = IA64_OPND_NIL;
+ switch (r_type)
+ {
+ case R_IA64_NONE:
+ case R_IA64_LDXMOV:
+ return bfd_reloc_ok;
+
+ /* Instruction relocations. */
+
+ case R_IA64_IMM14: opnd = IA64_OPND_IMM14; break;
+ case R_IA64_PCREL21F: opnd = IA64_OPND_TGT25; break;
+ case R_IA64_PCREL21M: opnd = IA64_OPND_TGT25b; break;
+ case R_IA64_PCREL21B: opnd = IA64_OPND_TGT25c; break;
+
+ case R_IA64_IMM22:
+ case R_IA64_GPREL22:
+ case R_IA64_LTOFF22:
+ case R_IA64_LTOFF22X:
+ case R_IA64_PLTOFF22:
+ case R_IA64_LTOFF_FPTR22:
+ opnd = IA64_OPND_IMM22;
+ break;
+
+ case R_IA64_IMM64:
+ case R_IA64_GPREL64I:
+ case R_IA64_LTOFF64I:
+ case R_IA64_PLTOFF64I:
+ case R_IA64_FPTR64I:
+ case R_IA64_LTOFF_FPTR64I:
+ opnd = IA64_OPND_IMMU64;
+ break;
+
+ /* Data relocations. */
+
+ case R_IA64_DIR32MSB:
+ case R_IA64_GPREL32MSB:
+ case R_IA64_FPTR32MSB:
+ case R_IA64_PCREL32MSB:
+ case R_IA64_SEGREL32MSB:
+ case R_IA64_SECREL32MSB:
+ case R_IA64_LTV32MSB:
+ size = 4; bigendian = 1;
+ break;
+
+ case R_IA64_DIR32LSB:
+ case R_IA64_GPREL32LSB:
+ case R_IA64_FPTR32LSB:
+ case R_IA64_PCREL32LSB:
+ case R_IA64_SEGREL32LSB:
+ case R_IA64_SECREL32LSB:
+ case R_IA64_LTV32LSB:
+ size = 4; bigendian = 0;
+ break;
+
+ case R_IA64_DIR64MSB:
+ case R_IA64_GPREL64MSB:
+ case R_IA64_PLTOFF64MSB:
+ case R_IA64_FPTR64MSB:
+ case R_IA64_PCREL64MSB:
+ case R_IA64_LTOFF_FPTR64MSB:
+ case R_IA64_SEGREL64MSB:
+ case R_IA64_SECREL64MSB:
+ case R_IA64_LTV64MSB:
+ size = 8; bigendian = 1;
+ break;
+
+ case R_IA64_DIR64LSB:
+ case R_IA64_GPREL64LSB:
+ case R_IA64_PLTOFF64LSB:
+ case R_IA64_FPTR64LSB:
+ case R_IA64_PCREL64LSB:
+ case R_IA64_LTOFF_FPTR64LSB:
+ case R_IA64_SEGREL64LSB:
+ case R_IA64_SECREL64LSB:
+ case R_IA64_LTV64LSB:
+ size = 8; bigendian = 0;
+ break;
+
+ /* Unsupported / Dynamic relocations. */
+
+ case R_IA64_REL32MSB:
+ case R_IA64_REL32LSB:
+ case R_IA64_REL64MSB:
+ case R_IA64_REL64LSB:
+
+ case R_IA64_IPLTMSB:
+ case R_IA64_IPLTLSB:
+ case R_IA64_EPLTMSB:
+ case R_IA64_EPLTLSB:
+ case R_IA64_COPY:
+
+ case R_IA64_SEGBASE:
+
+ case R_IA64_TPREL22:
+ case R_IA64_TPREL64MSB:
+ case R_IA64_TPREL64LSB:
+ case R_IA64_LTOFF_TP22:
+
+ default:
+ return bfd_reloc_notsupported;
+ }
+
+ switch (opnd)
+ {
+ case IA64_OPND_IMMU64:
+ hit_addr -= (long) hit_addr & 0x3;
+ t0 = bfd_get_64 (abfd, hit_addr);
+ t1 = bfd_get_64 (abfd, hit_addr + 8);
+
+ /* tmpl/s: bits 0.. 5 in t0
+ slot 0: bits 5..45 in t0
+ slot 1: bits 46..63 in t0, bits 0..22 in t1
+ slot 2: bits 23..63 in t1 */
+
+ /* First, clear the bits that form the 64 bit constant. */
+ t0 &= ~(0x3ffffLL << 46);
+ t1 &= ~(0x7fffffLL
+ | (( (0x07fLL << 13) | (0x1ffLL << 27)
+ | (0x01fLL << 22) | (0x001LL << 21)
+ | (0x001LL << 36)) << 23));
+
+ t0 |= ((val >> 22) & 0x03ffffLL) << 46; /* 18 lsbs of imm41 */
+ t1 |= ((val >> 40) & 0x7fffffLL) << 0; /* 23 msbs of imm41 */
+ t1 |= ( (((val >> 0) & 0x07f) << 13) /* imm7b */
+ | (((val >> 7) & 0x1ff) << 27) /* imm9d */
+ | (((val >> 16) & 0x01f) << 22) /* imm5c */
+ | (((val >> 21) & 0x001) << 21) /* ic */
+ | (((val >> 63) & 0x001) << 36)) << 23; /* i */
+
+ bfd_put_64 (abfd, t0, hit_addr);
+ bfd_put_64 (abfd, t1, hit_addr + 8);
+ break;
+
+ default:
+ switch ((long) hit_addr & 0x3)
+ {
+ case 0: shift = 5; break;
+ case 1: shift = 14; hit_addr += 3; break;
+ case 2: shift = 23; hit_addr += 6; break;
+ case 3: return bfd_reloc_notsupported; /* shouldn't happen... */
+ }
+ dword = bfd_get_64 (abfd, hit_addr);
+ insn = (dword >> shift) & 0x1ffffffffffLL;
+
+ op = elf64_ia64_operands + opnd;
+ err = (*op->insert) (op, val, &insn);
+ if (err)
+ return bfd_reloc_overflow;
+
+ dword &= ~(0x1ffffffffffLL << shift);
+ dword |= (insn << shift);
+ bfd_put_64 (abfd, dword, hit_addr);
+ break;
+
+ case IA64_OPND_NIL:
+ /* A data relocation. */
+ if (bigendian)
+ if (size == 4)
+ bfd_putb32 (val, hit_addr);
+ else
+ bfd_putb64 (val, hit_addr);
+ else
+ if (size == 4)
+ bfd_putl32 (val, hit_addr);
+ else
+ bfd_putl64 (val, hit_addr);
+ break;
+ }
+
+ return bfd_reloc_ok;
+}
+
+static void
+elf64_ia64_install_dyn_reloc (abfd, info, sec, srel, offset, type,
+ dynindx, addend)
+ bfd *abfd;
+ struct bfd_link_info *info;
+ asection *sec;
+ asection *srel;
+ bfd_vma offset;
+ unsigned int type;
+ long dynindx;
+ bfd_vma addend;
+{
+ Elf_Internal_Rela outrel;
+
+ outrel.r_offset = (sec->output_section->vma
+ + sec->output_offset
+ + offset);
+
+ BFD_ASSERT (dynindx != -1);
+ outrel.r_info = ELF64_R_INFO (dynindx, type);
+ outrel.r_addend = addend;
+
+ if (elf_section_data (sec)->stab_info != NULL)
+ {
+ /* This may be NULL for linker-generated relocations, as it is
+ inconvenient to pass all the bits around. And this shouldn't
+ happen. */
+ BFD_ASSERT (info != NULL);
+
+ offset = (_bfd_stab_section_offset
+ (abfd, &elf_hash_table (info)->stab_info, sec,
+ &elf_section_data (sec)->stab_info, offset));
+ if (offset == (bfd_vma) -1)
+ {
+ /* Run for the hills. We shouldn't be outputting a relocation
+ for this. So do what everyone else does and output a no-op. */
+ outrel.r_info = ELF64_R_INFO (0, R_IA64_NONE);
+ outrel.r_addend = 0;
+ offset = 0;
+ }
+ outrel.r_offset = offset;
+ }
+
+ bfd_elf64_swap_reloca_out (abfd, &outrel,
+ ((Elf64_External_Rela *) srel->contents
+ + srel->reloc_count++));
+ BFD_ASSERT (sizeof(Elf64_External_Rela) * srel->reloc_count
+ <= srel->_cooked_size);
+}
+
+/* Store an entry for target address TARGET_ADDR in the linkage table
+ and return the gp-relative address of the linkage table entry. */
+
+static bfd_vma
+set_got_entry (abfd, info, dyn_i, dynindx, addend, value, dyn_r_type)
+ bfd *abfd;
+ struct bfd_link_info *info;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ long dynindx;
+ bfd_vma addend;
+ bfd_vma value;
+ unsigned int dyn_r_type;
+{
+ struct elf64_ia64_link_hash_table *ia64_info;
+ asection *got_sec;
+
+ ia64_info = elf64_ia64_hash_table (info);
+ got_sec = ia64_info->got_sec;
+
+ BFD_ASSERT ((dyn_i->got_offset & 7) == 0);
+
+ if (! dyn_i->got_done)
+ {
+ dyn_i->got_done = true;
+
+ /* Store the target address in the linkage table entry. */
+ bfd_put_64 (abfd, value, got_sec->contents + dyn_i->got_offset);
+
+ /* Install a dynamic relocation if needed. */
+ if (info->shared
+ || elf64_ia64_dynamic_symbol_p (dyn_i->h, info)
+ || (dynindx != -1 && dyn_r_type == R_IA64_FPTR64LSB))
+ {
+ if (dynindx == -1)
+ {
+ dyn_r_type = R_IA64_REL64LSB;
+ dynindx = 0;
+ addend = value;
+ }
+
+ if (bfd_big_endian (abfd))
+ {
+ switch (dyn_r_type)
+ {
+ case R_IA64_REL64LSB:
+ dyn_r_type = R_IA64_REL64MSB;
+ break;
+ case R_IA64_DIR64LSB:
+ dyn_r_type = R_IA64_DIR64MSB;
+ break;
+ case R_IA64_FPTR64LSB:
+ dyn_r_type = R_IA64_FPTR64MSB;
+ break;
+ default:
+ BFD_ASSERT (false);
+ break;
+ }
+ }
+
+ elf64_ia64_install_dyn_reloc (abfd, NULL, got_sec,
+ ia64_info->rel_got_sec,
+ dyn_i->got_offset, dyn_r_type,
+ dynindx, addend);
+ }
+ }
+
+ /* Return the address of the linkage table entry. */
+ value = (got_sec->output_section->vma
+ + got_sec->output_offset
+ + dyn_i->got_offset);
+
+ return value;
+}
+
+/* Fill in a function descriptor consisting of the function's code
+ address and its global pointer. Return the descriptor's address. */
+
+static bfd_vma
+set_fptr_entry (abfd, info, dyn_i, value)
+ bfd *abfd;
+ struct bfd_link_info *info;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ bfd_vma value;
+{
+ struct elf64_ia64_link_hash_table *ia64_info;
+ asection *fptr_sec;
+
+ ia64_info = elf64_ia64_hash_table (info);
+ fptr_sec = ia64_info->fptr_sec;
+
+ if (!dyn_i->fptr_done)
+ {
+ dyn_i->fptr_done = 1;
+
+ /* Fill in the function descriptor. */
+ bfd_put_64 (abfd, value, fptr_sec->contents + dyn_i->fptr_offset);
+ bfd_put_64 (abfd, _bfd_get_gp_value (abfd),
+ fptr_sec->contents + dyn_i->fptr_offset + 8);
+ }
+
+ /* Return the descriptor's address. */
+ value = (fptr_sec->output_section->vma
+ + fptr_sec->output_offset
+ + dyn_i->fptr_offset);
+
+ return value;
+}
+
+/* Fill in a PLTOFF entry consisting of the function's code address
+ and its global pointer. Return the descriptor's address. */
+
+static bfd_vma
+set_pltoff_entry (abfd, info, dyn_i, value, is_plt)
+ bfd *abfd;
+ struct bfd_link_info *info;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ bfd_vma value;
+ boolean is_plt;
+{
+ struct elf64_ia64_link_hash_table *ia64_info;
+ asection *pltoff_sec;
+
+ ia64_info = elf64_ia64_hash_table (info);
+ pltoff_sec = ia64_info->pltoff_sec;
+
+ /* Don't do anything if this symbol uses a real PLT entry. In
+ that case, we'll fill this in during finish_dynamic_symbol. */
+ if ((! dyn_i->want_plt || is_plt)
+ && !dyn_i->pltoff_done)
+ {
+ /* Fill in the function descriptor. */
+ bfd_put_64 (abfd, value, pltoff_sec->contents + dyn_i->pltoff_offset);
+ bfd_put_64 (abfd, _bfd_get_gp_value (abfd),
+ pltoff_sec->contents + dyn_i->pltoff_offset + 8);
+
+ /* Install dynamic relocations if needed. */
+ if (!is_plt && info->shared)
+ {
+ unsigned int dyn_r_type;
+
+ if (bfd_big_endian (abfd))
+ dyn_r_type = R_IA64_REL64MSB;
+ else
+ dyn_r_type = R_IA64_REL64LSB;
+
+ elf64_ia64_install_dyn_reloc (abfd, NULL, pltoff_sec,
+ ia64_info->rel_pltoff_sec,
+ dyn_i->pltoff_offset,
+ dyn_r_type, 0, 0);
+ elf64_ia64_install_dyn_reloc (abfd, NULL, pltoff_sec,
+ ia64_info->rel_pltoff_sec,
+ dyn_i->pltoff_offset + 8,
+ dyn_r_type, 0, 0);
+ }
+
+ dyn_i->pltoff_done = 1;
+ }
+
+ /* Return the descriptor's address. */
+ value = (pltoff_sec->output_section->vma
+ + pltoff_sec->output_offset
+ + dyn_i->pltoff_offset);
+
+ return value;
+}
+
+static boolean
+elf64_ia64_final_link (abfd, info)
+ bfd *abfd;
+ struct bfd_link_info *info;
+{
+ struct elf64_ia64_link_hash_table *ia64_info;
+ ia64_info = elf64_ia64_hash_table (info);
+
+ /* Make sure we've got ourselves a nice fat __gp value. */
+ if (!info->relocateable)
+ {
+ bfd_vma min_vma = (bfd_vma) -1, max_vma = 0;
+ bfd_vma min_short_vma = min_vma, max_short_vma = 0;
+ struct elf_link_hash_entry *gp;
+ bfd_vma gp_val;
+ asection *os;
+
+ /* Find the min and max vma of all sections marked short. Also
+ collect min and max vma of any type, for use in selecting a
+ nice gp. */
+ for (os = abfd->sections; os ; os = os->next)
+ {
+ bfd_vma lo, hi;
+
+ if ((os->flags & SEC_ALLOC) == 0)
+ continue;
+
+ lo = os->vma;
+ hi = os->vma + os->_raw_size;
+ if (hi < lo)
+ hi = (bfd_vma) -1;
+
+ if (min_vma > lo)
+ min_vma = lo;
+ if (max_vma < hi)
+ max_vma = hi;
+ if (os->flags & SEC_SMALL_DATA)
+ {
+ if (min_short_vma > lo)
+ min_short_vma = lo;
+ if (max_short_vma < hi)
+ max_short_vma = hi;
+ }
+ }
+
+ /* See if the user wants to force a value. */
+ gp = elf_link_hash_lookup (elf_hash_table (info), "__gp", false,
+ false, false);
+
+ if (gp
+ && (gp->root.type == bfd_link_hash_defined
+ || gp->root.type == bfd_link_hash_defweak))
+ {
+ asection *gp_sec = gp->root.u.def.section;
+ gp_val = (gp->root.u.def.value
+ + gp_sec->output_section->vma
+ + gp_sec->output_offset);
+ }
+ else
+ {
+ /* Pick a sensible value. */
+
+ asection *got_sec = ia64_info->got_sec;
+
+ /* Start with just the address of the .got. */
+ if (got_sec)
+ gp_val = got_sec->output_section->vma;
+ else if (max_short_vma != 0)
+ gp_val = min_short_vma;
+ else
+ gp_val = min_vma;
+
+ /* If it is possible to address the entire image, but we
+ don't with the choice above, adjust. */
+ if (max_vma - min_vma < 0x400000
+ && max_vma - gp_val <= 0x200000
+ && gp_val - min_vma > 0x200000)
+ gp_val = min_vma + 0x200000;
+ else if (max_short_vma != 0)
+ {
+ /* If we don't cover all the short data, adjust. */
+ if (max_short_vma - gp_val >= 0x200000)
+ gp_val = min_short_vma + 0x200000;
+
+ /* If we're addressing stuff past the end, adjust back. */
+ if (gp_val > max_vma)
+ gp_val = max_vma - 0x200000 + 8;
+ }
+ }
+
+ /* Validate whether all SHF_IA_64_SHORT sections are within
+ range of the chosen GP. */
+
+ if (max_short_vma != 0)
+ {
+ if (max_short_vma - min_short_vma >= 0x400000)
+ {
+ (*_bfd_error_handler)
+ (_("%s: short data segment overflowed (0x%lx >= 0x400000)"),
+ bfd_get_filename (abfd),
+ (unsigned long)(max_short_vma - min_short_vma));
+ return false;
+ }
+ else if ((gp_val > min_short_vma
+ && gp_val - min_short_vma > 0x200000)
+ || (gp_val < max_short_vma
+ && max_short_vma - gp_val >= 0x200000))
+ {
+ (*_bfd_error_handler)
+ (_("%s: __gp does not cover short data segment"),
+ bfd_get_filename (abfd));
+ return false;
+ }
+ }
+
+ _bfd_set_gp_value (abfd, gp_val);
+ }
+
+ /* Tricky bits. DT_INIT and DT_FINI use a pltoff entry, which is
+ normally initialized in finish_dynamic_sections. Except that
+ we need all non-plt pltoff entries to be initialized before
+ finish_dynamic_symbols. This because the array of relocations
+ used for plt entries (aka DT_JMPREL) begins after all the
+ non-plt pltoff relocations. If the order gets confused, we
+ munge either the array or the array base. */
+ if (ia64_info->root.dynamic_sections_created)
+ {
+ struct elf_link_hash_entry *h;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ bfd_vma addr;
+
+ if (info->init_function
+ && (h = elf_link_hash_lookup (elf_hash_table (info),
+ info->init_function, false,
+ false, false))
+ && (h->elf_link_hash_flags & (ELF_LINK_HASH_REF_REGULAR
+ | ELF_LINK_HASH_DEF_REGULAR)) != 0)
+ {
+ dyn_i = get_dyn_sym_info (ia64_info, h, NULL, NULL, false);
+ addr = (h->root.u.def.section->output_section->vma
+ + h->root.u.def.section->output_offset
+ + h->root.u.def.value);
+ (void) set_pltoff_entry (abfd, info, dyn_i, addr, false);
+ }
+
+ if (info->fini_function
+ && (h = elf_link_hash_lookup (elf_hash_table (info),
+ info->fini_function, false,
+ false, false))
+ && (h->elf_link_hash_flags & (ELF_LINK_HASH_REF_REGULAR
+ | ELF_LINK_HASH_DEF_REGULAR)) != 0)
+ {
+ dyn_i = get_dyn_sym_info (ia64_info, h, NULL, NULL, false);
+ addr = (h->root.u.def.section->output_section->vma
+ + h->root.u.def.section->output_offset
+ + h->root.u.def.value);
+ (void) set_pltoff_entry (abfd, info, dyn_i, addr, false);
+ }
+ }
+
+ /* Invoke the regular ELF backend linker to do all the work. */
+ return bfd_elf64_bfd_final_link (abfd, info);
+}
+
+static boolean
+elf64_ia64_relocate_section (output_bfd, info, input_bfd, input_section,
+ contents, relocs, local_syms, local_sections)
+ bfd *output_bfd;
+ struct bfd_link_info *info;
+ bfd *input_bfd;
+ asection *input_section;
+ bfd_byte *contents;
+ Elf_Internal_Rela *relocs;
+ Elf_Internal_Sym *local_syms;
+ asection **local_sections;
+{
+ struct elf64_ia64_link_hash_table *ia64_info;
+ Elf_Internal_Shdr *symtab_hdr;
+ Elf_Internal_Rela *rel;
+ Elf_Internal_Rela *relend;
+ asection *srel;
+ boolean ret_val = true; /* for non-fatal errors */
+ bfd_vma gp_val;
+
+ symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
+ ia64_info = elf64_ia64_hash_table (info);
+
+ /* Infect various flags from the input section to the output section. */
+ if (info->relocateable)
+ {
+ bfd_vma flags;
+
+ flags = elf_section_data(input_section)->this_hdr.sh_flags;
+ flags &= SHF_IA_64_NORECOV;
+
+ elf_section_data(input_section->output_section)
+ ->this_hdr.sh_flags |= flags;
+ }
+
+ gp_val = _bfd_get_gp_value (output_bfd);
+ srel = get_reloc_section (input_bfd, ia64_info, input_section, false);
+
+ rel = relocs;
+ relend = relocs + input_section->reloc_count;
+ for (; rel < relend; ++rel)
+ {
+ struct elf_link_hash_entry *h;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ bfd_reloc_status_type r;
+ reloc_howto_type *howto;
+ unsigned long r_symndx;
+ Elf_Internal_Sym *sym;
+ unsigned int r_type;
+ bfd_vma value;
+ asection *sym_sec;
+ bfd_byte *hit_addr;
+ boolean dynamic_symbol_p;
+ boolean undef_weak_ref;
+
+ r_type = ELF64_R_TYPE (rel->r_info);
+ if (r_type > R_IA64_MAX_RELOC_CODE)
+ {
+ (*_bfd_error_handler)
+ (_("%s: unknown relocation type %d"),
+ bfd_get_filename (input_bfd), (int)r_type);
+ bfd_set_error (bfd_error_bad_value);
+ ret_val = false;
+ continue;
+ }
+ howto = lookup_howto (r_type);
+ r_symndx = ELF64_R_SYM (rel->r_info);
+
+ if (info->relocateable)
+ {
+ /* This is a relocateable link. We don't have to change
+ anything, unless the reloc is against a section symbol,
+ in which case we have to adjust according to where the
+ section symbol winds up in the output section. */
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ sym = local_syms + r_symndx;
+ if (ELF_ST_TYPE (sym->st_info) == STT_SECTION)
+ {
+ sym_sec = local_sections[r_symndx];
+ rel->r_addend += sym_sec->output_offset;
+ }
+ }
+ continue;
+ }
+
+ /* This is a final link. */
+
+ h = NULL;
+ sym = NULL;
+ sym_sec = NULL;
+ undef_weak_ref = false;
+
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ /* Reloc against local symbol. */
+ sym = local_syms + r_symndx;
+ sym_sec = local_sections[r_symndx];
+ value = (sym_sec->output_section->vma
+ + sym_sec->output_offset
+ + sym->st_value);
+ }
+ else
+ {
+ long indx;
+
+ /* Reloc against global symbol. */
+ indx = r_symndx - symtab_hdr->sh_info;
+ h = elf_sym_hashes (input_bfd)[indx];
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+ value = 0;
+ if (h->root.type == bfd_link_hash_defined
+ || h->root.type == bfd_link_hash_defweak)
+ {
+ sym_sec = h->root.u.def.section;
+
+ /* Detect the cases that sym_sec->output_section is
+ expected to be NULL -- all cases in which the symbol
+ is defined in another shared module. This includes
+ PLT relocs for which we've created a PLT entry and
+ other relocs for which we're prepared to create
+ dynamic relocations. */
+ /* ??? Just accept it NULL and continue. */
+
+ if (sym_sec->output_section != NULL)
+ {
+ value = (h->root.u.def.value
+ + sym_sec->output_section->vma
+ + sym_sec->output_offset);
+ }
+ }
+ else if (h->root.type == bfd_link_hash_undefweak)
+ undef_weak_ref = true;
+ else if (info->shared && !info->symbolic && !info->no_undefined)
+ ;
+ else
+ {
+ if (! ((*info->callbacks->undefined_symbol)
+ (info, h->root.root.string, input_bfd,
+ input_section, rel->r_offset,
+ (!info->shared || info->no_undefined))))
+ return false;
+ ret_val = false;
+ continue;
+ }
+ }
+
+ hit_addr = contents + rel->r_offset;
+ value += rel->r_addend;
+ dynamic_symbol_p = elf64_ia64_dynamic_symbol_p (h, info);
+
+ switch (r_type)
+ {
+ case R_IA64_NONE:
+ case R_IA64_LDXMOV:
+ continue;
+
+ case R_IA64_IMM14:
+ case R_IA64_IMM22:
+ case R_IA64_IMM64:
+ case R_IA64_DIR32MSB:
+ case R_IA64_DIR32LSB:
+ case R_IA64_DIR64MSB:
+ case R_IA64_DIR64LSB:
+ /* Install a dynamic relocation for this reloc. */
+ if ((dynamic_symbol_p || info->shared)
+ && (input_section->flags & SEC_ALLOC) != 0)
+ {
+ unsigned int dyn_r_type;
+ long dynindx;
+
+ BFD_ASSERT (srel != NULL);
+
+ /* If we don't need dynamic symbol lookup, find a
+ matching RELATIVE relocation. */
+ dyn_r_type = r_type;
+ if (dynamic_symbol_p)
+ dynindx = h->dynindx;
+ else
+ {
+ switch (r_type)
+ {
+ case R_IA64_DIR32MSB:
+ dyn_r_type = R_IA64_REL32MSB;
+ break;
+ case R_IA64_DIR32LSB:
+ dyn_r_type = R_IA64_REL32LSB;
+ break;
+ case R_IA64_DIR64MSB:
+ dyn_r_type = R_IA64_REL64MSB;
+ break;
+ case R_IA64_DIR64LSB:
+ dyn_r_type = R_IA64_REL64LSB;
+ break;
+
+ default:
+ /* We can't represent this without a dynamic symbol.
+ Adjust the relocation to be against an output
+ section symbol, which are always present in the
+ dynamic symbol table. */
+ /* ??? People shouldn't be doing non-pic code in
+ shared libraries. Hork. */
+ (*_bfd_error_handler)
+ (_("%s: linking non-pic code in a shared library"),
+ bfd_get_filename (input_bfd));
+ ret_val = false;
+ continue;
+ }
+ dynindx = 0;
+ }
+
+ elf64_ia64_install_dyn_reloc (output_bfd, info, input_section,
+ srel, rel->r_offset, dyn_r_type,
+ dynindx, rel->r_addend);
+ }
+ /* FALLTHRU */
+
+ case R_IA64_LTV32MSB:
+ case R_IA64_LTV32LSB:
+ case R_IA64_LTV64MSB:
+ case R_IA64_LTV64LSB:
+ r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+ break;
+
+ case R_IA64_GPREL22:
+ case R_IA64_GPREL64I:
+ case R_IA64_GPREL32MSB:
+ case R_IA64_GPREL32LSB:
+ case R_IA64_GPREL64MSB:
+ case R_IA64_GPREL64LSB:
+ if (dynamic_symbol_p)
+ {
+ (*_bfd_error_handler)
+ (_("%s: @gprel relocation against dynamic symbol %s"),
+ bfd_get_filename (input_bfd), h->root.root.string);
+ ret_val = false;
+ continue;
+ }
+ value -= gp_val;
+ r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+ break;
+
+ case R_IA64_LTOFF22:
+ case R_IA64_LTOFF22X:
+ case R_IA64_LTOFF64I:
+ dyn_i = get_dyn_sym_info (ia64_info, h, input_bfd, rel, false);
+ value = set_got_entry (input_bfd, info, dyn_i, (h ? h->dynindx : -1),
+ rel->r_addend, value, R_IA64_DIR64LSB);
+ value -= gp_val;
+ r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+ break;
+
+ case R_IA64_PLTOFF22:
+ case R_IA64_PLTOFF64I:
+ case R_IA64_PLTOFF64MSB:
+ case R_IA64_PLTOFF64LSB:
+ dyn_i = get_dyn_sym_info (ia64_info, h, input_bfd, rel, false);
+ value = set_pltoff_entry (output_bfd, info, dyn_i, value, false);
+ value -= gp_val;
+ r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+ break;
+
+ case R_IA64_FPTR64I:
+ case R_IA64_FPTR32MSB:
+ case R_IA64_FPTR32LSB:
+ case R_IA64_FPTR64MSB:
+ case R_IA64_FPTR64LSB:
+ dyn_i = get_dyn_sym_info (ia64_info, h, input_bfd, rel, false);
+ if (dyn_i->want_fptr)
+ {
+ if (!undef_weak_ref)
+ value = set_fptr_entry (output_bfd, info, dyn_i, value);
+ }
+ else
+ {
+ long dynindx;
+
+ /* Otherwise, we expect the dynamic linker to create
+ the entry. */
+
+ if (h)
+ {
+ if (h->dynindx != -1)
+ dynindx = h->dynindx;
+ else
+ dynindx = (_bfd_elf_link_lookup_local_dynindx
+ (info, h->root.u.def.section->owner,
+ global_sym_index (h)));
+ }
+ else
+ {
+ dynindx = (_bfd_elf_link_lookup_local_dynindx
+ (info, input_bfd, r_symndx));
+ }
+
+ elf64_ia64_install_dyn_reloc (output_bfd, info, input_section,
+ srel, rel->r_offset, r_type,
+ dynindx, rel->r_addend);
+ value = 0;
+ }
+
+ r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+ break;
+
+ case R_IA64_LTOFF_FPTR22:
+ case R_IA64_LTOFF_FPTR64I:
+ case R_IA64_LTOFF_FPTR64MSB:
+ case R_IA64_LTOFF_FPTR64LSB:
+ {
+ long dynindx;
+
+ dyn_i = get_dyn_sym_info (ia64_info, h, input_bfd, rel, false);
+ if (dyn_i->want_fptr)
+ {
+ BFD_ASSERT (h == NULL || h->dynindx == -1)
+ if (!undef_weak_ref)
+ value = set_fptr_entry (output_bfd, info, dyn_i, value);
+ dynindx = -1;
+ }
+ else
+ {
+ /* Otherwise, we expect the dynamic linker to create
+ the entry. */
+ if (h)
+ {
+ if (h->dynindx != -1)
+ dynindx = h->dynindx;
+ else
+ dynindx = (_bfd_elf_link_lookup_local_dynindx
+ (info, h->root.u.def.section->owner,
+ global_sym_index (h)));
+ }
+ else
+ dynindx = (_bfd_elf_link_lookup_local_dynindx
+ (info, input_bfd, r_symndx));
+ value = 0;
+ }
+
+ value = set_got_entry (output_bfd, info, dyn_i, dynindx,
+ rel->r_addend, value, R_IA64_FPTR64LSB);
+ value -= gp_val;
+ r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+ }
+ break;
+
+ case R_IA64_PCREL32MSB:
+ case R_IA64_PCREL32LSB:
+ case R_IA64_PCREL64MSB:
+ case R_IA64_PCREL64LSB:
+ /* Install a dynamic relocation for this reloc. */
+ if (dynamic_symbol_p)
+ {
+ BFD_ASSERT (srel != NULL);
+
+ elf64_ia64_install_dyn_reloc (output_bfd, info, input_section,
+ srel, rel->r_offset, r_type,
+ h->dynindx, rel->r_addend);
+ }
+ goto finish_pcrel;
+
+ case R_IA64_PCREL21F:
+ case R_IA64_PCREL21M:
+ /* ??? These two are only used for speculation fixup code.
+ They should never be dynamic. */
+ if (dynamic_symbol_p)
+ {
+ (*_bfd_error_handler)
+ (_("%s: dynamic relocation against speculation fixup"),
+ bfd_get_filename (input_bfd));
+ ret_val = false;
+ continue;
+ }
+ if (undef_weak_ref)
+ {
+ (*_bfd_error_handler)
+ (_("%s: speculation fixup against undefined weak symbol"),
+ bfd_get_filename (input_bfd));
+ ret_val = false;
+ continue;
+ }
+ goto finish_pcrel;
+
+ case R_IA64_PCREL21B:
+ /* We should have created a PLT entry for any dynamic symbol. */
+ /* ??? How to handle out of range branches, which are supposed
+ to be fixed up by a conforming linker. */
+
+ dyn_i = NULL;
+ if (h)
+ dyn_i = get_dyn_sym_info (ia64_info, h, NULL, NULL, false);
+
+ if (dyn_i && dyn_i->want_plt2)
+ {
+ /* Should have caught this earlier. */
+ BFD_ASSERT (rel->r_addend == 0);
+
+ value = (ia64_info->plt_sec->output_section->vma
+ + ia64_info->plt_sec->output_offset
+ + dyn_i->plt2_offset);
+ }
+ else
+ {
+ /* Since there's no PLT entry, Validate that this is
+ locally defined. */
+ BFD_ASSERT (undef_weak_ref || sym_sec->output_section != NULL);
+
+ /* If the symbol is undef_weak, we shouldn't be trying
+ to call it. There's every chance that we'd wind up
+ with an out-of-range fixup here. Don't bother setting
+ any value at all. */
+ if (undef_weak_ref)
+ continue;
+ }
+ goto finish_pcrel;
+
+ finish_pcrel:
+ /* Make pc-relative. */
+ value -= (input_section->output_section->vma
+ + input_section->output_offset
+ + rel->r_offset) & ~ (bfd_vma) 0x3;
+ r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+ break;
+
+ case R_IA64_SEGREL32MSB:
+ case R_IA64_SEGREL32LSB:
+ case R_IA64_SEGREL64MSB:
+ case R_IA64_SEGREL64LSB:
+ {
+ struct elf_segment_map *m;
+ Elf_Internal_Phdr *p;
+
+ /* Find the segment that contains the output_section. */
+ for (m = elf_tdata (output_bfd)->segment_map,
+ p = elf_tdata (output_bfd)->phdr;
+ m != NULL;
+ m = m->next, p++)
+ {
+ int i;
+ for (i = m->count - 1; i >= 0; i--)
+ if (m->sections[i] == sym_sec->output_section)
+ break;
+ if (i >= 0)
+ break;
+ }
+
+ if (m == NULL)
+ {
+ /* If the input section was discarded from the output, then
+ do nothing. */
+
+ if (bfd_is_abs_section (sym_sec->output_section))
+ r = bfd_reloc_ok;
+ else
+ r = bfd_reloc_notsupported;
+ }
+ else
+ {
+ /* The VMA of the segment is the vaddr of the associated
+ program header. */
+ if (value > p->p_vaddr)
+ value -= p->p_vaddr;
+ else
+ value = 0;
+ r = elf64_ia64_install_value (output_bfd, hit_addr, value,
+ r_type);
+ }
+ break;
+ }
+
+ case R_IA64_SECREL32MSB:
+ case R_IA64_SECREL32LSB:
+ case R_IA64_SECREL64MSB:
+ case R_IA64_SECREL64LSB:
+ /* Make output-section relative. */
+ if (value > input_section->output_section->vma)
+ value -= input_section->output_section->vma;
+ else
+ value = 0;
+ r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+ break;
+
+ case R_IA64_SEGBASE:
+
+ case R_IA64_REL32MSB:
+ case R_IA64_REL32LSB:
+ case R_IA64_REL64MSB:
+ case R_IA64_REL64LSB:
+
+ case R_IA64_IPLTMSB:
+ case R_IA64_IPLTLSB:
+ case R_IA64_EPLTMSB:
+ case R_IA64_EPLTLSB:
+ case R_IA64_COPY:
+
+ case R_IA64_TPREL22:
+ case R_IA64_TPREL64MSB:
+ case R_IA64_TPREL64LSB:
+ case R_IA64_LTOFF_TP22:
+ default:
+ r = bfd_reloc_notsupported;
+ break;
+ }
+
+ switch (r)
+ {
+ case bfd_reloc_ok:
+ break;
+
+ case bfd_reloc_undefined:
+ /* This can happen for global table relative relocs if
+ __gp is undefined. This is a panic situation so we
+ don't try to continue. */
+ (*info->callbacks->undefined_symbol)
+ (info, "__gp", input_bfd, input_section, rel->r_offset, 1);
+ return false;
+
+ case bfd_reloc_notsupported:
+ {
+ const char *name;
+
+ if (h)
+ name = h->root.root.string;
+ else
+ {
+ name = bfd_elf_string_from_elf_section (input_bfd,
+ symtab_hdr->sh_link,
+ sym->st_name);
+ if (name == NULL)
+ return false;
+ if (*name == '\0')
+ name = bfd_section_name (input_bfd, input_section);
+ }
+ if (!(*info->callbacks->warning) (info, _("unsupported reloc"),
+ name, input_bfd,
+ input_section, rel->r_offset))
+ return false;
+ ret_val = false;
+ }
+ break;
+
+ case bfd_reloc_dangerous:
+ case bfd_reloc_outofrange:
+ case bfd_reloc_overflow:
+ default:
+ {
+ const char *name;
+
+ if (h)
+ name = h->root.root.string;
+ else
+ {
+ name = bfd_elf_string_from_elf_section (input_bfd,
+ symtab_hdr->sh_link,
+ sym->st_name);
+ if (name == NULL)
+ return false;
+ if (*name == '\0')
+ name = bfd_section_name (input_bfd, input_section);
+ }
+ if (!(*info->callbacks->reloc_overflow) (info, name,
+ howto->name, 0,
+ input_bfd,
+ input_section,
+ rel->r_offset))
+ return false;
+ ret_val = false;
+ }
+ break;
+ }
+ }
+
+ return ret_val;
+}
+
+static boolean
+elf64_ia64_finish_dynamic_symbol (output_bfd, info, h, sym)
+ bfd *output_bfd;
+ struct bfd_link_info *info;
+ struct elf_link_hash_entry *h;
+ Elf_Internal_Sym *sym;
+{
+ struct elf64_ia64_link_hash_table *ia64_info;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+
+ ia64_info = elf64_ia64_hash_table (info);
+ dyn_i = get_dyn_sym_info (ia64_info, h, NULL, NULL, false);
+
+ /* Fill in the PLT data, if required. */
+ if (dyn_i && dyn_i->want_plt)
+ {
+ Elf_Internal_Rela outrel;
+ bfd_byte *loc;
+ asection *plt_sec;
+ bfd_vma plt_addr, pltoff_addr, gp_val, index;
+ Elf64_External_Rela *rel;
+
+ gp_val = _bfd_get_gp_value (output_bfd);
+
+ /* Initialize the minimal PLT entry. */
+
+ index = (dyn_i->plt_offset - PLT_HEADER_SIZE) / PLT_MIN_ENTRY_SIZE;
+ plt_sec = ia64_info->plt_sec;
+ loc = plt_sec->contents + dyn_i->plt_offset;
+
+ memcpy (loc, plt_min_entry, PLT_MIN_ENTRY_SIZE);
+ elf64_ia64_install_value (output_bfd, loc, index, R_IA64_IMM22);
+ elf64_ia64_install_value (output_bfd, loc+2, -dyn_i->plt_offset,
+ R_IA64_PCREL21B);
+
+ plt_addr = (plt_sec->output_section->vma
+ + plt_sec->output_offset
+ + dyn_i->plt_offset);
+ pltoff_addr = set_pltoff_entry (output_bfd, info, dyn_i, plt_addr, true);
+
+ /* Initialize the FULL PLT entry, if needed. */
+ if (dyn_i->want_plt2)
+ {
+ loc = plt_sec->contents + dyn_i->plt2_offset;
+
+ memcpy (loc, plt_full_entry, PLT_FULL_ENTRY_SIZE);
+ elf64_ia64_install_value (output_bfd, loc, pltoff_addr - gp_val,
+ R_IA64_IMM22);
+
+ /* Mark the symbol as undefined, rather than as defined in the
+ plt section. Leave the value alone. */
+ /* ??? We didn't redefine it in adjust_dynamic_symbol in the
+ first place. But perhaps elflink.h did some for us. */
+ if ((h->elf_link_hash_flags & ELF_LINK_HASH_DEF_REGULAR) == 0)
+ sym->st_shndx = SHN_UNDEF;
+ }
+
+ /* Create the dynamic relocation. */
+ outrel.r_offset = pltoff_addr;
+ if (bfd_little_endian (output_bfd))
+ outrel.r_info = ELF64_R_INFO (h->dynindx, R_IA64_IPLTLSB);
+ else
+ outrel.r_info = ELF64_R_INFO (h->dynindx, R_IA64_IPLTMSB);
+ outrel.r_addend = 0;
+
+ /* This is fun. In the .IA_64.pltoff section, we've got entries
+ that correspond both to real PLT entries, and those that
+ happened to resolve to local symbols but need to be created
+ to satisfy @pltoff relocations. The .rela.IA_64.pltoff
+ relocations for the real PLT should come at the end of the
+ section, so that they can be indexed by plt entry at runtime.
+
+ We emitted all of the relocations for the non-PLT @pltoff
+ entries during relocate_section. So we can consider the
+ existing sec->reloc_count to be the base of the array of
+ PLT relocations. */
+
+ rel = (Elf64_External_Rela *)ia64_info->rel_pltoff_sec->contents;
+ rel += ia64_info->rel_pltoff_sec->reloc_count;
+
+ bfd_elf64_swap_reloca_out (output_bfd, &outrel, rel + index);
+ }
+
+ /* Mark some specially defined symbols as absolute. */
+ if (strcmp (h->root.root.string, "_DYNAMIC") == 0
+ || strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0
+ || strcmp (h->root.root.string, "_PROCEDURE_LINKAGE_TABLE_") == 0)
+ sym->st_shndx = SHN_ABS;
+
+ return true;
+}
+
+static boolean
+elf64_ia64_finish_dynamic_sections (abfd, info)
+ bfd *abfd;
+ struct bfd_link_info *info;
+{
+ struct elf64_ia64_link_hash_table *ia64_info;
+ bfd *dynobj;
+
+ ia64_info = elf64_ia64_hash_table (info);
+ dynobj = ia64_info->root.dynobj;
+
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ Elf64_External_Dyn *dyncon, *dynconend;
+ asection *sdyn, *sgotplt;
+ bfd_vma gp_val;
+
+ sdyn = bfd_get_section_by_name (dynobj, ".dynamic");
+ sgotplt = bfd_get_section_by_name (dynobj, ".got.plt");
+ BFD_ASSERT (sdyn != NULL);
+ dyncon = (Elf64_External_Dyn *) sdyn->contents;
+ dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->_raw_size);
+
+ gp_val = _bfd_get_gp_value (abfd);
+
+ for (; dyncon < dynconend; dyncon++)
+ {
+ Elf_Internal_Dyn dyn;
+ const char *name;
+ asection *s;
+
+ bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn);
+
+ switch (dyn.d_tag)
+ {
+ case DT_PLTGOT:
+ dyn.d_un.d_ptr = gp_val;
+ break;
+
+ case DT_PLTRELSZ:
+ dyn.d_un.d_val = (ia64_info->minplt_entries
+ * sizeof (Elf64_External_Rela));
+ break;
+
+ case DT_JMPREL:
+ /* See the comment above in finish_dynamic_symbol. */
+ dyn.d_un.d_ptr = (ia64_info->rel_pltoff_sec->output_section->vma
+ + ia64_info->rel_pltoff_sec->output_offset
+ + (ia64_info->rel_pltoff_sec->reloc_count
+ * sizeof (Elf64_External_Rela)));
+ break;
+
+ case DT_IA_64_PLT_RESERVE:
+ dyn.d_un.d_ptr = (sgotplt->output_section->vma
+ + sgotplt->output_offset);
+ break;
+
+ case DT_RELASZ:
+ /* Do not have RELASZ include JMPREL. This makes things
+ easier on ld.so. This is not what the rest of BFD set up. */
+ dyn.d_un.d_val -= (ia64_info->minplt_entries
+ * sizeof (Elf64_External_Rela));
+ break;
+
+ case DT_INIT:
+ case DT_FINI:
+ {
+ struct elf_link_hash_entry *h;
+ struct elf64_ia64_dyn_sym_info *dyn_i;
+ const char *which;
+
+ if (dyn.d_tag == DT_INIT)
+ which = info->init_function;
+ else
+ which = info->fini_function;
+
+ h = elf_link_hash_lookup (elf_hash_table (info), which,
+ false, false, false);
+ dyn_i = get_dyn_sym_info (ia64_info, h, NULL, NULL, false);
+ dyn.d_un.d_ptr = set_pltoff_entry (abfd, info, dyn_i,
+ dyn.d_un.d_ptr, 0);
+ }
+ }
+
+ bfd_elf64_swap_dyn_out (abfd, &dyn, dyncon);
+ }
+
+ /* Initialize the PLT0 entry */
+ if (ia64_info->plt_sec)
+ {
+ bfd_byte *loc = ia64_info->plt_sec->contents;
+ bfd_vma pltres;
+
+ memcpy (loc, plt_header, PLT_HEADER_SIZE);
+
+ pltres = (sgotplt->output_section->vma
+ + sgotplt->output_offset
+ - gp_val);
+
+ elf64_ia64_install_value (abfd, loc+1, pltres, R_IA64_GPREL22);
+ }
+ }
+
+ return true;
+}
+\f
+/* ELF file flag handling: */
+
+/* Function to keep IA-64 specific file flags. */
+static boolean
+elf64_ia64_set_private_flags (abfd, flags)
+ bfd *abfd;
+ flagword flags;
+{
+ BFD_ASSERT (!elf_flags_init (abfd)
+ || elf_elfheader (abfd)->e_flags == flags);
+
+ elf_elfheader (abfd)->e_flags = flags;
+ elf_flags_init (abfd) = true;
+ return true;
+}
+
+/* Copy backend specific data from one object module to another */
+static boolean
+elf64_ia64_copy_private_bfd_data (ibfd, obfd)
+ bfd *ibfd, *obfd;
+{
+ if ( bfd_get_flavour (ibfd) != bfd_target_elf_flavour
+ || bfd_get_flavour (obfd) != bfd_target_elf_flavour)
+ return true;
+
+ BFD_ASSERT (!elf_flags_init (obfd)
+ || (elf_elfheader (obfd)->e_flags
+ == elf_elfheader (ibfd)->e_flags));
+
+ elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags;
+ elf_flags_init (obfd) = true;
+ return true;
+}
+
+/* Merge backend specific data from an object file to the output
+ object file when linking. */
+static boolean
+elf64_ia64_merge_private_bfd_data (ibfd, obfd)
+ bfd *ibfd, *obfd;
+{
+ flagword out_flags;
+ flagword in_flags;
+ boolean ok = true;
+
+ /* Don't even pretend to support mixed-format linking. */
+ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour
+ || bfd_get_flavour (obfd) != bfd_target_elf_flavour)
+ return false;
+
+ in_flags = elf_elfheader (ibfd)->e_flags;
+ out_flags = elf_elfheader (obfd)->e_flags;
+
+ if (! elf_flags_init (obfd))
+ {
+ elf_flags_init (obfd) = true;
+ elf_elfheader (obfd)->e_flags = in_flags;
+
+ if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
+ && bfd_get_arch_info (obfd)->the_default)
+ {
+ return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd),
+ bfd_get_mach (ibfd));
+ }
+
+ return true;
+ }
+
+ /* Check flag compatibility. */
+ if (in_flags == out_flags)
+ return true;
+
+ if ((in_flags & EF_IA_64_TRAPNIL) != (out_flags & EF_IA_64_TRAPNIL))
+ {
+ (*_bfd_error_handler)
+ (_("%s: linking trap-on-NULL-dereference with non-trapping files"),
+ bfd_get_filename (ibfd));
+
+ bfd_set_error (bfd_error_bad_value);
+ ok = false;
+ }
+ if ((in_flags & EF_IA_64_BE) != (out_flags & EF_IA_64_BE))
+ {
+ (*_bfd_error_handler)
+ (_("%s: linking big-endian files with little-endian files"),
+ bfd_get_filename (ibfd));
+
+ bfd_set_error (bfd_error_bad_value);
+ ok = false;
+ }
+ if ((in_flags & EF_IA_64_ABI64) != (out_flags & EF_IA_64_ABI64))
+ {
+ (*_bfd_error_handler)
+ (_("%s: linking 64-bit files with 32-bit files"),
+ bfd_get_filename (ibfd));
+
+ bfd_set_error (bfd_error_bad_value);
+ ok = false;
+ }
+
+ return ok;
+}
+
+static boolean
+elf64_ia64_print_private_bfd_data (abfd, ptr)
+ bfd *abfd;
+ PTR ptr;
+{
+ FILE *file = (FILE *) ptr;
+ flagword flags = elf_elfheader (abfd)->e_flags;
+
+ BFD_ASSERT (abfd != NULL && ptr != NULL);
+
+ fprintf (file, "private flags = %s%s%s%s\n",
+ (flags & EF_IA_64_TRAPNIL) ? "TRAPNIL, " : "",
+ (flags & EF_IA_64_EXT) ? "EXT, " : "",
+ (flags & EF_IA_64_BE) ? "BE, " : "LE, ",
+ (flags & EF_IA_64_ABI64) ? "ABI64" : "ABI32");
+ _bfd_elf_print_private_bfd_data (abfd, ptr);
+ return true;
+}
+\f
+#define TARGET_LITTLE_SYM bfd_elf64_ia64_little_vec
+#define TARGET_LITTLE_NAME "elf64-ia64-little"
+#define TARGET_BIG_SYM bfd_elf64_ia64_big_vec
+#define TARGET_BIG_NAME "elf64-ia64-big"
+#define ELF_ARCH bfd_arch_ia64
+#define ELF_MACHINE_CODE EM_IA_64
+#define ELF_MACHINE_ALT1 1999 /* EAS2.3 */
+#define ELF_MACHINE_ALT2 1998 /* EAS2.2 */
+#define ELF_MAXPAGESIZE 0x10000 /* 64KB */
+
+#define elf_backend_section_from_shdr \
+ elf64_ia64_section_from_shdr
+#define elf_backend_fake_sections \
+ elf64_ia64_fake_sections
+#define elf_backend_add_symbol_hook \
+ elf64_ia64_add_symbol_hook
+#define elf_backend_additional_program_headers \
+ elf64_ia64_additional_program_headers
+#define elf_backend_modify_segment_map \
+ elf64_ia64_modify_segment_map
+#define elf_info_to_howto \
+ elf64_ia64_info_to_howto
+
+#define bfd_elf64_bfd_reloc_type_lookup \
+ elf64_ia64_reloc_type_lookup
+#define bfd_elf64_bfd_is_local_label_name \
+ elf64_ia64_is_local_label_name
+
+/* Stuff for the BFD linker: */
+#define bfd_elf64_bfd_link_hash_table_create \
+ elf64_ia64_hash_table_create
+#define elf_backend_create_dynamic_sections \
+ elf64_ia64_create_dynamic_sections
+#define elf_backend_check_relocs \
+ elf64_ia64_check_relocs
+#define elf_backend_adjust_dynamic_symbol \
+ elf64_ia64_adjust_dynamic_symbol
+#define elf_backend_size_dynamic_sections \
+ elf64_ia64_size_dynamic_sections
+#define elf_backend_relocate_section \
+ elf64_ia64_relocate_section
+#define elf_backend_finish_dynamic_symbol \
+ elf64_ia64_finish_dynamic_symbol
+#define elf_backend_finish_dynamic_sections \
+ elf64_ia64_finish_dynamic_sections
+#define bfd_elf64_bfd_final_link \
+ elf64_ia64_final_link
+
+#define bfd_elf64_bfd_copy_private_bfd_data \
+ elf64_ia64_copy_private_bfd_data
+#define bfd_elf64_bfd_merge_private_bfd_data \
+ elf64_ia64_merge_private_bfd_data
+#define bfd_elf64_bfd_set_private_flags \
+ elf64_ia64_set_private_flags
+#define bfd_elf64_bfd_print_private_bfd_data \
+ elf64_ia64_print_private_bfd_data
+
+#define elf_backend_plt_readonly 1
+#define elf_backend_want_plt_sym 0
+#define elf_backend_plt_alignment 5
+#define elf_backend_got_header_size 0
+#define elf_backend_plt_header_size PLT_HEADER_SIZE
+#define elf_backend_want_got_plt 1
+#define elf_backend_may_use_rel_p 1
+#define elf_backend_may_use_rela_p 1
+#define elf_backend_default_use_rela_p 1
+#define elf_backend_want_dynbss 0
+#define elf_backend_copy_indirect_symbol elf64_ia64_hash_copy_indirect
+#define elf_backend_hide_symbol elf64_ia64_hash_hide_symbol
+
+#include "elf64-target.h"
"BFD_RELOC_AVR_CALL",
"BFD_RELOC_VTABLE_INHERIT",
"BFD_RELOC_VTABLE_ENTRY",
+ "BFD_RELOC_IA64_IMM14",
+ "BFD_RELOC_IA64_IMM22",
+ "BFD_RELOC_IA64_IMM64",
+ "BFD_RELOC_IA64_DIR32MSB",
+ "BFD_RELOC_IA64_DIR32LSB",
+ "BFD_RELOC_IA64_DIR64MSB",
+ "BFD_RELOC_IA64_DIR64LSB",
+ "BFD_RELOC_IA64_GPREL22",
+ "BFD_RELOC_IA64_GPREL64I",
+ "BFD_RELOC_IA64_GPREL32MSB",
+ "BFD_RELOC_IA64_GPREL32LSB",
+ "BFD_RELOC_IA64_GPREL64MSB",
+ "BFD_RELOC_IA64_GPREL64LSB",
+ "BFD_RELOC_IA64_LTOFF22",
+ "BFD_RELOC_IA64_LTOFF64I",
+ "BFD_RELOC_IA64_PLTOFF22",
+ "BFD_RELOC_IA64_PLTOFF64I",
+ "BFD_RELOC_IA64_PLTOFF64MSB",
+ "BFD_RELOC_IA64_PLTOFF64LSB",
+ "BFD_RELOC_IA64_FPTR64I",
+ "BFD_RELOC_IA64_FPTR32MSB",
+ "BFD_RELOC_IA64_FPTR32LSB",
+ "BFD_RELOC_IA64_FPTR64MSB",
+ "BFD_RELOC_IA64_FPTR64LSB",
+ "BFD_RELOC_IA64_PCREL21B",
+ "BFD_RELOC_IA64_PCREL21M",
+ "BFD_RELOC_IA64_PCREL21F",
+ "BFD_RELOC_IA64_PCREL32MSB",
+ "BFD_RELOC_IA64_PCREL32LSB",
+ "BFD_RELOC_IA64_PCREL64MSB",
+ "BFD_RELOC_IA64_PCREL64LSB",
+ "BFD_RELOC_IA64_LTOFF_FPTR22",
+ "BFD_RELOC_IA64_LTOFF_FPTR64I",
+ "BFD_RELOC_IA64_LTOFF_FPTR64MSB",
+ "BFD_RELOC_IA64_LTOFF_FPTR64LSB",
+ "BFD_RELOC_IA64_SEGBASE",
+ "BFD_RELOC_IA64_SEGREL32MSB",
+ "BFD_RELOC_IA64_SEGREL32LSB",
+ "BFD_RELOC_IA64_SEGREL64MSB",
+ "BFD_RELOC_IA64_SEGREL64LSB",
+ "BFD_RELOC_IA64_SECREL32MSB",
+ "BFD_RELOC_IA64_SECREL32LSB",
+ "BFD_RELOC_IA64_SECREL64MSB",
+ "BFD_RELOC_IA64_SECREL64LSB",
+ "BFD_RELOC_IA64_REL32MSB",
+ "BFD_RELOC_IA64_REL32LSB",
+ "BFD_RELOC_IA64_REL64MSB",
+ "BFD_RELOC_IA64_REL64LSB",
+ "BFD_RELOC_IA64_LTV32MSB",
+ "BFD_RELOC_IA64_LTV32LSB",
+ "BFD_RELOC_IA64_LTV64MSB",
+ "BFD_RELOC_IA64_LTV64LSB",
+ "BFD_RELOC_IA64_IPLTMSB",
+ "BFD_RELOC_IA64_IPLTLSB",
+ "BFD_RELOC_IA64_EPLTMSB",
+ "BFD_RELOC_IA64_EPLTLSB",
+ "BFD_RELOC_IA64_COPY",
+ "BFD_RELOC_IA64_TPREL22",
+ "BFD_RELOC_IA64_TPREL64MSB",
+ "BFD_RELOC_IA64_TPREL64LSB",
+ "BFD_RELOC_IA64_LTOFF_TP22",
+ "BFD_RELOC_IA64_LTOFF22X",
+ "BFD_RELOC_IA64_LDXMOV",
"@@overflow: BFD_RELOC_UNUSED@@",
};
#endif
is stored in the reloc's addend. For Rel hosts, we are forced to put
this offset in the reloc's section offset.
+ENUM
+ BFD_RELOC_IA64_IMM14
+ENUMX
+ BFD_RELOC_IA64_IMM22
+ENUMX
+ BFD_RELOC_IA64_IMM64
+ENUMX
+ BFD_RELOC_IA64_DIR32MSB
+ENUMX
+ BFD_RELOC_IA64_DIR32LSB
+ENUMX
+ BFD_RELOC_IA64_DIR64MSB
+ENUMX
+ BFD_RELOC_IA64_DIR64LSB
+ENUMX
+ BFD_RELOC_IA64_GPREL22
+ENUMX
+ BFD_RELOC_IA64_GPREL64I
+ENUMX
+ BFD_RELOC_IA64_GPREL32MSB
+ENUMX
+ BFD_RELOC_IA64_GPREL32LSB
+ENUMX
+ BFD_RELOC_IA64_GPREL64MSB
+ENUMX
+ BFD_RELOC_IA64_GPREL64LSB
+ENUMX
+ BFD_RELOC_IA64_LTOFF22
+ENUMX
+ BFD_RELOC_IA64_LTOFF64I
+ENUMX
+ BFD_RELOC_IA64_PLTOFF22
+ENUMX
+ BFD_RELOC_IA64_PLTOFF64I
+ENUMX
+ BFD_RELOC_IA64_PLTOFF64MSB
+ENUMX
+ BFD_RELOC_IA64_PLTOFF64LSB
+ENUMX
+ BFD_RELOC_IA64_FPTR64I
+ENUMX
+ BFD_RELOC_IA64_FPTR32MSB
+ENUMX
+ BFD_RELOC_IA64_FPTR32LSB
+ENUMX
+ BFD_RELOC_IA64_FPTR64MSB
+ENUMX
+ BFD_RELOC_IA64_FPTR64LSB
+ENUMX
+ BFD_RELOC_IA64_PCREL21B
+ENUMX
+ BFD_RELOC_IA64_PCREL21M
+ENUMX
+ BFD_RELOC_IA64_PCREL21F
+ENUMX
+ BFD_RELOC_IA64_PCREL32MSB
+ENUMX
+ BFD_RELOC_IA64_PCREL32LSB
+ENUMX
+ BFD_RELOC_IA64_PCREL64MSB
+ENUMX
+ BFD_RELOC_IA64_PCREL64LSB
+ENUMX
+ BFD_RELOC_IA64_LTOFF_FPTR22
+ENUMX
+ BFD_RELOC_IA64_LTOFF_FPTR64I
+ENUMX
+ BFD_RELOC_IA64_LTOFF_FPTR64MSB
+ENUMX
+ BFD_RELOC_IA64_LTOFF_FPTR64LSB
+ENUMX
+ BFD_RELOC_IA64_SEGBASE
+ENUMX
+ BFD_RELOC_IA64_SEGREL32MSB
+ENUMX
+ BFD_RELOC_IA64_SEGREL32LSB
+ENUMX
+ BFD_RELOC_IA64_SEGREL64MSB
+ENUMX
+ BFD_RELOC_IA64_SEGREL64LSB
+ENUMX
+ BFD_RELOC_IA64_SECREL32MSB
+ENUMX
+ BFD_RELOC_IA64_SECREL32LSB
+ENUMX
+ BFD_RELOC_IA64_SECREL64MSB
+ENUMX
+ BFD_RELOC_IA64_SECREL64LSB
+ENUMX
+ BFD_RELOC_IA64_REL32MSB
+ENUMX
+ BFD_RELOC_IA64_REL32LSB
+ENUMX
+ BFD_RELOC_IA64_REL64MSB
+ENUMX
+ BFD_RELOC_IA64_REL64LSB
+ENUMX
+ BFD_RELOC_IA64_LTV32MSB
+ENUMX
+ BFD_RELOC_IA64_LTV32LSB
+ENUMX
+ BFD_RELOC_IA64_LTV64MSB
+ENUMX
+ BFD_RELOC_IA64_LTV64LSB
+ENUMX
+ BFD_RELOC_IA64_IPLTMSB
+ENUMX
+ BFD_RELOC_IA64_IPLTLSB
+ENUMX
+ BFD_RELOC_IA64_EPLTMSB
+ENUMX
+ BFD_RELOC_IA64_EPLTLSB
+ENUMX
+ BFD_RELOC_IA64_COPY
+ENUMX
+ BFD_RELOC_IA64_TPREL22
+ENUMX
+ BFD_RELOC_IA64_TPREL64MSB
+ENUMX
+ BFD_RELOC_IA64_TPREL64LSB
+ENUMX
+ BFD_RELOC_IA64_LTOFF_TP22
+ENUMX
+ BFD_RELOC_IA64_LTOFF22X
+ENUMX
+ BFD_RELOC_IA64_LDXMOV
+ENUMDOC
+ Intel IA64 Relocations.
ENDSENUM
BFD_RELOC_UNUSED
CODE_FRAGMENT
extern const bfd_target bfd_efi_app_ia32_vec;
extern const bfd_target bfd_efi_app_ia64_vec;
extern const bfd_target bfd_elf64_alpha_vec;
+extern const bfd_target bfd_elf64_ia64_little_vec;
+extern const bfd_target bfd_elf64_ia64_big_vec;
extern const bfd_target bfd_elf32_avr_vec;
extern const bfd_target bfd_elf32_bigarc_vec;
extern const bfd_target bfd_elf32_bigarm_vec;
&bfd_elf32_big_generic_vec,
#ifdef BFD64
&bfd_elf64_alpha_vec,
+ &bfd_elf64_ia64_little_vec,
+ &bfd_elf64_ia64_big_vec,
#endif
&bfd_elf32_avr_vec,
&bfd_elf32_bigarc_vec,
+Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
+ David Mosberger <davidm@hpl.hp.com>
+
+ * dis-asm.h (print_insn_ia64): Declare.
+
2000-04-05 Richard Henderson <rth@cygnus.com>
* splay-tree.h (splay_tree_remove): Declare.
extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i386_att PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i386_intel PARAMS ((bfd_vma, disassemble_info*));
+extern int print_insn_ia64 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i370 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*));
+Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
+ David Mosberger <davidm@hpl.hp.com>
+
+ * ia64.h: New file.
+
2000-04-14 H.J. Lu <hjl@gnu.org>
* common.h (ELFOSABI_TRUE64): Renamed to ELFOSABI_TRU64.
--- /dev/null
+/* IA-64 ELF support for BFD.
+ Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+
+#ifndef _ELF_IA64_H
+#define _ELF_IA64_H
+
+/* Bits in the e_flags field of the Elf64_Ehdr: */
+
+#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */
+#define EF_IA_64_ABI64 (1 << 4) /* 64-bit ABI */
+#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */
+
+/* ??? These four definitions are not part of the SVR4 ABI.
+ They were present in David's initial code drop, so it is probable
+ that they are used by HP/UX. */
+#define EF_IA_64_TRAPNIL (1 << 0) /* trap NIL pointer dereferences */
+#define EF_IA_64_EXT (1 << 2) /* program uses arch. extensions */
+#define EF_IA_64_BE (1 << 3) /* PSR BE bit set (big-endian) */
+#define EFA_IA_64_EAS2_3 0x23000000 /* ia64 EAS 2.3 */
+
+#define ELF_STRING_ia64_archext ".IA_64.archext"
+#define ELF_STRING_ia64_pltoff ".IA_64.pltoff"
+#define ELF_STRING_ia64_unwind ".IA_64.unwind"
+#define ELF_STRING_ia64_unwind_info ".IA_64.unwind_info"
+
+/* Bits in the sh_flags field of Elf64_Shdr: */
+
+#define SHF_IA_64_SHORT 0x10000000 /* section near gp */
+#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */
+
+/* Possible values for sh_type in Elf64_Shdr: */
+
+#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */
+#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */
+
+/* Bits in the p_flags field of Elf64_Phdr: */
+
+#define PF_IA_64_NORECOV 0x80000000
+
+/* Possible values for p_type in Elf64_Phdr: */
+
+#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */
+#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */
+
+/* Possible values for d_tag in Elf64_Dyn: */
+
+#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0)
+
+/* ia64-specific relocation types: */
+
+/* Relocs apply to specific instructions within a bundle. The least
+ significant 2 bits of the address indicate which instruction in the
+ bundle the reloc refers to (0=first slot, 1=second slow, 2=third
+ slot, 3=undefined) and the remaining bits give the address of the
+ bundle (16 byte aligned).
+
+ The top 5 bits of the reloc code specifies the expression type, the
+ low 3 bits the format of the data word being relocated.
+
+ ??? Relocations below marked ## are not part of the SVR4 processor
+ suppliment. They were present in David's initial code drop, so it
+ is possible that they are used by HP/UX. */
+
+#include "elf/reloc-macros.h"
+
+START_RELOC_NUMBERS (elf_ia64_reloc_type)
+ RELOC_NUMBER (R_IA64_NONE, 0x00) /* none */
+
+ RELOC_NUMBER (R_IA64_IMM14, 0x21) /* symbol + addend, add imm14 */
+ RELOC_NUMBER (R_IA64_IMM22, 0x22) /* symbol + addend, add imm22 */
+ RELOC_NUMBER (R_IA64_IMM64, 0x23) /* symbol + addend, mov imm64 */
+ RELOC_NUMBER (R_IA64_DIR32MSB, 0x24) /* symbol + addend, data4 MSB */
+ RELOC_NUMBER (R_IA64_DIR32LSB, 0x25) /* symbol + addend, data4 LSB */
+ RELOC_NUMBER (R_IA64_DIR64MSB, 0x26) /* symbol + addend, data8 MSB */
+ RELOC_NUMBER (R_IA64_DIR64LSB, 0x27) /* symbol + addend, data8 LSB */
+
+ RELOC_NUMBER (R_IA64_GPREL22, 0x2a) /* @gprel(sym + add), add imm22 */
+ RELOC_NUMBER (R_IA64_GPREL64I, 0x2b) /* @gprel(sym + add), mov imm64 */
+ RELOC_NUMBER (R_IA64_GPREL32MSB, 0x2c) /* @gprel(sym + add), data4 MSB ## */
+ RELOC_NUMBER (R_IA64_GPREL32LSB, 0x2d) /* @gprel(sym + add), data4 LSB ## */
+ RELOC_NUMBER (R_IA64_GPREL64MSB, 0x2e) /* @gprel(sym + add), data8 MSB */
+ RELOC_NUMBER (R_IA64_GPREL64LSB, 0x2f) /* @gprel(sym + add), data8 LSB */
+
+ RELOC_NUMBER (R_IA64_LTOFF22, 0x32) /* @ltoff(sym + add), add imm22 */
+ RELOC_NUMBER (R_IA64_LTOFF64I, 0x33) /* @ltoff(sym + add), mov imm64 */
+
+ RELOC_NUMBER (R_IA64_PLTOFF22, 0x3a) /* @pltoff(sym + add), add imm22 */
+ RELOC_NUMBER (R_IA64_PLTOFF64I, 0x3b) /* @pltoff(sym + add), mov imm64 */
+ RELOC_NUMBER (R_IA64_PLTOFF64MSB, 0x3e) /* @pltoff(sym + add), data8 MSB */
+ RELOC_NUMBER (R_IA64_PLTOFF64LSB, 0x3f) /* @pltoff(sym + add), data8 LSB */
+
+ RELOC_NUMBER (R_IA64_FPTR64I, 0x43) /* @fptr(sym + add), mov imm64 */
+ RELOC_NUMBER (R_IA64_FPTR32MSB, 0x44) /* @fptr(sym + add), data4 MSB */
+ RELOC_NUMBER (R_IA64_FPTR32LSB, 0x45) /* @fptr(sym + add), data4 LSB */
+ RELOC_NUMBER (R_IA64_FPTR64MSB, 0x46) /* @fptr(sym + add), data8 MSB */
+ RELOC_NUMBER (R_IA64_FPTR64LSB, 0x47) /* @fptr(sym + add), data8 LSB */
+
+ RELOC_NUMBER (R_IA64_PCREL21B, 0x49) /* @pcrel(sym + add), ptb, call */
+ RELOC_NUMBER (R_IA64_PCREL21M, 0x4a) /* @pcrel(sym + add), chk.s */
+ RELOC_NUMBER (R_IA64_PCREL21F, 0x4b) /* @pcrel(sym + add), fchkf */
+ RELOC_NUMBER (R_IA64_PCREL32MSB, 0x4c) /* @pcrel(sym + add), data4 MSB */
+ RELOC_NUMBER (R_IA64_PCREL32LSB, 0x4d) /* @pcrel(sym + add), data4 LSB */
+ RELOC_NUMBER (R_IA64_PCREL64MSB, 0x4e) /* @pcrel(sym + add), data8 MSB */
+ RELOC_NUMBER (R_IA64_PCREL64LSB, 0x4f) /* @pcrel(sym + add), data8 LSB */
+
+ RELOC_NUMBER (R_IA64_LTOFF_FPTR22, 0x52) /* @ltoff(@fptr(s+a)), imm22 */
+ RELOC_NUMBER (R_IA64_LTOFF_FPTR64I, 0x53) /* @ltoff(@fptr(s+a)), imm64 */
+ RELOC_NUMBER (R_IA64_LTOFF_FPTR64MSB, 0x56) /* @ltoff(@fptr(s+a)), 8 MSB ##*/
+ RELOC_NUMBER (R_IA64_LTOFF_FPTR64LSB, 0x57) /* @ltoff(@fptr(s+a)), 8 LSB ##*/
+
+ RELOC_NUMBER (R_IA64_SEGBASE, 0x58) /* set segment base for @segrel ## */
+ RELOC_NUMBER (R_IA64_SEGREL32MSB, 0x5c) /* @segrel(sym + add), data4 MSB */
+ RELOC_NUMBER (R_IA64_SEGREL32LSB, 0x5d) /* @segrel(sym + add), data4 LSB */
+ RELOC_NUMBER (R_IA64_SEGREL64MSB, 0x5e) /* @segrel(sym + add), data8 MSB */
+ RELOC_NUMBER (R_IA64_SEGREL64LSB, 0x5f) /* @segrel(sym + add), data8 LSB */
+
+ RELOC_NUMBER (R_IA64_SECREL32MSB, 0x64) /* @secrel(sym + add), data4 MSB */
+ RELOC_NUMBER (R_IA64_SECREL32LSB, 0x65) /* @secrel(sym + add), data4 LSB */
+ RELOC_NUMBER (R_IA64_SECREL64MSB, 0x66) /* @secrel(sym + add), data8 MSB */
+ RELOC_NUMBER (R_IA64_SECREL64LSB, 0x67) /* @secrel(sym + add), data8 LSB */
+
+ RELOC_NUMBER (R_IA64_REL32MSB, 0x6c) /* data 4 + REL */
+ RELOC_NUMBER (R_IA64_REL32LSB, 0x6d) /* data 4 + REL */
+ RELOC_NUMBER (R_IA64_REL64MSB, 0x6e) /* data 8 + REL */
+ RELOC_NUMBER (R_IA64_REL64LSB, 0x6f) /* data 8 + REL */
+
+ RELOC_NUMBER (R_IA64_LTV32MSB, 0x70) /* symbol + addend, data4 MSB */
+ RELOC_NUMBER (R_IA64_LTV32LSB, 0x71) /* symbol + addend, data4 LSB */
+ RELOC_NUMBER (R_IA64_LTV64MSB, 0x72) /* symbol + addend, data8 MSB */
+ RELOC_NUMBER (R_IA64_LTV64LSB, 0x73) /* symbol + addend, data8 LSB */
+
+ RELOC_NUMBER (R_IA64_IPLTMSB, 0x80) /* dynamic reloc, imported PLT, MSB */
+ RELOC_NUMBER (R_IA64_IPLTLSB, 0x81) /* dynamic reloc, imported PLT, LSB */
+ RELOC_NUMBER (R_IA64_EPLTMSB, 0x82) /* dynamic reloc, exported PLT, ## */
+ RELOC_NUMBER (R_IA64_EPLTLSB, 0x83) /* dynamic reloc, exported PLT, ## */
+ RELOC_NUMBER (R_IA64_COPY, 0x84) /* dynamic reloc, data copy ## */
+ RELOC_NUMBER (R_IA64_LTOFF22X, 0x86) /* LTOFF22, relaxable. */
+ RELOC_NUMBER (R_IA64_LDXMOV, 0x87) /* Use of LTOFF22X. */
+
+ RELOC_NUMBER (R_IA64_TPREL22, 0x92) /* sym-TP+add, add imm22 ## */
+ RELOC_NUMBER (R_IA64_TPREL64MSB, 0x96) /* sym-TP+add, data8 MSB ## */
+ RELOC_NUMBER (R_IA64_TPREL64LSB, 0x97) /* sym-TP+add, data8 LSB ## */
+
+ RELOC_NUMBER (R_IA64_LTOFF_TP22, 0x9a) /* @ltoff(sym-TP+add), add imm22 ## */
+
+ FAKE_RELOC (R_IA64_MAX_RELOC_CODE, 0x9a)
+END_RELOC_NUMBERS
+
+#endif /* _ELF_IA64_H */
+Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
+ David Mosberger <davidm@hpl.hp.com>
+ Timothy Wall <twall@cygnus.com>
+ Jim Wilson <wilson@cygnus.com>
+
+ * ia64.h: New file.
+
2000-03-27 Nick Clifton <nickc@cygnus.com>
* d30v.h (SHORT_A1): Fix value.
--- /dev/null
+/* ia64.h -- Header file for ia64 opcode table
+ Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+
+ See the file HP-COPYRIGHT for additional information. */
+
+#ifndef opcode_ia64_h
+#define opcode_ia64_h
+
+#include <sys/types.h>
+
+#include <bfd.h>
+
+
+typedef BFD_HOST_U_64_BIT ia64_insn;
+
+enum ia64_insn_type
+ {
+ IA64_TYPE_NIL = 0, /* illegal type */
+ IA64_TYPE_A, /* integer alu (I- or M-unit) */
+ IA64_TYPE_I, /* non-alu integer (I-unit) */
+ IA64_TYPE_M, /* memory (M-unit) */
+ IA64_TYPE_B, /* branch (B-unit) */
+ IA64_TYPE_F, /* floating-point (F-unit) */
+ IA64_TYPE_X, /* long encoding (X-unit) */
+ IA64_TYPE_DYN, /* Dynamic opcode */
+ IA64_NUM_TYPES
+ };
+
+enum ia64_unit
+ {
+ IA64_UNIT_NIL = 0, /* illegal unit */
+ IA64_UNIT_I, /* integer unit */
+ IA64_UNIT_M, /* memory unit */
+ IA64_UNIT_B, /* branching unit */
+ IA64_UNIT_F, /* floating-point unit */
+ IA64_UNIT_L, /* long "unit" */
+ IA64_UNIT_X, /* may be integer or branch unit */
+ IA64_NUM_UNITS
+ };
+
+/* Changes to this enumeration must be propagated to the operand table in
+ bfd/cpu-ia64-opc.c
+ */
+enum ia64_opnd
+ {
+ IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/
+
+ /* constants */
+ IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */
+ IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */
+ IA64_OPND_C1, /* the constant 1 */
+ IA64_OPND_C8, /* the constant 8 */
+ IA64_OPND_C16, /* the constant 16 */
+ IA64_OPND_GR0, /* gr0 */
+ IA64_OPND_IP, /* instruction pointer (ip) */
+ IA64_OPND_PR, /* predicate register (pr) */
+ IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */
+ IA64_OPND_PSR, /* processor status register (psr) */
+ IA64_OPND_PSR_L, /* processor status register L (psr.l) */
+ IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */
+
+ /* register operands: */
+ IA64_OPND_AR3, /* third application register # (bits 20-26) */
+ IA64_OPND_B1, /* branch register # (bits 6-8) */
+ IA64_OPND_B2, /* branch register # (bits 13-15) */
+ IA64_OPND_CR3, /* third control register # (bits 20-26) */
+ IA64_OPND_F1, /* first floating-point register # */
+ IA64_OPND_F2, /* second floating-point register # */
+ IA64_OPND_F3, /* third floating-point register # */
+ IA64_OPND_F4, /* fourth floating-point register # */
+ IA64_OPND_P1, /* first predicate # */
+ IA64_OPND_P2, /* second predicate # */
+ IA64_OPND_R1, /* first register # */
+ IA64_OPND_R2, /* second register # */
+ IA64_OPND_R3, /* third register # */
+ IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */
+
+ /* indirect operands: */
+ IA64_OPND_CPUID_R3, /* cpuid[reg] */
+ IA64_OPND_DBR_R3, /* dbr[reg] */
+ IA64_OPND_DTR_R3, /* dtr[reg] */
+ IA64_OPND_ITR_R3, /* itr[reg] */
+ IA64_OPND_IBR_R3, /* ibr[reg] */
+ IA64_OPND_MR3, /* memory at addr of third register # */
+ IA64_OPND_MSR_R3, /* msr[reg] */
+ IA64_OPND_PKR_R3, /* pkr[reg] */
+ IA64_OPND_PMC_R3, /* pmc[reg] */
+ IA64_OPND_PMD_R3, /* pmd[reg] */
+ IA64_OPND_RR_R3, /* rr[reg] */
+
+ /* immediate operands: */
+ IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */
+ IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */
+ IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */
+ IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
+ IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */
+ IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */
+ IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */
+ IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */
+ IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */
+ IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */
+ IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */
+ IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */
+ IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */
+ IA64_OPND_SOF, /* 8-bit stack frame size */
+ IA64_OPND_SOL, /* 8-bit size of locals */
+ IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */
+ IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */
+ IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
+ IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */
+ IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
+ IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
+ IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */
+ IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */
+ IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */
+ IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
+ IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
+ IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */
+ IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */
+ IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
+ IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */
+ IA64_OPND_IMMU62, /* unsigned 62-bit immediate */
+ IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */
+ IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
+ IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */
+ IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */
+ IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */
+ IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */
+ IA64_OPND_POS6, /* 6-bit count (bits 14-19) */
+ IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
+ IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */
+ IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */
+ IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
+ IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */
+ IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
+
+ IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */
+ };
+
+enum ia64_dependency_mode
+{
+ IA64_DV_RAW,
+ IA64_DV_WAW,
+ IA64_DV_WAR,
+};
+
+enum ia64_dependency_semantics
+{
+ IA64_DVS_NONE,
+ IA64_DVS_IMPLIED,
+ IA64_DVS_IMPLIEDF,
+ IA64_DVS_DATA,
+ IA64_DVS_INSTR,
+ IA64_DVS_SPECIFIC,
+ IA64_DVS_OTHER,
+};
+
+enum ia64_resource_specifier
+{
+ IA64_RS_ANY,
+ IA64_RS_AR_K,
+ IA64_RS_AR_UNAT,
+ IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
+ IA64_RS_ARb, /* 48-63, 112-127 */
+ IA64_RS_BR,
+ IA64_RS_CFM,
+ IA64_RS_CPUID,
+ IA64_RS_CR_IRR,
+ IA64_RS_CR_LRR,
+ IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
+ IA64_RS_DBR,
+ IA64_RS_FR,
+ IA64_RS_FRb,
+ IA64_RS_GR0,
+ IA64_RS_GR,
+ IA64_RS_IBR,
+ IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
+ IA64_RS_MSR,
+ IA64_RS_PKR,
+ IA64_RS_PMC,
+ IA64_RS_PMD,
+ IA64_RS_PR,
+ IA64_RS_PR63,
+ IA64_RS_RR,
+
+ IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
+ IA64_RS_CRX, /* CRs not in RS_CR */
+ IA64_RS_PSR, /* PSR bits */
+ IA64_RS_RSE, /* implementation-specific RSE resources */
+ IA64_RS_AR_FPSR,
+};
+
+enum ia64_rse_resource
+{
+ IA64_RSE_N_STACKED_PHYS,
+ IA64_RSE_BOF,
+ IA64_RSE_STORE_REG,
+ IA64_RSE_LOAD_REG,
+ IA64_RSE_BSPLOAD,
+ IA64_RSE_RNATBITINDEX,
+ IA64_RSE_CFLE,
+ IA64_RSE_NDIRTY,
+};
+
+/* Information about a given resource dependency */
+struct ia64_dependency
+{
+ /* Name of the resource */
+ const char *name;
+ /* Does this dependency need further specification? */
+ enum ia64_resource_specifier specifier;
+ /* Mode of dependency */
+ enum ia64_dependency_mode mode;
+ /* Dependency semantics */
+ enum ia64_dependency_semantics semantics;
+ /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
+#define REG_NONE (-1)
+ int regindex;
+ /* Special info on semantics */
+ const char *info;
+};
+
+/* Two arrays of indexes into the ia64_dependency table.
+ chks are dependencies to check for conflicts when an opcode is
+ encountered; regs are dependencies to register (mark as used) when an
+ opcode is used. chks correspond to readers (RAW) or writers (WAW or
+ WAR) of a resource, while regs correspond to writers (RAW or WAW) and
+ readers (WAR) of a resource. */
+struct ia64_opcode_dependency
+{
+ int nchks;
+ const unsigned short *chks;
+ int nregs;
+ const unsigned short *regs;
+};
+
+/* encode/extract the note/index for a dependency */
+#define RDEP(N,X) (((N)<<11)|(X))
+#define NOTE(X) (((X)>>11)&0x1F)
+#define DEP(X) ((X)&0x7FF)
+
+/* A template descriptor describes the execution units that are active
+ for each of the three slots. It also specifies the location of
+ instruction group boundaries that may be present between two slots. */
+struct ia64_templ_desc
+ {
+ int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
+ enum ia64_unit exec_unit[3];
+ const char *name;
+ };
+
+/* The opcode table is an array of struct ia64_opcode. */
+
+struct ia64_opcode
+ {
+ /* The opcode name. */
+ const char *name;
+
+ /* The type of the instruction: */
+ enum ia64_insn_type type;
+
+ /* Number of output operands: */
+ int num_outputs;
+
+ /* The opcode itself. Those bits which will be filled in with
+ operands are zeroes. */
+ ia64_insn opcode;
+
+ /* The opcode mask. This is used by the disassembler. This is a
+ mask containing ones indicating those bits which must match the
+ opcode field, and zeroes indicating those bits which need not
+ match (and are presumably filled in by operands). */
+ ia64_insn mask;
+
+ /* An array of operand codes. Each code is an index into the
+ operand table. They appear in the order which the operands must
+ appear in assembly code, and are terminated by a zero. */
+ enum ia64_opnd operands[5];
+
+ /* One bit flags for the opcode. These are primarily used to
+ indicate specific processors and environments support the
+ instructions. The defined values are listed below. */
+ unsigned int flags;
+
+ /* Used by ia64_find_next_opcode (). */
+ short ent_index;
+
+ /* Opcode dependencies. */
+ const struct ia64_opcode_dependency *dependencies;
+ };
+
+/* Values defined for the flags field of a struct ia64_opcode. */
+
+#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */
+#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */
+#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */
+#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */
+#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */
+#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */
+#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */
+#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */
+#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */
+#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
+
+/* A macro to extract the major opcode from an instruction. */
+#define IA64_OP(i) (((i) >> 37) & 0xf)
+
+enum ia64_operand_class
+ {
+ IA64_OPND_CLASS_CST, /* constant */
+ IA64_OPND_CLASS_REG, /* register */
+ IA64_OPND_CLASS_IND, /* indirect register */
+ IA64_OPND_CLASS_ABS, /* absolute value */
+ IA64_OPND_CLASS_REL, /* IP-relative value */
+ };
+
+/* The operands table is an array of struct ia64_operand. */
+
+struct ia64_operand
+{
+ enum ia64_operand_class class;
+
+ /* Set VALUE as the operand bits for the operand of type SELF in the
+ instruction pointed to by CODE. If an error occurs, *CODE is not
+ modified and the returned string describes the cause of the
+ error. If no error occurs, NULL is returned. */
+ const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
+ ia64_insn *code);
+
+ /* Extract the operand bits for an operand of type SELF from
+ instruction CODE store them in *VALUE. If an error occurs, the
+ cause of the error is described by the string returned. If no
+ error occurs, NULL is returned. */
+ const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
+ ia64_insn *value);
+
+ /* A string whose meaning depends on the operand class. */
+
+ const char *str;
+
+ struct bit_field
+ {
+ /* The number of bits in the operand. */
+ int bits;
+
+ /* How far the operand is left shifted in the instruction. */
+ int shift;
+ }
+ field[4]; /* no operand has more than this many bit-fields */
+
+ unsigned int flags;
+
+ const char *desc; /* brief description */
+};
+
+/* Values defined for the flags field of a struct ia64_operand. */
+
+/* Disassemble as signed decimal (instead of hex): */
+#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0)
+/* Disassemble as unsigned decimal (instead of hex): */
+#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
+
+extern const struct ia64_templ_desc ia64_templ_desc[16];
+
+/* The tables are sorted by major opcode number and are otherwise in
+ the order in which the disassembler should consider instructions. */
+extern struct ia64_opcode ia64_opcodes_a[];
+extern struct ia64_opcode ia64_opcodes_i[];
+extern struct ia64_opcode ia64_opcodes_m[];
+extern struct ia64_opcode ia64_opcodes_b[];
+extern struct ia64_opcode ia64_opcodes_f[];
+extern struct ia64_opcode ia64_opcodes_d[];
+
+
+extern struct ia64_opcode *ia64_find_opcode (const char *name);
+extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
+
+extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
+ enum ia64_insn_type type);
+
+extern void ia64_free_opcode (struct ia64_opcode *ent);
+extern const struct ia64_dependency *ia64_find_dependency (int index);
+
+/* To avoid circular library dependencies, this array is implemented
+ in bfd/cpu-ia64-opc.c: */
+extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
+
+#endif /* opcode_ia64_h */
+Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
+ David Mosberger <davidm@hpl.hp.com>
+ Timothy Wall <twall@cygnus.com>
+ Bob Manson <manson@charmed.cygnus.com>
+ Jim Wilson <wilson@cygnus.com>
+
+ * Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h.
+ (CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c,
+ ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c,
+ ia64-asmtab.c.
+ (ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo.
+ (ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen,
+ ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules.
+ * Makefile.in: Rebuild.
+ * configure Rebuild.
+ * configure.in (bfd_ia64_arch): New target.
+ * disassemble.c (ARCH_ia64): Define.
+ (disassembler): Support ARCH_ia64.
+ * ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl,
+ ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c,
+ ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
+ ia64-war.tbl, ia64-waw.tbl): New files.
+
2000-04-20 Alexandre Oliva <aoliva@cygnus.com>
* m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
mcore-opc.h \
sh-opc.h \
sysdep.h \
+ ia64-asmtab.h \
+ ia64-opc.h \
w65-opc.h \
z8k-opc.h
i370-opc.c \
i386-dis.c \
i960-dis.c \
+ ia64-dis.c \
+ ia64-opc-a.c \
+ ia64-opc-b.c \
+ ia64-opc-f.c \
+ ia64-opc-i.c \
+ ia64-opc-m.c \
+ ia64-opc-d.c \
+ ia64-opc.c \
+ ia64-gen.c \
+ ia64-asmtab.c \
m32r-asm.c \
m32r-desc.c \
m32r-dis.c \
i370-dis.lo \
i370-opc.lo \
i960-dis.lo \
+ ia64-dis.lo \
+ ia64-opc.lo \
m32r-asm.lo \
m32r-desc.lo \
m32r-dis.lo \
+ia64-ic.tbl: $(srcdir)/ia64-ic.tbl
+ $(LN_S) -f $(srcdir)/ia64-ic.tbl
+ia64-raw.tbl: $(srcdir)/ia64-raw.tbl
+ $(LN_S) -f $(srcdir)/ia64-raw.tbl
+ia64-waw.tbl: $(srcdir)/ia64-waw.tbl
+ $(LN_S) -f $(srcdir)/ia64-waw.tbl
+ia64-war.tbl: $(srcdir)/ia64-war.tbl
+ $(LN_S) -f $(srcdir)/ia64-war.tbl
+
+ia64-gen: ia64-gen.o
+ $(LINK) ia64-gen.o $(LIBIBERTY)
+
+ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \
+ ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h
+
+ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl
+ ./ia64-gen > $(srcdir)/ia64-asmtab.c
# This dependency stuff is copied from BFD.
$(INCDIR)/ansidecl.h sysdep.h config.h opintl.h
i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H)
+ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ia64.h $(BFD_H)
+ia64-opc.lo: $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/libiberty.h \
+ $(INCDIR)/ansidecl.h sysdep.h ia64-asmtab.h ia64-asmtab.c
m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
m32r-opc.h opintl.h
mcore-opc.h \
sh-opc.h \
sysdep.h \
+ ia64-asmtab.h \
+ ia64-opc.h \
w65-opc.h \
z8k-opc.h
i370-opc.c \
i386-dis.c \
i960-dis.c \
+ ia64-dis.c \
+ ia64-opc-a.c \
+ ia64-opc-b.c \
+ ia64-opc-f.c \
+ ia64-opc-i.c \
+ ia64-opc-m.c \
+ ia64-opc-d.c \
+ ia64-opc.c \
+ ia64-gen.c \
+ ia64-asmtab.c \
m32r-asm.c \
m32r-desc.c \
m32r-dis.c \
i370-dis.lo \
i370-opc.lo \
i960-dis.lo \
+ ia64-dis.lo \
+ ia64-opc.lo \
m32r-asm.lo \
m32r-desc.lo \
m32r-dis.lo \
distclean-generic clean-generic maintainer-clean-generic clean \
mostlyclean distclean maintainer-clean
+ia64-ic.tbl: $(srcdir)/ia64-ic.tbl
+ $(LN_S) -f $(srcdir)/ia64-ic.tbl
+ia64-raw.tbl: $(srcdir)/ia64-raw.tbl
+ $(LN_S) -f $(srcdir)/ia64-raw.tbl
+ia64-waw.tbl: $(srcdir)/ia64-waw.tbl
+ $(LN_S) -f $(srcdir)/ia64-waw.tbl
+ia64-war.tbl: $(srcdir)/ia64-war.tbl
+ $(LN_S) -f $(srcdir)/ia64-war.tbl
+
+ia64-gen: ia64-gen.o
+ $(LINK) ia64-gen.o $(LIBIBERTY)
+
+ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \
+ ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h
+
+ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl
+ ./ia64-gen > $(srcdir)/ia64-asmtab.c
disassemble.lo: disassemble.c $(INCDIR)/dis-asm.h
$(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/disassemble.c
$(INCDIR)/ansidecl.h sysdep.h config.h opintl.h
i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H)
+ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ia64.h $(BFD_H)
+ia64-opc.lo: $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/libiberty.h \
+ $(INCDIR)/ansidecl.h sysdep.h ia64-asmtab.h ia64-asmtab.c
m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
m32r-opc.h opintl.h
bfd_i386_arch) ta="$ta i386-dis.lo" ;;
bfd_i860_arch) ;;
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
+ bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;;
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
bfd_i386_arch) ta="$ta i386-dis.lo" ;;
bfd_i860_arch) ;;
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
+ bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;;
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
#define ARCH_i370
#define ARCH_i386
#define ARCH_i960
+#define ARCH_ia64
#define ARCH_fr30
#define ARCH_m32r
#define ARCH_m68k
disassemble = print_insn_i960;
break;
#endif
+#ifdef ARCH_ia64
+ case bfd_arch_ia64:
+ disassemble = print_insn_ia64;
+ break;
+#endif
#ifdef ARCH_fr30
case bfd_arch_fr30:
disassemble = print_insn_fr30;
--- /dev/null
+/* This file is automatically generated by ia64-gen. Do not edit! */
+static const char *ia64_strings[] = {
+ "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and",
+ "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call",
+ "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmpxchg1",
+ "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop", "czx1",
+ "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", "exit",
+ "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", "fandcm",
+ "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", "fetchadd4",
+ "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", "fmerge", "fmin",
+ "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", "fnmpy", "fnorm", "for",
+ "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", "fpcvt", "fpma", "fpmax",
+ "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", "fpnegabs", "fpnma",
+ "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", "fselect", "fsetc",
+ "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", "g", "ga", "ge",
+ "getf", "geu", "gt", "gtu", "h", "hu", "i", "ia", "imp", "invala", "itc",
+ "itr", "l", "ld1", "ld2", "ld4", "ld8", "ldf", "ldf8", "ldfd", "ldfe",
+ "ldfp8", "ldfpd", "ldfps", "ldfs", "le", "leu", "lfetch", "loadrs",
+ "loop", "lr", "lt", "ltu", "lu", "m", "many", "mf", "mix1", "mix2",
+ "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne", "neq", "nge", "ngt",
+ "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1", "nt2", "nta", "nz",
+ "or", "orcm", "ord", "pack2", "pack4", "padd1", "padd2", "padd4", "pavg1",
+ "pavg2", "pavgsub1", "pavgsub2", "pcmp1", "pcmp2", "pcmp4", "pmax1",
+ "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2", "popcnt", "pr", "probe",
+ "psad1", "pshl2", "pshl4", "pshladd2", "pshr2", "pshr4", "pshradd2",
+ "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz", "rel", "ret", "rfi",
+ "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3", "sa", "se", "setf",
+ "shl", "shladd", "shladdp4", "shr", "shrp", "sig", "spill", "spnt",
+ "sptk", "srlz", "ssm", "sss", "st1", "st2", "st4", "st8", "stf", "stf8",
+ "stfd", "stfe", "stfs", "sub", "sum", "sxt1", "sxt2", "sxt4", "sync",
+ "tak", "tbit", "thash", "tnat", "tpa", "trunc", "ttag", "u", "unc",
+ "unord", "unpack1", "unpack2", "unpack4", "uss", "uus", "uuu", "w",
+ "wexit", "wtop", "x", "xchg1", "xchg2", "xchg4", "xchg8", "xf", "xma",
+ "xmpy", "xor", "xuf", "z", "zxt1", "zxt2", "zxt4",
+};
+
+static const struct ia64_dependency
+dependencies[] = {
+ { "ALAT", 0, 0, 0, -1, },
+ { "AR[BSP]", 25, 0, 2, 17, },
+ { "AR[BSPSTORE]", 25, 0, 2, 18, },
+ { "AR[CCV]", 25, 0, 2, 32, },
+ { "AR[EC]", 25, 0, 2, 66, },
+ { "AR[FPSR].sf0.controls", 29, 0, 2, -1, },
+ { "AR[FPSR].sf1.controls", 29, 0, 2, -1, },
+ { "AR[FPSR].sf2.controls", 29, 0, 2, -1, },
+ { "AR[FPSR].sf3.controls", 29, 0, 2, -1, },
+ { "AR[FPSR].sf0.flags", 29, 0, 2, -1, },
+ { "AR[FPSR].sf1.flags", 29, 0, 2, -1, },
+ { "AR[FPSR].sf2.flags", 29, 0, 2, -1, },
+ { "AR[FPSR].sf3.flags", 29, 0, 2, -1, },
+ { "AR[FPSR].traps", 29, 0, 2, -1, },
+ { "AR[FPSR].rv", 29, 0, 2, -1, },
+ { "AR[ITC]", 25, 0, 2, 44, },
+ { "AR[K%], % in 0 - 7", 1, 0, 2, -1, },
+ { "AR[LC]", 25, 0, 2, 65, },
+ { "AR[PFS]", 25, 0, 2, 64, },
+ { "AR[PFS]", 25, 0, 2, 64, },
+ { "AR[PFS]", 25, 0, 0, 64, },
+ { "AR[RNAT]", 25, 0, 2, 19, },
+ { "AR[RSC]", 25, 0, 2, 16, },
+ { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, },
+ { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, },
+ { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, },
+ { "BR%, % in 0 - 7", 5, 0, 2, -1, },
+ { "BR%, % in 0 - 7", 5, 0, 0, -1, },
+ { "BR%, % in 0 - 7", 5, 0, 2, -1, },
+ { "CFM", 6, 0, 2, -1, },
+ { "CFM", 6, 0, 2, -1, },
+ { "CFM", 6, 0, 2, -1, },
+ { "CFM", 6, 0, 2, -1, },
+ { "CFM", 6, 0, 0, -1, },
+ { "CPUID#", 7, 0, 5, -1, },
+ { "CR[CMCV]", 26, 0, 3, 74, },
+ { "CR[DCR]", 26, 0, 3, 0, },
+ { "CR[EOI]", 26, 0, 6, 67, "SC Section 10.8.3.4", },
+ { "CR[GPTA]", 26, 0, 3, 9, },
+ { "CR[IFA]", 26, 0, 1, 20, },
+ { "CR[IFA]", 26, 0, 3, 20, },
+ { "CR[IFS]", 26, 0, 3, 23, },
+ { "CR[IFS]", 26, 0, 1, 23, },
+ { "CR[IFS]", 26, 0, 1, 23, },
+ { "CR[IHA]", 26, 0, 3, 25, },
+ { "CR[IIM]", 26, 0, 3, 24, },
+ { "CR[IIP]", 26, 0, 3, 19, },
+ { "CR[IIP]", 26, 0, 1, 19, },
+ { "CR[IIPA]", 26, 0, 3, 22, },
+ { "CR[IPSR]", 26, 0, 3, 16, },
+ { "CR[IPSR]", 26, 0, 1, 16, },
+ { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, },
+ { "CR[ISR]", 26, 0, 3, 17, },
+ { "CR[ITIR]", 26, 0, 3, 21, },
+ { "CR[ITIR]", 26, 0, 1, 21, },
+ { "CR[ITM]", 26, 0, 3, 1, },
+ { "CR[ITV]", 26, 0, 3, 72, },
+ { "CR[IVA]", 26, 0, 4, 2, },
+ { "CR[IVR]", 26, 0, 6, 65, "SC Section 10.8.3.2", },
+ { "CR[LID]", 26, 0, 6, 64, "SC Section 10.8.3.1", },
+ { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, },
+ { "CR[PMV]", 26, 0, 3, 73, },
+ { "CR[PTA]", 26, 0, 3, 8, },
+ { "CR[TPR]", 26, 0, 3, 66, },
+ { "CR[TPR]", 26, 0, 6, 66, "SC Section 10.8.3.3", },
+ { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, },
+ { "DBR#", 11, 0, 2, -1, },
+ { "DBR#", 11, 0, 3, -1, },
+ { "DTC", 0, 0, 3, -1, },
+ { "DTC", 0, 0, 2, -1, },
+ { "DTC", 0, 0, 0, -1, },
+ { "DTC", 0, 0, 2, -1, },
+ { "DTC_LIMIT*", 0, 0, 2, -1, },
+ { "DTR", 0, 0, 3, -1, },
+ { "DTR", 0, 0, 2, -1, },
+ { "DTR", 0, 0, 3, -1, },
+ { "DTR", 0, 0, 0, -1, },
+ { "DTR", 0, 0, 2, -1, },
+ { "FR%, % in 0 - 1", 12, 0, 0, -1, },
+ { "FR%, % in 2 - 127", 13, 0, 2, -1, },
+ { "FR%, % in 2 - 127", 13, 0, 0, -1, },
+ { "GR0", 14, 0, 0, -1, },
+ { "GR%, % in 1 - 127", 15, 0, 0, -1, },
+ { "GR%, % in 1 - 127", 15, 0, 2, -1, },
+ { "IBR#", 16, 0, 2, -1, },
+ { "InService*", 17, 0, 3, -1, },
+ { "InService*", 17, 0, 2, -1, },
+ { "InService*", 17, 0, 2, -1, },
+ { "IP", 0, 0, 0, -1, },
+ { "ITC", 0, 0, 4, -1, },
+ { "ITC", 0, 0, 2, -1, },
+ { "ITC", 0, 0, 0, -1, },
+ { "ITC", 0, 0, 4, -1, },
+ { "ITC", 0, 0, 2, -1, },
+ { "ITC_LIMIT*", 0, 0, 2, -1, },
+ { "ITR", 0, 0, 2, -1, },
+ { "ITR", 0, 0, 4, -1, },
+ { "ITR", 0, 0, 2, -1, },
+ { "ITR", 0, 0, 0, -1, },
+ { "ITR", 0, 0, 4, -1, },
+ { "memory", 0, 0, 0, -1, },
+ { "MSR#", 18, 0, 5, -1, },
+ { "PKR#", 19, 0, 3, -1, },
+ { "PKR#", 19, 0, 0, -1, },
+ { "PKR#", 19, 0, 2, -1, },
+ { "PKR#", 19, 0, 2, -1, },
+ { "PMC#", 20, 0, 2, -1, },
+ { "PMC#", 20, 0, 6, -1, "SC+3 Section 12.1.1", },
+ { "PMD#", 21, 0, 2, -1, },
+ { "PR0", 0, 0, 0, -1, },
+ { "PR%, % in 1 - 62", 22, 0, 2, -1, },
+ { "PR%, % in 1 - 62", 22, 0, 2, -1, },
+ { "PR%, % in 1 - 62", 22, 0, 0, -1, },
+ { "PR63", 23, 0, 2, -1, },
+ { "PR63", 23, 0, 2, -1, },
+ { "PR63", 23, 0, 0, -1, },
+ { "PSR.ac", 27, 0, 1, 3, },
+ { "PSR.ac", 27, 0, 3, 3, },
+ { "PSR.ac", 27, 0, 2, 3, },
+ { "PSR.be", 27, 0, 1, 1, },
+ { "PSR.be", 27, 0, 3, 1, },
+ { "PSR.be", 27, 0, 2, 1, },
+ { "PSR.bn", 27, 0, 2, 44, },
+ { "PSR.cpl", 27, 0, 1, 32, },
+ { "PSR.da", 27, 0, 3, 38, },
+ { "PSR.db", 27, 0, 3, 24, },
+ { "PSR.db", 27, 0, 2, 24, },
+ { "PSR.db", 27, 0, 3, 24, },
+ { "PSR.dd", 27, 0, 3, 39, },
+ { "PSR.dfh", 27, 0, 3, 19, },
+ { "PSR.dfh", 27, 0, 2, 19, },
+ { "PSR.dfl", 27, 0, 3, 18, },
+ { "PSR.dfl", 27, 0, 2, 18, },
+ { "PSR.di", 27, 0, 3, 22, },
+ { "PSR.di", 27, 0, 2, 22, },
+ { "PSR.dt", 27, 0, 3, 17, },
+ { "PSR.dt", 27, 0, 2, 17, },
+ { "PSR.ed", 27, 0, 3, 43, },
+ { "PSR.i", 27, 0, 2, 14, },
+ { "PSR.i", 27, 0, 3, 14, },
+ { "PSR.ia", 27, 0, 0, 14, },
+ { "PSR.ic", 27, 0, 2, 13, },
+ { "PSR.ic", 27, 0, 3, 13, },
+ { "PSR.id", 27, 0, 0, 14, },
+ { "PSR.is", 27, 0, 0, 14, },
+ { "PSR.it", 27, 0, 3, 14, },
+ { "PSR.lp", 27, 0, 2, 25, },
+ { "PSR.lp", 27, 0, 3, 25, },
+ { "PSR.lp", 27, 0, 3, 25, },
+ { "PSR.mc", 27, 0, 0, 35, },
+ { "PSR.mfh", 27, 0, 2, 5, },
+ { "PSR.mfl", 27, 0, 2, 4, },
+ { "PSR.pk", 27, 0, 3, 15, },
+ { "PSR.pk", 27, 0, 2, 15, },
+ { "PSR.pp", 27, 0, 2, 21, },
+ { "PSR.ri", 27, 0, 0, 41, },
+ { "PSR.rt", 27, 0, 2, 27, },
+ { "PSR.rt", 27, 0, 3, 27, },
+ { "PSR.rt", 27, 0, 3, 27, },
+ { "PSR.si", 27, 0, 2, 23, },
+ { "PSR.si", 27, 0, 3, 23, },
+ { "PSR.sp", 27, 0, 2, 20, },
+ { "PSR.sp", 27, 0, 3, 20, },
+ { "PSR.ss", 27, 0, 3, 40, },
+ { "PSR.tb", 27, 0, 3, 26, },
+ { "PSR.tb", 27, 0, 2, 26, },
+ { "PSR.up", 27, 0, 2, 2, },
+ { "RR#", 24, 0, 3, -1, },
+ { "RR#", 24, 0, 2, -1, },
+ { "RSE", 28, 0, 2, -1, },
+ { "ALAT", 0, 1, 0, -1, },
+ { "AR[BSP]", 25, 1, 2, 17, },
+ { "AR[BSPSTORE]", 25, 1, 2, 18, },
+ { "AR[CCV]", 25, 1, 2, 32, },
+ { "AR[EC]", 25, 1, 2, 66, },
+ { "AR[FPSR].sf0.controls", 29, 1, 2, -1, },
+ { "AR[FPSR].sf1.controls", 29, 1, 2, -1, },
+ { "AR[FPSR].sf2.controls", 29, 1, 2, -1, },
+ { "AR[FPSR].sf3.controls", 29, 1, 2, -1, },
+ { "AR[FPSR].sf0.flags", 29, 1, 0, -1, },
+ { "AR[FPSR].sf0.flags", 29, 1, 2, -1, },
+ { "AR[FPSR].sf0.flags", 29, 1, 2, -1, },
+ { "AR[FPSR].sf1.flags", 29, 1, 0, -1, },
+ { "AR[FPSR].sf1.flags", 29, 1, 2, -1, },
+ { "AR[FPSR].sf1.flags", 29, 1, 2, -1, },
+ { "AR[FPSR].sf2.flags", 29, 1, 0, -1, },
+ { "AR[FPSR].sf2.flags", 29, 1, 2, -1, },
+ { "AR[FPSR].sf2.flags", 29, 1, 2, -1, },
+ { "AR[FPSR].sf3.flags", 29, 1, 0, -1, },
+ { "AR[FPSR].sf3.flags", 29, 1, 2, -1, },
+ { "AR[FPSR].sf3.flags", 29, 1, 2, -1, },
+ { "AR[FPSR].rv", 29, 1, 2, -1, },
+ { "AR[FPSR].traps", 29, 1, 2, -1, },
+ { "AR[ITC]", 25, 1, 2, 44, },
+ { "AR[K%], % in 0 - 7", 1, 1, 2, -1, },
+ { "AR[LC]", 25, 1, 2, 65, },
+ { "AR[PFS]", 25, 1, 0, 64, },
+ { "AR[PFS]", 25, 1, 2, 64, },
+ { "AR[PFS]", 25, 1, 2, 64, },
+ { "AR[RNAT]", 25, 1, 2, 19, },
+ { "AR[RSC]", 25, 1, 2, 16, },
+ { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, },
+ { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, },
+ { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, },
+ { "BR%, % in 0 - 7", 5, 1, 2, -1, },
+ { "BR%, % in 0 - 7", 5, 1, 2, -1, },
+ { "BR%, % in 0 - 7", 5, 1, 2, -1, },
+ { "BR%, % in 0 - 7", 5, 1, 0, -1, },
+ { "CFM", 6, 1, 2, -1, },
+ { "CPUID#", 7, 1, 0, -1, },
+ { "CR[CMCV]", 26, 1, 2, 74, },
+ { "CR[DCR]", 26, 1, 2, 0, },
+ { "CR[EOI]", 26, 1, 6, 67, "SC Section 10.8.3.4", },
+ { "CR[GPTA]", 26, 1, 2, 9, },
+ { "CR[IFA]", 26, 1, 2, 20, },
+ { "CR[IFS]", 26, 1, 2, 23, },
+ { "CR[IHA]", 26, 1, 2, 25, },
+ { "CR[IIM]", 26, 1, 2, 24, },
+ { "CR[IIP]", 26, 1, 2, 19, },
+ { "CR[IIPA]", 26, 1, 2, 22, },
+ { "CR[IPSR]", 26, 1, 2, 16, },
+ { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, },
+ { "CR[ISR]", 26, 1, 2, 17, },
+ { "CR[ITIR]", 26, 1, 2, 21, },
+ { "CR[ITM]", 26, 1, 2, 1, },
+ { "CR[ITV]", 26, 1, 2, 72, },
+ { "CR[IVA]", 26, 1, 2, 2, },
+ { "CR[IVR]", 26, 1, 6, 65, "SC", },
+ { "CR[LID]", 26, 1, 6, 64, "SC", },
+ { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, },
+ { "CR[PMV]", 26, 1, 2, 73, },
+ { "CR[PTA]", 26, 1, 2, 8, },
+ { "CR[TPR]", 26, 1, 2, 66, },
+ { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, },
+ { "DBR#", 11, 1, 2, -1, },
+ { "DTC", 0, 1, 0, -1, },
+ { "DTC", 0, 1, 2, -1, },
+ { "DTC", 0, 1, 2, -1, },
+ { "DTC_LIMIT*", 0, 1, 2, -1, },
+ { "DTR", 0, 1, 2, -1, },
+ { "DTR", 0, 1, 2, -1, },
+ { "DTR", 0, 1, 2, -1, },
+ { "DTR", 0, 1, 0, -1, },
+ { "FR%, % in 0 - 1", 12, 1, 0, -1, },
+ { "FR%, % in 2 - 127", 13, 1, 2, -1, },
+ { "GR0", 14, 1, 0, -1, },
+ { "GR%, % in 1 - 127", 15, 1, 2, -1, },
+ { "IBR#", 16, 1, 2, -1, },
+ { "InService*", 17, 1, 6, -1, "SC", },
+ { "IP", 0, 1, 0, -1, },
+ { "ITC", 0, 1, 0, -1, },
+ { "ITC", 0, 1, 2, -1, },
+ { "ITC", 0, 1, 2, -1, },
+ { "ITR", 0, 1, 2, -1, },
+ { "ITR", 0, 1, 2, -1, },
+ { "ITR", 0, 1, 0, -1, },
+ { "memory", 0, 1, 0, -1, },
+ { "MSR#", 18, 1, 6, -1, "SC", },
+ { "PKR#", 19, 1, 0, -1, },
+ { "PKR#", 19, 1, 0, -1, },
+ { "PKR#", 19, 1, 2, -1, },
+ { "PMC#", 20, 1, 2, -1, },
+ { "PMD#", 21, 1, 2, -1, },
+ { "PR0", 0, 1, 0, -1, },
+ { "PR%, % in 1 - 62", 22, 1, 0, -1, },
+ { "PR%, % in 1 - 62", 22, 1, 0, -1, },
+ { "PR%, % in 1 - 62", 22, 1, 2, -1, },
+ { "PR%, % in 1 - 62", 22, 1, 2, -1, },
+ { "PR63", 23, 1, 0, -1, },
+ { "PR63", 23, 1, 0, -1, },
+ { "PR63", 23, 1, 2, -1, },
+ { "PR63", 23, 1, 2, -1, },
+ { "PSR.ac", 27, 1, 2, 3, },
+ { "PSR.be", 27, 1, 2, 1, },
+ { "PSR.bn", 27, 1, 2, 44, },
+ { "PSR.cpl", 27, 1, 2, 32, },
+ { "PSR.da", 27, 1, 2, 38, },
+ { "PSR.db", 27, 1, 2, 24, },
+ { "PSR.dd", 27, 1, 2, 39, },
+ { "PSR.dfh", 27, 1, 2, 19, },
+ { "PSR.dfl", 27, 1, 2, 18, },
+ { "PSR.di", 27, 1, 2, 22, },
+ { "PSR.dt", 27, 1, 2, 17, },
+ { "PSR.ed", 27, 1, 2, 43, },
+ { "PSR.i", 27, 1, 2, 14, },
+ { "PSR.ia", 27, 1, 2, 14, },
+ { "PSR.ic", 27, 1, 2, 13, },
+ { "PSR.id", 27, 1, 2, 14, },
+ { "PSR.is", 27, 1, 2, 14, },
+ { "PSR.it", 27, 1, 2, 14, },
+ { "PSR.lp", 27, 1, 2, 25, },
+ { "PSR.mc", 27, 1, 2, 35, },
+ { "PSR.mfh", 27, 1, 0, 5, },
+ { "PSR.mfh", 27, 1, 2, 5, },
+ { "PSR.mfh", 27, 1, 2, 5, },
+ { "PSR.mfl", 27, 1, 0, 4, },
+ { "PSR.mfl", 27, 1, 2, 4, },
+ { "PSR.mfl", 27, 1, 2, 4, },
+ { "PSR.pk", 27, 1, 2, 15, },
+ { "PSR.pp", 27, 1, 2, 21, },
+ { "PSR.ri", 27, 1, 2, 41, },
+ { "PSR.rt", 27, 1, 2, 27, },
+ { "PSR.si", 27, 1, 2, 23, },
+ { "PSR.sp", 27, 1, 2, 20, },
+ { "PSR.ss", 27, 1, 2, 40, },
+ { "PSR.tb", 27, 1, 2, 26, },
+ { "PSR.up", 27, 1, 2, 2, },
+ { "RR#", 24, 1, 2, -1, },
+ { "RSE", 28, 1, 2, -1, },
+ { "PR63", 23, 2, 2, -1, },
+};
+
+static const short dep0[] = {
+ 88, 249, 2131, 2294,
+};
+
+static const short dep1[] = {
+ 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 20602,
+
+};
+
+static const short dep2[] = {
+ 2131, 2294,
+};
+
+static const short dep3[] = {
+ 32, 33, 2129, 2130, 2131, 2294, 4127, 20602,
+};
+
+static const short dep4[] = {
+ 32, 33, 81, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127,
+ 20602,
+};
+
+static const short dep5[] = {
+ 88, 249, 2157, 2158, 2160, 2161, 2163, 2311, 2314, 2315, 2318, 2319,
+};
+
+static const short dep6[] = {
+ 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2311, 2314, 2315,
+ 2318, 2319, 4127, 20602,
+};
+
+static const short dep7[] = {
+ 88, 249, 22637, 22638, 22640, 22641, 22643, 22791, 22794, 22795, 22798, 22799,
+
+};
+
+static const short dep8[] = {
+ 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 22791,
+ 22794, 22795, 22798, 22799,
+};
+
+static const short dep9[] = {
+ 88, 249, 2312, 2314, 2316, 2318,
+};
+
+static const short dep10[] = {
+ 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2312, 2315, 2316,
+ 2319, 4127, 20602,
+};
+
+static const short dep11[] = {
+ 88, 249, 2313, 2315, 2317, 2319,
+};
+
+static const short dep12[] = {
+ 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2313, 2314, 2317,
+ 2318, 4127, 20602,
+};
+
+static const short dep13[] = {
+ 88, 249, 2312, 2313, 2314, 2315, 2316, 2317, 2318, 2319,
+};
+
+static const short dep14[] = {
+ 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2312, 2313, 2314,
+ 2315, 2316, 2317, 2318, 2319, 4127, 20602,
+};
+
+static const short dep15[] = {
+ 88, 249, 2357,
+};
+
+static const short dep16[] = {
+ 32, 33, 88, 145, 163, 164, 249, 2074, 2075, 2157, 2159, 2160, 2162, 2163,
+ 4127,
+};
+
+static const short dep17[] = {
+ 88, 144, 249, 288, 2357, 28841, 28980,
+};
+
+static const short dep18[] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22,
+ 23, 24, 25, 32, 33, 88, 133, 145, 163, 164, 249, 288, 2074, 2075, 2157, 2159,
+ 2160, 2162, 2163, 4127, 28841, 28980,
+};
+
+static const short dep19[] = {
+ 1, 4, 32, 88, 123, 171, 174, 208, 249, 275, 2357, 28841, 28980,
+};
+
+static const short dep20[] = {
+ 1, 18, 20, 30, 32, 33, 88, 145, 147, 148, 163, 164, 171, 174, 208, 249, 275,
+ 2074, 2075, 2157, 2159, 2160, 2162, 2163, 4127, 28841, 28980,
+};
+
+static const short dep21[] = {
+ 1, 32, 43, 88, 171, 208, 215, 249, 28841, 28980,
+};
+
+static const short dep22[] = {
+ 1, 30, 32, 33, 88, 142, 163, 171, 208, 215, 249, 4127, 28841, 28980,
+};
+
+static const short dep23[] = {
+ 32, 88, 208, 249,
+};
+
+static const short dep24[] = {
+ 88, 163, 208, 249,
+};
+
+static const short dep25[] = {
+ 1, 32, 88, 117, 118, 120, 121, 122, 123, 124, 127, 128, 129, 130, 131, 132,
+ 133, 134, 135, 136, 137, 139, 140, 141, 142, 143, 144, 145, 148, 149, 150,
+ 151, 152, 153, 154, 155, 158, 159, 160, 161, 162, 163, 164, 165, 166, 171,
+ 208, 249, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284,
+ 285, 286, 287, 288, 289, 290, 291, 293, 294, 296, 297, 298, 299, 300, 301,
+ 302, 303, 304, 305, 306, 28841, 28980,
+};
+
+static const short dep26[] = {
+ 1, 30, 32, 33, 42, 43, 47, 50, 64, 88, 123, 163, 171, 208, 249, 272, 273,
+ 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288,
+ 289, 290, 291, 293, 294, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305,
+ 306, 4127, 28841, 28980,
+};
+
+static const short dep27[] = {
+ 88, 122, 249, 274,
+};
+
+static const short dep28[] = {
+ 88, 123, 163, 249, 274,
+};
+
+static const short dep29[] = {
+ 88, 123, 249, 275,
+};
+
+static const short dep30[] = {
+ 18, 19, 88, 89, 92, 96, 99, 123, 145, 163, 249, 275,
+};
+
+static const short dep31[] = {
+ 32, 33, 88, 163, 249, 2157, 2159, 2160, 2162, 2163, 4127,
+};
+
+static const short dep32[] = {
+ 1, 18, 32, 88, 171, 196, 197, 208, 249, 2074, 2252, 2255, 2357, 28841, 28980,
+
+};
+
+static const short dep33[] = {
+ 1, 4, 30, 32, 33, 88, 123, 145, 163, 164, 171, 196, 198, 208, 249, 2074, 2075,
+ 2157, 2159, 2160, 2162, 2163, 2253, 2255, 4127, 28841, 28980,
+};
+
+static const short dep34[] = {
+ 88, 249,
+};
+
+static const short dep35[] = {
+ 88, 163, 249, 2074, 2076,
+};
+
+static const short dep36[] = {
+ 32, 33, 88, 145, 163, 164, 249, 2157, 2159, 2160, 2162, 2163, 4127,
+};
+
+static const short dep37[] = {
+ 4, 29, 30, 31, 88, 113, 114, 174, 208, 249, 270, 271, 2357,
+};
+
+static const short dep38[] = {
+ 4, 29, 32, 33, 88, 145, 163, 164, 174, 208, 249, 270, 271, 309, 2157, 2159,
+ 2160, 2162, 2163, 4127,
+};
+
+static const short dep39[] = {
+ 17, 88, 195, 249, 2357,
+};
+
+static const short dep40[] = {
+ 17, 32, 33, 88, 145, 163, 164, 195, 249, 2157, 2159, 2160, 2162, 2163, 4127,
+
+};
+
+static const short dep41[] = {
+ 4, 17, 29, 30, 31, 88, 113, 114, 174, 195, 208, 249, 270, 271, 2357,
+};
+
+static const short dep42[] = {
+ 4, 17, 29, 32, 33, 88, 145, 163, 164, 174, 195, 208, 249, 270, 271, 309, 2157,
+ 2159, 2160, 2162, 2163, 4127,
+};
+
+static const short dep43[] = {
+ 1, 4, 30, 32, 33, 88, 123, 145, 163, 164, 171, 196, 198, 208, 249, 2157, 2159,
+ 2160, 2162, 2163, 2253, 2255, 4127, 28841, 28980,
+};
+
+static const short dep44[] = {
+ 88, 163, 249,
+};
+
+static const short dep45[] = {
+ 9, 88, 179, 180, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728,
+ 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799,
+};
+
+static const short dep46[] = {
+ 5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 22791, 22794, 22795,
+ 22798, 22799,
+};
+
+static const short dep47[] = {
+ 9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 2127, 2292,
+ 18582, 18583, 18724, 18725, 18727, 18728, 22637, 22638, 22639, 22641, 22642,
+ 22791, 22794, 22795, 22798, 22799,
+};
+
+static const short dep48[] = {
+ 5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190,
+ 249, 2126, 2127, 2128, 2157, 2158, 2161, 2292, 4127, 16513, 16515, 18724,
+ 18726, 18727, 18729, 22791, 22794, 22795, 22798, 22799,
+};
+
+static const short dep49[] = {
+ 10, 88, 182, 183, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728,
+ 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799,
+};
+
+static const short dep50[] = {
+ 6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 22791, 22794, 22795,
+ 22798, 22799,
+};
+
+static const short dep51[] = {
+ 11, 88, 185, 186, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728,
+ 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799,
+};
+
+static const short dep52[] = {
+ 7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 22791, 22794, 22795,
+ 22798, 22799,
+};
+
+static const short dep53[] = {
+ 12, 88, 188, 189, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728,
+ 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799,
+};
+
+static const short dep54[] = {
+ 8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 22791, 22794, 22795,
+ 22798, 22799,
+};
+
+static const short dep55[] = {
+ 9, 88, 179, 180, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728,
+
+};
+
+static const short dep56[] = {
+ 5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729,
+};
+
+static const short dep57[] = {
+ 9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 2127, 2292,
+ 18582, 18583, 18724, 18725, 18727, 18728,
+};
+
+static const short dep58[] = {
+ 5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190,
+ 249, 2126, 2127, 2128, 2157, 2158, 2161, 2292, 4127, 16513, 16515, 18724,
+ 18726, 18727, 18729,
+};
+
+static const short dep59[] = {
+ 10, 88, 182, 183, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728,
+
+};
+
+static const short dep60[] = {
+ 6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729,
+};
+
+static const short dep61[] = {
+ 11, 88, 185, 186, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728,
+
+};
+
+static const short dep62[] = {
+ 7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729,
+};
+
+static const short dep63[] = {
+ 12, 88, 188, 189, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728,
+
+};
+
+static const short dep64[] = {
+ 8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729,
+};
+
+static const short dep65[] = {
+ 88, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728,
+};
+
+static const short dep66[] = {
+ 32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 2292, 4127, 16513,
+ 16515, 18724, 18726, 18727, 18729,
+};
+
+static const short dep67[] = {
+ 5, 88, 175, 249,
+};
+
+static const short dep68[] = {
+ 5, 32, 33, 88, 163, 175, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep69[] = {
+ 5, 32, 33, 88, 163, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep70[] = {
+ 6, 88, 176, 249,
+};
+
+static const short dep71[] = {
+ 5, 32, 33, 88, 163, 176, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep72[] = {
+ 7, 88, 177, 249,
+};
+
+static const short dep73[] = {
+ 5, 32, 33, 88, 163, 177, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep74[] = {
+ 8, 88, 178, 249,
+};
+
+static const short dep75[] = {
+ 5, 32, 33, 88, 163, 178, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep76[] = {
+ 9, 88, 180, 181, 249,
+};
+
+static const short dep77[] = {
+ 32, 33, 88, 163, 180, 181, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep78[] = {
+ 32, 33, 88, 163, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep79[] = {
+ 10, 88, 183, 184, 249,
+};
+
+static const short dep80[] = {
+ 32, 33, 88, 163, 183, 184, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep81[] = {
+ 11, 88, 186, 187, 249,
+};
+
+static const short dep82[] = {
+ 32, 33, 88, 163, 186, 187, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep83[] = {
+ 12, 88, 189, 190, 249,
+};
+
+static const short dep84[] = {
+ 32, 33, 88, 163, 189, 190, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep85[] = {
+ 9, 13, 14, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep86[] = {
+ 9, 10, 13, 14, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep87[] = {
+ 9, 11, 13, 14, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep88[] = {
+ 9, 12, 13, 14, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep89[] = {
+ 9, 88, 179, 180, 249,
+};
+
+static const short dep90[] = {
+ 5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep91[] = {
+ 9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249,
+};
+
+static const short dep92[] = {
+ 5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190,
+ 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep93[] = {
+ 10, 88, 182, 183, 249,
+};
+
+static const short dep94[] = {
+ 6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep95[] = {
+ 11, 88, 185, 186, 249,
+};
+
+static const short dep96[] = {
+ 7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep97[] = {
+ 12, 88, 188, 189, 249,
+};
+
+static const short dep98[] = {
+ 8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep99[] = {
+ 9, 88, 179, 180, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318,
+ 2319,
+};
+
+static const short dep100[] = {
+ 5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 2311, 2314, 2315, 2318, 2319, 4127, 16513, 16515,
+};
+
+static const short dep101[] = {
+ 9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 2157, 2158,
+ 2159, 2161, 2162, 2311, 2314, 2315, 2318, 2319,
+};
+
+static const short dep102[] = {
+ 5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190,
+ 249, 2126, 2127, 2128, 2157, 2158, 2161, 2311, 2314, 2315, 2318, 2319, 4127,
+ 16513, 16515,
+};
+
+static const short dep103[] = {
+ 10, 88, 182, 183, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318,
+ 2319,
+};
+
+static const short dep104[] = {
+ 6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 2311, 2314, 2315, 2318, 2319, 4127, 16513, 16515,
+};
+
+static const short dep105[] = {
+ 11, 88, 185, 186, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318,
+ 2319,
+};
+
+static const short dep106[] = {
+ 7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 2311, 2314, 2315, 2318, 2319, 4127, 16513, 16515,
+};
+
+static const short dep107[] = {
+ 12, 88, 188, 189, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318,
+ 2319,
+};
+
+static const short dep108[] = {
+ 8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 2311, 2314, 2315, 2318, 2319, 4127, 16513, 16515,
+};
+
+static const short dep109[] = {
+ 9, 88, 179, 180, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795,
+ 22798, 22799,
+};
+
+static const short dep110[] = {
+ 5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 4127, 16513, 16515, 22791, 22794, 22795, 22798, 22799,
+};
+
+static const short dep111[] = {
+ 9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 22637, 22638,
+ 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799,
+};
+
+static const short dep112[] = {
+ 5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190,
+ 249, 2126, 2127, 2128, 2157, 2158, 2161, 4127, 16513, 16515, 22791, 22794,
+ 22795, 22798, 22799,
+};
+
+static const short dep113[] = {
+ 10, 88, 182, 183, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795,
+ 22798, 22799,
+};
+
+static const short dep114[] = {
+ 6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 4127, 16513, 16515, 22791, 22794, 22795, 22798, 22799,
+};
+
+static const short dep115[] = {
+ 11, 88, 185, 186, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795,
+ 22798, 22799,
+};
+
+static const short dep116[] = {
+ 7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 4127, 16513, 16515, 22791, 22794, 22795, 22798, 22799,
+};
+
+static const short dep117[] = {
+ 12, 88, 188, 189, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795,
+ 22798, 22799,
+};
+
+static const short dep118[] = {
+ 8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2126, 2127, 2128, 2157, 2158, 2161,
+ 4127, 16513, 16515, 22791, 22794, 22795, 22798, 22799,
+};
+
+static const short dep119[] = {
+ 88, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318, 2319,
+};
+
+static const short dep120[] = {
+ 32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 2311, 2314, 2315,
+ 2318, 2319, 4127, 16513, 16515,
+};
+
+static const short dep121[] = {
+ 88, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799,
+
+};
+
+static const short dep122[] = {
+ 32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 4127, 16513, 16515,
+ 22791, 22794, 22795, 22798, 22799,
+};
+
+static const short dep123[] = {
+ 13, 14, 32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 2292, 4127,
+ 16513, 16515, 18724, 18726, 18727, 18729,
+};
+
+static const short dep124[] = {
+ 32, 33, 88, 145, 163, 164, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127,
+ 20602,
+};
+
+static const short dep125[] = {
+ 88, 249, 2075, 2076, 2253, 2254,
+};
+
+static const short dep126[] = {
+ 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2252, 2254, 4127,
+ 20602,
+};
+
+static const short dep127[] = {
+ 32, 33, 88, 163, 249, 2074, 2076, 2157, 2158, 2161, 2294, 4127, 20602,
+};
+
+static const short dep128[] = {
+ 88, 249, 14446, 14448, 14449, 14451, 14602, 14603, 14606, 14607,
+};
+
+static const short dep129[] = {
+ 32, 33, 88, 163, 249, 2129, 2130, 2131, 4127, 14602, 14603, 14606, 14607,
+ 20602, 24685, 24686, 24689,
+};
+
+static const short dep130[] = {
+ 88, 110, 112, 113, 115, 249, 14602, 14603, 14606, 14607,
+};
+
+static const short dep131[] = {
+ 32, 33, 88, 163, 249, 4127, 14602, 14603, 14606, 14607, 24685, 24686, 24689,
+
+};
+
+static const short dep132[] = {
+ 32, 33, 88, 163, 249, 2157, 2158, 2161, 2294, 4127, 20602,
+};
+
+static const short dep133[] = {
+ 32, 33, 88, 110, 113, 163, 249, 2294, 4127, 20602, 24685,
+};
+
+static const short dep134[] = {
+ 4, 17, 19, 20, 88, 174, 195, 198, 249, 2073, 2251,
+};
+
+static const short dep135[] = {
+ 32, 33, 88, 163, 174, 195, 197, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2251,
+ 4127, 20602,
+};
+
+static const short dep136[] = {
+ 4, 17, 18, 19, 32, 33, 88, 163, 249, 2073, 2157, 2158, 2161, 2294, 4127, 20602,
+
+};
+
+static const short dep137[] = {
+ 0, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep138[] = {
+ 0, 88, 170, 249,
+};
+
+static const short dep139[] = {
+ 0, 32, 33, 88, 145, 163, 164, 170, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep140[] = {
+ 32, 33, 88, 163, 170, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep141[] = {
+ 2, 21, 88, 172, 199, 249, 28841, 28980,
+};
+
+static const short dep142[] = {
+ 1, 2, 21, 22, 88, 157, 158, 163, 172, 199, 249, 28841, 28980,
+};
+
+static const short dep143[] = {
+ 1, 21, 22, 30, 32, 33, 88, 157, 158, 163, 172, 199, 249, 4127, 28841, 28980,
+
+};
+
+static const short dep144[] = {
+ 0, 32, 33, 88, 163, 170, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep145[] = {
+ 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 22, 23, 88, 171, 172,
+ 173, 175, 176, 177, 178, 180, 181, 183, 184, 186, 187, 189, 190, 191, 192,
+ 193, 199, 200, 201, 249, 2064, 2073, 2242, 2251, 28841, 28980,
+};
+
+static const short dep146[] = {
+ 22, 32, 33, 88, 123, 163, 171, 172, 173, 175, 176, 177, 178, 180, 181, 183,
+ 184, 186, 187, 189, 190, 191, 192, 193, 199, 200, 201, 249, 2129, 2130, 2131,
+ 2157, 2158, 2161, 2242, 2251, 4127, 20602, 28841, 28980,
+};
+
+static const short dep147[] = {
+ 88, 249, 14452, 14454, 14455, 14457, 14486, 14487, 14502, 14608, 14609, 14629,
+ 14630, 14632, 14633, 14642,
+};
+
+static const short dep148[] = {
+ 32, 33, 88, 162, 163, 249, 2157, 2158, 2161, 4127, 14608, 14609, 14629, 14630,
+ 14632, 14633, 14642,
+};
+
+static const short dep149[] = {
+ 14452, 14454, 14455, 14457, 14486, 14487, 14502, 14608, 14609, 14629, 14630,
+ 14632, 14633, 14642,
+};
+
+static const short dep150[] = {
+ 162, 14608, 14609, 14629, 14630, 14632, 14633, 14642,
+};
+
+static const short dep151[] = {
+ 88, 249, 14453, 14454, 14456, 14457, 14465, 14466, 14467, 14468, 14469, 14470,
+ 14471, 14472, 14474, 14477, 14478, 14486, 14487, 14488, 14489, 14490, 14495,
+ 14496, 14497, 14498, 14502, 14608, 14609, 14615, 14616, 14617, 14618, 14620,
+ 14622, 14629, 14630, 14632, 14633, 14634, 14635, 14638, 14639, 14642,
+};
+
+static const short dep152[] = {
+ 32, 33, 64, 88, 123, 163, 249, 2157, 2158, 2161, 4127, 14608, 14609, 14615,
+ 14616, 14617, 14618, 14620, 14622, 14629, 14630, 14632, 14633, 14634, 14635,
+ 14638, 14639, 14642,
+};
+
+static const short dep153[] = {
+ 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 22, 23, 32, 33, 88, 123,
+ 160, 163, 249, 2064, 2073, 2157, 2158, 2161, 2294, 4127, 20602, 28841,
+};
+
+static const short dep154[] = {
+ 35, 36, 37, 38, 39, 40, 41, 42, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55,
+ 56, 57, 59, 61, 62, 63, 64, 85, 87, 88, 210, 211, 212, 213, 214, 215, 216,
+ 217, 218, 219, 220, 222, 223, 224, 225, 226, 228, 230, 231, 232, 248, 249,
+ 2108, 2277,
+};
+
+static const short dep155[] = {
+ 32, 33, 87, 88, 123, 142, 163, 210, 211, 212, 213, 214, 215, 216, 217, 218,
+ 219, 220, 222, 223, 224, 225, 226, 228, 230, 231, 232, 248, 249, 2129, 2130,
+ 2131, 2157, 2158, 2161, 2277, 4127, 20602,
+};
+
+static const short dep156[] = {
+ 51, 86, 88, 221, 248, 249, 2131, 2294,
+};
+
+static const short dep157[] = {
+ 32, 33, 35, 36, 38, 40, 41, 43, 44, 45, 46, 48, 49, 52, 53, 55, 56, 57, 58,
+ 59, 61, 62, 63, 85, 86, 88, 123, 142, 163, 221, 248, 249, 2099, 2108, 2157,
+ 2158, 2161, 2294, 4127, 20602,
+};
+
+static const short dep158[] = {
+ 2, 21, 33, 88, 172, 199, 208, 249, 2131, 2294, 28841, 28980,
+};
+
+static const short dep159[] = {
+ 2, 18, 19, 21, 22, 30, 32, 33, 88, 157, 158, 163, 172, 199, 208, 249, 2294,
+ 4127, 20602, 28841, 28980,
+};
+
+static const short dep160[] = {
+ 88, 117, 118, 120, 121, 125, 126, 129, 130, 131, 132, 133, 134, 135, 136,
+ 138, 141, 142, 146, 147, 150, 151, 152, 153, 154, 156, 157, 159, 160, 161,
+ 162, 164, 165, 166, 249, 272, 273, 277, 279, 280, 281, 282, 284, 286, 290,
+ 293, 294, 296, 297, 298, 299, 301, 302, 303, 305, 306,
+};
+
+static const short dep161[] = {
+ 32, 33, 64, 88, 123, 163, 249, 272, 273, 277, 279, 280, 281, 282, 284, 286,
+ 290, 293, 294, 296, 297, 298, 299, 301, 302, 303, 305, 306, 2129, 2130, 2131,
+ 2157, 2158, 2161, 4127, 20602,
+};
+
+static const short dep162[] = {
+ 88, 116, 118, 119, 121, 150, 151, 166, 249, 272, 273, 293, 294, 296, 297,
+ 306,
+};
+
+static const short dep163[] = {
+ 32, 33, 88, 162, 163, 249, 272, 273, 293, 294, 296, 297, 306, 2129, 2130,
+ 2131, 2157, 2158, 2161, 4127, 20602,
+};
+
+static const short dep164[] = {
+ 32, 33, 88, 118, 121, 123, 126, 127, 130, 132, 134, 136, 138, 139, 141, 145,
+ 146, 148, 149, 150, 151, 153, 154, 156, 158, 159, 161, 163, 165, 166, 249,
+ 2157, 2158, 2161, 2294, 4127, 20602,
+};
+
+static const short dep165[] = {
+ 32, 33, 88, 118, 121, 150, 151, 163, 166, 249, 2157, 2158, 2161, 2294, 4127,
+ 20602,
+};
+
+static const short dep166[] = {
+ 32, 33, 67, 68, 73, 75, 88, 102, 123, 152, 163, 167, 249, 2129, 2130, 2131,
+ 2157, 2158, 2161, 2294, 4127, 20602,
+};
+
+static const short dep167[] = {
+ 32, 33, 67, 68, 73, 75, 88, 102, 123, 124, 125, 127, 128, 152, 163, 167, 249,
+ 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602,
+};
+
+static const short dep168[] = {
+ 68, 69, 88, 92, 93, 236, 237, 249, 251, 252,
+};
+
+static const short dep169[] = {
+ 32, 33, 39, 54, 69, 71, 77, 88, 90, 93, 123, 142, 163, 167, 236, 237, 249,
+ 251, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602,
+};
+
+static const short dep170[] = {
+ 32, 33, 39, 54, 69, 71, 88, 90, 93, 95, 97, 123, 142, 163, 167, 236, 237,
+ 249, 251, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602,
+};
+
+static const short dep171[] = {
+ 88, 249, 12455, 12456, 12595,
+};
+
+static const short dep172[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 12595,
+ 20602,
+};
+
+static const short dep173[] = {
+ 88, 249, 6210, 6211, 6378,
+};
+
+static const short dep174[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6378,
+ 20602,
+};
+
+static const short dep175[] = {
+ 88, 249, 6228, 6391,
+};
+
+static const short dep176[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6391,
+ 20602,
+};
+
+static const short dep177[] = {
+ 88, 249, 6246, 6247, 6248, 6249, 6402, 6404, 8451,
+};
+
+static const short dep178[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6249,
+ 6403, 6404, 8295, 8450, 20602,
+};
+
+static const short dep179[] = {
+ 88, 249, 6250, 6251, 6405,
+};
+
+static const short dep180[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6405,
+ 20602,
+};
+
+static const short dep181[] = {
+ 88, 249, 6252, 6406,
+};
+
+static const short dep182[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6406,
+ 20602,
+};
+
+static const short dep183[] = {
+ 88, 249, 10341, 10497,
+};
+
+static const short dep184[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 10497,
+ 20602,
+};
+
+static const short dep185[] = {
+ 68, 69, 73, 74, 88, 92, 93, 236, 237, 239, 240, 249, 251, 252,
+};
+
+static const short dep186[] = {
+ 32, 33, 39, 69, 71, 74, 77, 88, 90, 93, 123, 142, 163, 167, 236, 237, 239,
+ 241, 249, 251, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602,
+};
+
+static const short dep187[] = {
+ 68, 69, 88, 92, 93, 95, 96, 236, 237, 249, 251, 252, 253, 254,
+};
+
+static const short dep188[] = {
+ 32, 33, 39, 54, 69, 71, 88, 90, 93, 95, 97, 123, 142, 163, 167, 236, 237,
+ 249, 251, 252, 253, 254, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602,
+
+};
+
+static const short dep189[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127,
+ 12456, 20602,
+};
+
+static const short dep190[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127,
+ 6210, 20602,
+};
+
+static const short dep191[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127,
+ 6228, 20602,
+};
+
+static const short dep192[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127,
+ 6248, 8294, 20602,
+};
+
+static const short dep193[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127,
+ 6250, 20602,
+};
+
+static const short dep194[] = {
+ 32, 33, 88, 123, 162, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294,
+ 4127, 6251, 6252, 20602,
+};
+
+static const short dep195[] = {
+ 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127,
+ 10341, 20602,
+};
+
+static const short dep196[] = {
+ 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 6178,
+ 20602,
+};
+
+static const short dep197[] = {
+ 68, 70, 71, 88, 89, 90, 91, 235, 236, 249, 250, 251,
+};
+
+static const short dep198[] = {
+ 32, 33, 69, 70, 74, 76, 88, 91, 93, 95, 98, 123, 163, 167, 235, 237, 249,
+ 250, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602,
+};
+
+static const short dep199[] = {
+ 68, 70, 71, 72, 88, 89, 90, 91, 94, 235, 236, 238, 249, 250, 251,
+};
+
+static const short dep200[] = {
+ 32, 33, 69, 70, 72, 74, 76, 88, 91, 93, 94, 95, 98, 123, 163, 167, 235, 237,
+ 238, 249, 250, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602,
+};
+
+static const short dep201[] = {
+ 68, 70, 71, 75, 76, 77, 88, 89, 90, 91, 235, 236, 241, 242, 249, 250, 251,
+
+};
+
+static const short dep202[] = {
+ 32, 33, 69, 70, 74, 76, 88, 91, 93, 123, 163, 167, 235, 237, 240, 242, 249,
+ 250, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602,
+};
+
+static const short dep203[] = {
+ 68, 70, 71, 88, 89, 90, 91, 97, 98, 99, 235, 236, 249, 250, 251, 254, 255,
+
+};
+
+static const short dep204[] = {
+ 32, 33, 69, 70, 88, 91, 93, 95, 98, 123, 163, 167, 235, 237, 249, 250, 252,
+ 253, 255, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602,
+};
+
+static const short dep205[] = {
+ 32, 33, 38, 62, 88, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294,
+ 4127, 20602,
+};
+
+static const short dep206[] = {
+ 32, 33, 88, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127,
+ 20602,
+};
+
+static const short dep207[] = {
+ 32, 33, 68, 73, 75, 88, 123, 163, 167, 249, 2129, 2130, 2131, 2157, 2158,
+ 2161, 2294, 4127, 20602,
+};
+
+static const short dep208[] = {
+ 32, 33, 88, 145, 163, 164, 249, 2126, 2127, 2128, 2129, 2130, 2131, 2157,
+ 2158, 2161, 4127, 16513, 16515, 20602,
+};
+
+static const short dep209[] = {
+ 32, 33, 68, 73, 75, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127,
+ 20602,
+};
+
+static const short dep210[] = {
+ 32, 33, 69, 70, 88, 91, 123, 163, 235, 237, 249, 250, 252, 2129, 2130, 2131,
+ 2157, 2158, 2161, 4127, 20602,
+};
+
+static const short dep211[] = {
+ 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, 127,
+ 128, 135, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127,
+ 20602,
+};
+
+static const short dep212[] = {
+ 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125,
+ 127, 128, 135, 137, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161,
+ 2294, 4127, 20602,
+};
+
+static const short dep213[] = {
+ 0, 88, 170, 249, 2131, 2294,
+};
+
+static const short dep214[] = {
+ 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125,
+ 127, 128, 135, 152, 163, 167, 170, 249, 2129, 2130, 2131, 2157, 2158, 2161,
+ 2294, 4127, 20602,
+};
+
+static const short dep215[] = {
+ 0, 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124,
+ 125, 127, 128, 135, 137, 152, 163, 167, 170, 249, 2129, 2130, 2131, 2157,
+ 2158, 2161, 2294, 4127, 20602,
+};
+
+static const short dep216[] = {
+ 23, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125,
+ 127, 128, 135, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294,
+ 4127, 20602,
+};
+
+static const short dep217[] = {
+ 0, 88, 170, 249, 2294, 26706,
+};
+
+static const short dep218[] = {
+ 0, 88, 100, 170, 249, 256,
+};
+
+static const short dep219[] = {
+ 0, 32, 33, 67, 68, 73, 75, 88, 102, 116, 117, 119, 120, 123, 124, 125, 127,
+ 128, 135, 152, 163, 167, 170, 249, 256, 2129, 2130, 2131, 2157, 2158, 2161,
+ 4127, 20602,
+};
+
+static const short dep220[] = {
+ 0, 23, 88, 100, 170, 201, 249, 256,
+};
+
+static const short dep221[] = {
+ 0, 32, 33, 67, 68, 73, 75, 88, 102, 116, 117, 119, 120, 123, 124, 125, 127,
+ 128, 135, 152, 163, 167, 170, 201, 249, 256, 2129, 2130, 2131, 2157, 2158,
+ 2161, 4127, 20602,
+};
+
+static const short dep222[] = {
+ 0, 88, 100, 170, 249, 256, 2131, 2294,
+};
+
+static const short dep223[] = {
+ 0, 3, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124,
+ 125, 127, 128, 135, 152, 163, 167, 170, 249, 256, 2129, 2130, 2131, 2157,
+ 2158, 2161, 2294, 4127, 20602,
+};
+
+static const short dep224[] = {
+ 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125,
+ 127, 128, 135, 152, 163, 167, 170, 249, 256, 2129, 2130, 2131, 2157, 2158,
+ 2161, 2294, 4127, 20602,
+};
+
+static const short dep225[] = {
+ 32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 2294, 4127, 16513,
+ 16515, 20602,
+};
+
+static const short dep226[] = {
+ 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, 127,
+ 128, 135, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2292, 4127,
+ 16513, 16515, 18724, 18726, 18727, 18729, 20602,
+};
+
+static const short dep227[] = {
+ 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125,
+ 127, 128, 135, 137, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161,
+ 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 20602,
+};
+
+static const short dep228[] = {
+ 0, 88, 170, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728,
+};
+
+static const short dep229[] = {
+ 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125,
+ 127, 128, 135, 152, 163, 167, 170, 249, 2129, 2130, 2131, 2157, 2158, 2161,
+ 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 20602,
+};
+
+static const short dep230[] = {
+ 0, 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124,
+ 125, 127, 128, 135, 137, 152, 163, 167, 170, 249, 2129, 2130, 2131, 2157,
+ 2158, 2161, 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 20602,
+};
+
+static const short dep231[] = {
+ 0, 88, 170, 249, 2128, 2292, 18582, 18583, 18724, 18725, 18727, 18728,
+};
+
+static const short dep232[] = {
+ 32, 33, 67, 88, 123, 137, 163, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep233[] = {
+ 32, 33, 67, 88, 123, 124, 128, 137, 163, 249, 2157, 2158, 2161, 4127,
+};
+
+static const short dep234[] = {
+ 32, 33, 67, 88, 123, 137, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294,
+ 4127, 20602,
+};
+
+static const short dep235[] = {
+ 32, 33, 67, 88, 123, 124, 128, 137, 163, 249, 2129, 2130, 2131, 2157, 2158,
+ 2161, 2294, 4127, 20602,
+};
+
+static const short dep236[] = {
+ 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602,
+};
+
+static const short dep237[] = {
+ 32, 33, 88, 163, 249, 2157, 2158, 2159, 2160, 2161, 2162, 2163, 4127,
+};
+
+static const short dep238[] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 19, 20, 21, 22, 23,
+ 88, 171, 172, 173, 174, 175, 176, 177, 178, 180, 181, 183, 184, 186, 187,
+ 189, 190, 191, 192, 193, 195, 198, 199, 200, 201, 249, 2064, 2073, 2131, 2242,
+ 2251, 2294, 28841, 28980,
+};
+
+static const short dep239[] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23,
+ 32, 33, 88, 123, 160, 163, 171, 172, 173, 174, 175, 176, 177, 178, 180, 181,
+ 183, 184, 186, 187, 189, 190, 191, 192, 193, 195, 197, 199, 200, 201, 249,
+ 2064, 2073, 2129, 2130, 2131, 2157, 2158, 2161, 2242, 2251, 2294, 4127, 20602,
+ 28841, 28980,
+};
+
+#define NELS(X) (sizeof(X)/sizeof(X[0]))
+static const struct ia64_opcode_dependency
+op_dependencies[] = {
+ { NELS(dep1), dep1, NELS(dep0), dep0, },
+ { NELS(dep3), dep3, NELS(dep2), dep2, },
+ { NELS(dep4), dep4, NELS(dep0), dep0, },
+ { NELS(dep6), dep6, NELS(dep5), dep5, },
+ { NELS(dep8), dep8, NELS(dep7), dep7, },
+ { NELS(dep10), dep10, NELS(dep9), dep9, },
+ { NELS(dep12), dep12, NELS(dep11), dep11, },
+ { NELS(dep14), dep14, NELS(dep13), dep13, },
+ { NELS(dep16), dep16, NELS(dep15), dep15, },
+ { NELS(dep18), dep18, NELS(dep17), dep17, },
+ { NELS(dep20), dep20, NELS(dep19), dep19, },
+ { NELS(dep22), dep22, NELS(dep21), dep21, },
+ { NELS(dep24), dep24, NELS(dep23), dep23, },
+ { NELS(dep26), dep26, NELS(dep25), dep25, },
+ { NELS(dep28), dep28, NELS(dep27), dep27, },
+ { NELS(dep30), dep30, NELS(dep29), dep29, },
+ { NELS(dep31), dep31, NELS(dep15), dep15, },
+ { NELS(dep33), dep33, NELS(dep32), dep32, },
+ { NELS(dep35), dep35, NELS(dep34), dep34, },
+ { NELS(dep36), dep36, NELS(dep15), dep15, },
+ { NELS(dep38), dep38, NELS(dep37), dep37, },
+ { NELS(dep40), dep40, NELS(dep39), dep39, },
+ { NELS(dep42), dep42, NELS(dep41), dep41, },
+ { NELS(dep43), dep43, NELS(dep32), dep32, },
+ { NELS(dep44), dep44, NELS(dep34), dep34, },
+ { NELS(dep46), dep46, NELS(dep45), dep45, },
+ { NELS(dep48), dep48, NELS(dep47), dep47, },
+ { NELS(dep50), dep50, NELS(dep49), dep49, },
+ { NELS(dep52), dep52, NELS(dep51), dep51, },
+ { NELS(dep54), dep54, NELS(dep53), dep53, },
+ { NELS(dep56), dep56, NELS(dep55), dep55, },
+ { NELS(dep58), dep58, NELS(dep57), dep57, },
+ { NELS(dep60), dep60, NELS(dep59), dep59, },
+ { NELS(dep62), dep62, NELS(dep61), dep61, },
+ { NELS(dep64), dep64, NELS(dep63), dep63, },
+ { NELS(dep66), dep66, NELS(dep65), dep65, },
+ { NELS(dep68), dep68, NELS(dep67), dep67, },
+ { NELS(dep69), dep69, NELS(dep34), dep34, },
+ { NELS(dep71), dep71, NELS(dep70), dep70, },
+ { NELS(dep73), dep73, NELS(dep72), dep72, },
+ { NELS(dep75), dep75, NELS(dep74), dep74, },
+ { NELS(dep77), dep77, NELS(dep76), dep76, },
+ { NELS(dep78), dep78, NELS(dep34), dep34, },
+ { NELS(dep80), dep80, NELS(dep79), dep79, },
+ { NELS(dep82), dep82, NELS(dep81), dep81, },
+ { NELS(dep84), dep84, NELS(dep83), dep83, },
+ { NELS(dep85), dep85, NELS(dep34), dep34, },
+ { NELS(dep86), dep86, NELS(dep34), dep34, },
+ { NELS(dep87), dep87, NELS(dep34), dep34, },
+ { NELS(dep88), dep88, NELS(dep34), dep34, },
+ { NELS(dep90), dep90, NELS(dep89), dep89, },
+ { NELS(dep92), dep92, NELS(dep91), dep91, },
+ { NELS(dep94), dep94, NELS(dep93), dep93, },
+ { NELS(dep96), dep96, NELS(dep95), dep95, },
+ { NELS(dep98), dep98, NELS(dep97), dep97, },
+ { NELS(dep100), dep100, NELS(dep99), dep99, },
+ { NELS(dep102), dep102, NELS(dep101), dep101, },
+ { NELS(dep104), dep104, NELS(dep103), dep103, },
+ { NELS(dep106), dep106, NELS(dep105), dep105, },
+ { NELS(dep108), dep108, NELS(dep107), dep107, },
+ { NELS(dep110), dep110, NELS(dep109), dep109, },
+ { NELS(dep112), dep112, NELS(dep111), dep111, },
+ { NELS(dep114), dep114, NELS(dep113), dep113, },
+ { NELS(dep116), dep116, NELS(dep115), dep115, },
+ { NELS(dep118), dep118, NELS(dep117), dep117, },
+ { NELS(dep120), dep120, NELS(dep119), dep119, },
+ { NELS(dep122), dep122, NELS(dep121), dep121, },
+ { NELS(dep123), dep123, NELS(dep65), dep65, },
+ { NELS(dep124), dep124, NELS(dep34), dep34, },
+ { NELS(dep126), dep126, NELS(dep125), dep125, },
+ { NELS(dep127), dep127, NELS(dep0), dep0, },
+ { NELS(dep129), dep129, NELS(dep128), dep128, },
+ { NELS(dep131), dep131, NELS(dep130), dep130, },
+ { NELS(dep132), dep132, NELS(dep0), dep0, },
+ { NELS(dep133), dep133, NELS(dep0), dep0, },
+ { NELS(dep135), dep135, NELS(dep134), dep134, },
+ { NELS(dep136), dep136, NELS(dep0), dep0, },
+ { NELS(dep137), dep137, NELS(dep34), dep34, },
+ { NELS(dep139), dep139, NELS(dep138), dep138, },
+ { NELS(dep140), dep140, NELS(dep138), dep138, },
+ { NELS(dep142), dep142, NELS(dep141), dep141, },
+ { NELS(dep143), dep143, NELS(dep141), dep141, },
+ { NELS(dep144), dep144, NELS(dep138), dep138, },
+ { NELS(dep146), dep146, NELS(dep145), dep145, },
+ { NELS(dep148), dep148, NELS(dep147), dep147, },
+ { NELS(dep150), dep150, NELS(dep149), dep149, },
+ { NELS(dep152), dep152, NELS(dep151), dep151, },
+ { NELS(dep153), dep153, NELS(dep0), dep0, },
+ { NELS(dep155), dep155, NELS(dep154), dep154, },
+ { NELS(dep157), dep157, NELS(dep156), dep156, },
+ { NELS(dep159), dep159, NELS(dep158), dep158, },
+ { NELS(dep161), dep161, NELS(dep160), dep160, },
+ { NELS(dep163), dep163, NELS(dep162), dep162, },
+ { NELS(dep164), dep164, NELS(dep0), dep0, },
+ { NELS(dep165), dep165, NELS(dep0), dep0, },
+ { NELS(dep166), dep166, NELS(dep0), dep0, },
+ { NELS(dep167), dep167, NELS(dep34), dep34, },
+ { NELS(dep169), dep169, NELS(dep168), dep168, },
+ { NELS(dep170), dep170, NELS(dep168), dep168, },
+ { NELS(dep172), dep172, NELS(dep171), dep171, },
+ { NELS(dep174), dep174, NELS(dep173), dep173, },
+ { NELS(dep176), dep176, NELS(dep175), dep175, },
+ { NELS(dep178), dep178, NELS(dep177), dep177, },
+ { NELS(dep180), dep180, NELS(dep179), dep179, },
+ { NELS(dep182), dep182, NELS(dep181), dep181, },
+ { NELS(dep184), dep184, NELS(dep183), dep183, },
+ { NELS(dep186), dep186, NELS(dep185), dep185, },
+ { NELS(dep188), dep188, NELS(dep187), dep187, },
+ { NELS(dep189), dep189, NELS(dep0), dep0, },
+ { NELS(dep190), dep190, NELS(dep0), dep0, },
+ { NELS(dep191), dep191, NELS(dep0), dep0, },
+ { NELS(dep192), dep192, NELS(dep0), dep0, },
+ { NELS(dep193), dep193, NELS(dep0), dep0, },
+ { NELS(dep194), dep194, NELS(dep0), dep0, },
+ { NELS(dep195), dep195, NELS(dep0), dep0, },
+ { NELS(dep196), dep196, NELS(dep0), dep0, },
+ { NELS(dep198), dep198, NELS(dep197), dep197, },
+ { NELS(dep200), dep200, NELS(dep199), dep199, },
+ { NELS(dep202), dep202, NELS(dep201), dep201, },
+ { NELS(dep204), dep204, NELS(dep203), dep203, },
+ { NELS(dep205), dep205, NELS(dep0), dep0, },
+ { NELS(dep206), dep206, NELS(dep0), dep0, },
+ { NELS(dep207), dep207, NELS(dep0), dep0, },
+ { NELS(dep208), dep208, NELS(dep34), dep34, },
+ { NELS(dep209), dep209, NELS(dep34), dep34, },
+ { NELS(dep210), dep210, NELS(dep197), dep197, },
+ { NELS(dep211), dep211, NELS(dep0), dep0, },
+ { NELS(dep212), dep212, NELS(dep0), dep0, },
+ { NELS(dep214), dep214, NELS(dep213), dep213, },
+ { NELS(dep215), dep215, NELS(dep213), dep213, },
+ { NELS(dep216), dep216, NELS(dep0), dep0, },
+ { NELS(dep214), dep214, NELS(dep217), dep217, },
+ { NELS(dep219), dep219, NELS(dep218), dep218, },
+ { NELS(dep221), dep221, NELS(dep220), dep220, },
+ { NELS(dep223), dep223, NELS(dep222), dep222, },
+ { NELS(dep224), dep224, NELS(dep222), dep222, },
+ { NELS(dep225), dep225, NELS(dep0), dep0, },
+ { NELS(dep226), dep226, NELS(dep65), dep65, },
+ { NELS(dep227), dep227, NELS(dep65), dep65, },
+ { NELS(dep229), dep229, NELS(dep228), dep228, },
+ { NELS(dep230), dep230, NELS(dep228), dep228, },
+ { NELS(dep229), dep229, NELS(dep231), dep231, },
+ { NELS(dep232), dep232, NELS(dep34), dep34, },
+ { NELS(dep233), dep233, NELS(dep34), dep34, },
+ { NELS(dep234), dep234, NELS(dep0), dep0, },
+ { NELS(dep235), dep235, NELS(dep0), dep0, },
+ { NELS(dep236), dep236, NELS(dep34), dep34, },
+ { NELS(dep237), dep237, NELS(dep15), dep15, },
+ { NELS(dep239), dep239, NELS(dep238), dep238, },
+};
+
+static const struct ia64_completer_table
+completer_table[] = {
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 0 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 1 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 90 },
+ { 0x0, 0x0, 0, 123, -1, 0, 1, 8 },
+ { 0x0, 0x0, 0, 128, -1, 0, 1, 19 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 147 },
+ { 0x0, 0x0, 0, 502, -1, 0, 1, 12 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 11 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 73 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 15 },
+ { 0x1, 0x1, 0, 716, -1, 13, 1, 0 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 35 },
+ { 0x0, 0x0, 0, 142, -1, 0, 1, 31 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 31 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 124 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 46 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 42 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 80 },
+ { 0x0, 0x0, 0, 144, -1, 0, 1, 31 },
+ { 0x0, 0x0, 0, 146, -1, 0, 1, 31 },
+ { 0x0, 0x0, 0, 533, -1, 0, 1, 31 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 26 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 37 },
+ { 0x0, 0x0, 0, 419, -1, 0, 1, 35 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 79 },
+ { 0x0, 0x0, 0, 78, -1, 0, 1, 126 },
+ { 0x0, 0x0, 0, 79, -1, 0, 1, 126 },
+ { 0x0, 0x0, 0, 80, -1, 0, 1, 137 },
+ { 0x0, 0x0, 0, 218, -1, 0, 1, 142 },
+ { 0x0, 0x0, 0, 220, -1, 0, 1, 144 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 81 },
+ { 0x0, 0x0, 0, 81, -1, 0, 1, 42 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 2 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 69 },
+ { 0x1, 0x1, 0, 205, -1, 20, 1, 69 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 70 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 71 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 72 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 74 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 88 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 89 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 91 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 92 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 93 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 94 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 99 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 100 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 101 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 102 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 103 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 104 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 105 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 108 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 109 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 110 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 111 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 112 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 113 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 114 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 115 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 148 },
+ { 0x0, 0x0, 0, 712, -1, 0, 1, 0 },
+ { 0x0, 0x0, 0, 509, -1, 0, 1, 0 },
+ { 0x0, 0x0, 0, 717, -1, 0, 1, 0 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 13 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 86 },
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+ { 0x41, 0x41, 147, -1, 129, 6, 1, 20 },
+ { 0x600001, 0x600001, 147, -1, 130, 12, 1, 21 },
+ { 0x400001, 0x400001, 147, -1, 130, 12, 1, 21 },
+ { 0x200001, 0x200001, 147, -1, 130, 12, 1, 21 },
+ { 0x1, 0x1, 147, -1, 130, 12, 1, 21 },
+ { 0x600001, 0x600001, 147, -1, 131, 12, 1, 22 },
+ { 0x400001, 0x400001, 147, -1, 131, 12, 1, 22 },
+ { 0x200001, 0x200001, 147, -1, 131, 12, 1, 22 },
+ { 0x1, 0x1, 147, -1, 131, 12, 1, 22 },
+ { 0x18000041, 0x18000041, 147, -1, 131, 6, 1, 22 },
+ { 0x10000041, 0x10000041, 147, -1, 131, 6, 1, 22 },
+ { 0x8000041, 0x8000041, 147, -1, 131, 6, 1, 22 },
+ { 0x41, 0x41, 147, -1, 131, 6, 1, 22 },
+ { 0x600001, 0x600001, 147, -1, 132, 12, 1, 23 },
+ { 0x400001, 0x400001, 147, -1, 132, 12, 1, 23 },
+ { 0x200001, 0x200001, 147, -1, 132, 12, 1, 23 },
+ { 0x1, 0x1, 147, -1, 132, 12, 1, 23 },
+ { 0x0, 0x0, 156, -1, -1, 0, 1, 77 },
+ { 0x9, 0x9, 156, -1, 435, 32, 1, 131 },
+ { 0x9, 0x9, 156, -1, 442, 32, 1, 141 },
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+ { 0x1, 0x1, 157, -1, 718, 38, 1, 3 },
+ { 0x0, 0x0, 157, -1, 102, 0, 0, -1 },
+ { 0x0, 0x0, 157, -1, 93, 0, 0, -1 },
+ { 0x0, 0x0, 158, 420, 538, 0, 0, -1 },
+ { 0x0, 0x0, 158, 421, 724, 0, 1, 56 },
+ { 0x0, 0x0, 158, 422, 557, 0, 0, -1 },
+ { 0x1, 0x1, 158, 423, -1, 29, 1, 51 },
+ { 0x0, 0x0, 159, 417, 546, 0, 0, -1 },
+ { 0x1, 0x9, 159, 418, 724, 33, 1, 56 },
+ { 0x0, 0x0, 160, -1, 538, 0, 0, -1 },
+ { 0x0, 0x0, 160, -1, 724, 0, 1, 56 },
+ { 0x1, 0x1, 161, 429, -1, 27, 1, 35 },
+ { 0x0, 0x0, 162, 424, 540, 0, 0, -1 },
+ { 0x1, 0x1, 162, 425, 724, 33, 1, 56 },
+ { 0x0, 0x0, 162, 426, 558, 0, 0, -1 },
+ { 0x3, 0x3, 162, 427, -1, 28, 1, 51 },
+ { 0x0, 0x0, 163, 498, 542, 0, 0, -1 },
+ { 0x1, 0x1, 163, 499, 724, 36, 1, 56 },
+ { 0x0, 0x0, 163, 500, 559, 0, 0, -1 },
+ { 0x5, 0x5, 163, 501, -1, 27, 1, 51 },
+ { 0x0, 0x0, 164, -1, 719, 0, 1, 65 },
+ { 0x1, 0x1, 166, -1, -1, 28, 1, 35 },
+ { 0x1, 0x1, 167, 526, -1, 27, 1, 35 },
+ { 0x1, 0x1, 168, 454, -1, 28, 1, 134 },
+ { 0x1, 0x1, 168, 455, -1, 28, 1, 135 },
+ { 0x1, 0x1, 168, 456, -1, 28, 1, 128 },
+ { 0x1, 0x1, 168, 457, -1, 28, 1, 126 },
+ { 0x1, 0x1, 168, 458, -1, 28, 1, 131 },
+ { 0x1, 0x1, 168, 459, -1, 28, 1, 127 },
+ { 0x1, 0x1, 168, 460, -1, 28, 1, 129 },
+ { 0x1, 0x1, 168, 461, -1, 28, 1, 126 },
+ { 0x1, 0x1, 168, 462, -1, 28, 1, 130 },
+ { 0x1, 0x1, 168, 463, -1, 28, 1, 137 },
+ { 0x1, 0x1, 168, 464, -1, 28, 1, 139 },
+ { 0x1, 0x1, 168, 465, -1, 28, 1, 141 },
+ { 0x1, 0x1, 168, 466, -1, 28, 1, 138 },
+ { 0x1, 0x1, 168, 467, -1, 28, 1, 140 },
+ { 0x1, 0x1, 168, 468, -1, 28, 1, 137 },
+ { 0x1, 0x1, 168, 450, -1, 28, 1, 142 },
+ { 0x1, 0x1, 168, 451, -1, 28, 1, 143 },
+ { 0x1, 0x1, 168, 452, -1, 28, 1, 144 },
+ { 0x1, 0x1, 168, 453, -1, 28, 1, 145 },
+ { 0x1, 0x1, 169, 469, -1, 29, 1, 142 },
+ { 0x1, 0x1, 169, 470, -1, 29, 1, 143 },
+ { 0x1, 0x1, 169, 471, -1, 29, 1, 144 },
+ { 0x1, 0x1, 169, 472, -1, 29, 1, 145 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 134 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 135 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 128 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 126 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 131 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 127 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 129 },
+ { 0x3, 0x3, 170, 530, -1, 28, 1, 126 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 130 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 137 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 139 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 141 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 138 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 140 },
+ { 0x3, 0x3, 170, 531, -1, 28, 1, 137 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 142 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 143 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 144 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 145 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 132 },
+ { 0x3, 0x3, 170, 512, -1, 28, 1, 132 },
+ { 0x3, 0x3, 170, -1, -1, 28, 1, 133 },
+ { 0x3, 0x3, 170, 513, -1, 28, 1, 132 },
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+ { 0x0, 0x0, 171, 745, 98, 0, 1, 3 },
+ { 0x11, 0x31, 172, 718, 100, 33, 1, 6 },
+ { 0x2200001, 0x2200001, 172, -1, 100, 12, 1, 6 },
+ { 0x11, 0x11, 172, -1, 100, 33, 1, 6 },
+ { 0x1, 0x1, 172, -1, 100, 37, 1, 6 },
+ { 0x2000001, 0x2000001, 172, -1, 100, 12, 1, 6 },
+ { 0x200001, 0x200001, 172, -1, 105, 12, 1, 6 },
+ { 0x1, 0x1, 172, 718, 105, 33, 1, 6 },
+ { 0x2000001, 0x2000001, 173, -1, -1, 12, 1, 6 },
+ { 0x1, 0x1, 173, -1, -1, 37, 1, 6 },
+ { 0x2200001, 0x2200001, 173, -1, -1, 12, 1, 6 },
+ { 0x11, 0x11, 173, -1, -1, 33, 1, 6 },
+ { 0x1, 0x1, 173, -1, -1, 12, 1, 7 },
+ { 0x0, 0x0, 173, -1, -1, 0, 1, 7 },
+ { 0x200001, 0x200001, 173, -1, -1, 12, 1, 7 },
+ { 0x1, 0x1, 173, -1, -1, 33, 1, 7 },
+ { 0x9, 0x9, 173, -1, -1, 33, 1, 7 },
+ { 0x1, 0x1, 173, 718, -1, 33, 1, 6 },
+ { 0x1200001, 0x1200001, 173, -1, -1, 12, 1, 7 },
+ { 0x200001, 0x200001, 173, -1, -1, 12, 1, 6 },
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+ { 0x9, 0x9, 174, -1, 725, 33, 1, 51 },
+ { 0x0, 0x0, 174, 729, 560, 0, 0, -1 },
+ { 0x7, 0x7, 174, 730, -1, 27, 1, 51 },
+ { 0x1, 0x1, 194, -1, -1, 27, 1, 12 },
+ { 0x1, 0x1, 208, -1, -1, 29, 1, 0 },
+ { 0x2, 0x3, 208, -1, -1, 27, 1, 35 },
+ { 0x0, 0x0, 208, -1, -1, 0, 1, 35 },
+ { 0x0, 0x0, 208, -1, -1, 0, 1, 0 },
+ { 0x0, 0x0, 208, 734, -1, 0, 1, 95 },
+ { 0x0, 0x0, 208, 518, 227, 0, 0, -1 },
+ { 0x1, 0x1, 209, -1, -1, 27, 1, 0 },
+ { 0x1, 0x1, 210, -1, 431, 32, 1, 134 },
+ { 0x1, 0x1, 210, -1, 432, 32, 1, 135 },
+ { 0x1, 0x1, 210, -1, 473, 32, 1, 132 },
+ { 0x1, 0x1, 210, 659, 473, 32, 1, 132 },
+ { 0x0, 0x0, 211, -1, 159, 0, 0, -1 },
+ { 0x0, 0x0, 211, -1, 160, 0, 0, -1 },
+ { 0x0, 0x0, 211, 706, 201, 0, 0, -1 },
+ { 0x5, 0x5, 211, 709, 204, 20, 1, 69 },
+ { 0x0, 0x0, 215, 735, 228, 0, 0, -1 },
+ { 0x0, 0x0, 216, -1, 307, 0, 0, -1 },
+ { 0x0, 0x0, 216, -1, 356, 0, 0, -1 },
+ { 0x0, 0x0, 216, -1, -1, 0, 1, 123 },
+ { 0x0, 0x0, 216, -1, -1, 0, 1, 68 },
+ { 0x1, 0x1, 216, 533, 534, 36, 1, 67 },
+ { 0x1, 0x1, 216, 533, 565, 36, 1, 67 },
+ { 0x0, 0x0, 216, -1, 552, 0, 0, -1 },
+ { 0x0, 0x0, 216, 656, -1, 0, 1, 35 },
+ { 0x0, 0x0, 216, 533, 553, 0, 0, -1 },
+ { 0x1, 0x1, 216, -1, -1, 36, 1, 67 },
+ { 0x1, 0x1, 216, 657, -1, 31, 1, 136 },
+ { 0x1, 0x1, 216, 654, 436, 32, 1, 127 },
+ { 0x1, 0x1, 216, 655, 443, 32, 1, 138 },
+ { 0x1, 0x1, 216, 658, -1, 31, 1, 146 },
+ { 0x0, 0x0, 217, 564, -1, 0, 1, 30 },
+ { 0x0, 0x0, 217, 565, -1, 0, 1, 67 },
+ { 0x0, 0x0, 217, 566, -1, 0, 1, 46 },
+ { 0x0, 0x0, 217, 567, -1, 0, 1, 41 },
+ { 0x1, 0x1, 217, 568, -1, 12, 1, 60 },
+ { 0x0, 0x0, 217, 569, -1, 0, 1, 55 },
+ { 0x200001, 0x200001, 217, 570, -1, 12, 1, 60 },
+ { 0x1, 0x1, 217, 571, -1, 33, 1, 55 },
+ { 0x1000001, 0x1000001, 217, 572, -1, 12, 1, 60 },
+ { 0x1, 0x1, 217, 573, -1, 36, 1, 55 },
+ { 0x1200001, 0x1200001, 217, 574, -1, 12, 1, 50 },
+ { 0x9, 0x9, 217, 575, -1, 33, 1, 50 },
+ { 0x200001, 0x1200001, 217, 576, -1, 12, 1, 60 },
+ { 0x1, 0x9, 217, 577, -1, 33, 1, 55 },
+ { 0x1, 0x1, 217, 578, -1, 28, 1, 30 },
+ { 0x0, 0x0, 217, 579, -1, 0, 1, 30 },
+ { 0x3, 0x3, 217, 580, -1, 27, 1, 30 },
+ { 0x1, 0x1, 217, 581, -1, 27, 1, 30 },
+ { 0x1, 0x1, 217, 582, -1, 37, 1, 30 },
+ { 0x1, 0x1, 217, -1, -1, 36, 1, 67 },
+ { 0x1, 0x1, 217, 583, -1, 36, 1, 67 },
+ { 0x0, 0x0, 217, 584, -1, 0, 1, 50 },
+ { 0x1, 0x1, 217, 585, -1, 28, 1, 50 },
+ { 0x1, 0x1, 217, 586, -1, 27, 1, 50 },
+ { 0x1, 0x1, 217, 587, -1, 29, 1, 50 },
+ { 0x3, 0x3, 217, 588, -1, 28, 1, 50 },
+ { 0x5, 0x5, 217, 589, -1, 27, 1, 50 },
+ { 0x7, 0x7, 217, 590, -1, 27, 1, 50 },
+ { 0x3, 0x3, 217, 591, -1, 27, 1, 50 },
+ { 0x0, 0x0, 217, 592, -1, 0, 1, 25 },
+ { 0x0, 0x0, 217, 593, -1, 0, 1, 36 },
+ { 0x1, 0x1, 218, 594, -1, 34, 1, 32 },
+ { 0x1, 0x1, 218, 595, -1, 34, 1, 67 },
+ { 0x1, 0x1, 218, 596, -1, 34, 1, 47 },
+ { 0x1, 0x1, 218, 597, -1, 34, 1, 43 },
+ { 0x400001, 0x400001, 218, 598, -1, 12, 1, 62 },
+ { 0x1, 0x1, 218, 599, -1, 34, 1, 57 },
+ { 0x600001, 0x600001, 218, 600, -1, 12, 1, 62 },
+ { 0x3, 0x3, 218, 601, -1, 33, 1, 57 },
+ { 0x1400001, 0x1400001, 218, 602, -1, 12, 1, 62 },
+ { 0x5, 0x5, 218, 603, -1, 34, 1, 57 },
+ { 0x1600001, 0x1600001, 218, 604, -1, 12, 1, 52 },
+ { 0xb, 0xb, 218, 605, -1, 33, 1, 52 },
+ { 0x600001, 0x1600001, 218, 606, -1, 12, 1, 62 },
+ { 0x3, 0xb, 218, 607, -1, 33, 1, 57 },
+ { 0x41, 0x41, 218, 608, -1, 28, 1, 32 },
+ { 0x1, 0x1, 218, 609, -1, 34, 1, 32 },
+ { 0x83, 0x83, 218, 610, -1, 27, 1, 32 },
+ { 0x81, 0x81, 218, 611, -1, 27, 1, 32 },
+ { 0x9, 0x9, 218, 612, -1, 34, 1, 32 },
+ { 0x5, 0x5, 218, 613, -1, 34, 1, 67 },
+ { 0x1, 0x1, 218, 614, -1, 34, 1, 52 },
+ { 0x41, 0x41, 218, 615, -1, 28, 1, 52 },
+ { 0x81, 0x81, 218, 616, -1, 27, 1, 52 },
+ { 0x21, 0x21, 218, 617, -1, 29, 1, 52 },
+ { 0x43, 0x43, 218, 618, -1, 28, 1, 52 },
+ { 0x85, 0x85, 218, 619, -1, 27, 1, 52 },
+ { 0x87, 0x87, 218, 620, -1, 27, 1, 52 },
+ { 0x83, 0x83, 218, 621, -1, 27, 1, 52 },
+ { 0x1, 0x1, 218, 622, -1, 34, 1, 27 },
+ { 0x1, 0x1, 218, 623, -1, 34, 1, 38 },
+ { 0x1, 0x1, 219, 624, -1, 35, 1, 33 },
+ { 0x1, 0x1, 219, 625, -1, 35, 1, 67 },
+ { 0x1, 0x1, 219, 626, -1, 35, 1, 48 },
+ { 0x1, 0x1, 219, 627, -1, 35, 1, 44 },
+ { 0x800001, 0x800001, 219, 628, -1, 12, 1, 63 },
+ { 0x1, 0x1, 219, 629, -1, 35, 1, 58 },
+ { 0xa00001, 0xa00001, 219, 630, -1, 12, 1, 63 },
+ { 0x5, 0x5, 219, 631, -1, 33, 1, 58 },
+ { 0x1800001, 0x1800001, 219, 632, -1, 12, 1, 63 },
+ { 0x3, 0x3, 219, 633, -1, 35, 1, 58 },
+ { 0x1a00001, 0x1a00001, 219, 634, -1, 12, 1, 53 },
+ { 0xd, 0xd, 219, 635, -1, 33, 1, 53 },
+ { 0xa00001, 0x1a00001, 219, 636, -1, 12, 1, 63 },
+ { 0x5, 0xd, 219, 637, -1, 33, 1, 58 },
+ { 0x81, 0x81, 219, 638, -1, 28, 1, 33 },
+ { 0x1, 0x1, 219, 639, -1, 35, 1, 33 },
+ { 0x103, 0x103, 219, 640, -1, 27, 1, 33 },
+ { 0x101, 0x101, 219, 641, -1, 27, 1, 33 },
+ { 0x5, 0x5, 219, 642, -1, 35, 1, 33 },
+ { 0x3, 0x3, 219, 643, -1, 35, 1, 67 },
+ { 0x1, 0x1, 219, 644, -1, 35, 1, 53 },
+ { 0x81, 0x81, 219, 645, -1, 28, 1, 53 },
+ { 0x101, 0x101, 219, 646, -1, 27, 1, 53 },
+ { 0x41, 0x41, 219, 647, -1, 29, 1, 53 },
+ { 0x83, 0x83, 219, 648, -1, 28, 1, 53 },
+ { 0x105, 0x105, 219, 649, -1, 27, 1, 53 },
+ { 0x107, 0x107, 219, 650, -1, 27, 1, 53 },
+ { 0x103, 0x103, 219, 651, -1, 27, 1, 53 },
+ { 0x1, 0x1, 219, 652, -1, 35, 1, 28 },
+ { 0x1, 0x1, 219, 653, -1, 35, 1, 39 },
+ { 0x3, 0x3, 220, -1, -1, 34, 1, 34 },
+ { 0x3, 0x3, 220, -1, -1, 34, 1, 67 },
+ { 0x3, 0x3, 220, -1, -1, 34, 1, 49 },
+ { 0x3, 0x3, 220, -1, -1, 34, 1, 45 },
+ { 0xc00001, 0xc00001, 220, -1, -1, 12, 1, 64 },
+ { 0x3, 0x3, 220, 720, -1, 34, 1, 59 },
+ { 0xe00001, 0xe00001, 220, -1, -1, 12, 1, 64 },
+ { 0x7, 0x7, 220, 721, -1, 33, 1, 59 },
+ { 0x1c00001, 0x1c00001, 220, -1, -1, 12, 1, 64 },
+ { 0x7, 0x7, 220, 722, -1, 34, 1, 59 },
+ { 0x1e00001, 0x1e00001, 220, -1, -1, 12, 1, 54 },
+ { 0xf, 0xf, 220, 723, -1, 33, 1, 54 },
+ { 0xe00001, 0x1e00001, 220, -1, -1, 12, 1, 64 },
+ { 0x7, 0xf, 220, 726, -1, 33, 1, 59 },
+ { 0xc1, 0xc1, 220, -1, -1, 28, 1, 34 },
+ { 0x3, 0x3, 220, 713, -1, 34, 1, 34 },
+ { 0x183, 0x183, 220, -1, -1, 27, 1, 34 },
+ { 0x181, 0x181, 220, 714, -1, 27, 1, 34 },
+ { 0xb, 0xb, 220, -1, -1, 34, 1, 34 },
+ { 0x7, 0x7, 220, -1, -1, 34, 1, 67 },
+ { 0x3, 0x3, 220, -1, -1, 34, 1, 54 },
+ { 0xc1, 0xc1, 220, -1, -1, 28, 1, 54 },
+ { 0x181, 0x181, 220, -1, -1, 27, 1, 54 },
+ { 0x61, 0x61, 220, -1, -1, 29, 1, 54 },
+ { 0xc3, 0xc3, 220, -1, -1, 28, 1, 54 },
+ { 0x185, 0x185, 220, -1, -1, 27, 1, 54 },
+ { 0x187, 0x187, 220, -1, -1, 27, 1, 54 },
+ { 0x183, 0x183, 220, -1, -1, 27, 1, 54 },
+ { 0x3, 0x3, 220, -1, -1, 34, 1, 29 },
+ { 0x3, 0x3, 220, -1, -1, 34, 1, 40 },
+ { 0x3, 0x3, 221, -1, 437, 32, 1, 129 },
+ { 0x3, 0x3, 221, -1, 444, 32, 1, 140 },
+ { 0x1, 0x1, 222, -1, -1, 28, 1, 35 },
+ { 0x0, 0x0, 229, -1, -1, 0, 1, 136 },
+ { 0x0, 0x0, 229, -1, -1, 0, 1, 146 },
+ { 0x1, 0x1, 230, -1, 475, 33, 1, 133 },
+ { 0x0, 0x0, 230, -1, 473, 0, 1, 132 },
+ { 0x0, 0x0, 231, 683, 233, 0, 0, -1 },
+ { 0x0, 0x0, 231, 684, 236, 0, 0, -1 },
+ { 0x1, 0x1, 231, 685, 122, 33, 1, 8 },
+ { 0x8000001, 0x8000001, 231, 686, 124, 6, 1, 9 },
+ { 0x0, 0x0, 231, 687, 240, 0, 0, -1 },
+ { 0x1, 0x1, 231, 688, 125, 33, 1, 10 },
+ { 0x0, 0x0, 231, 689, 244, 0, 0, -1 },
+ { 0x1, 0x1, 231, 690, 126, 33, 1, 17 },
+ { 0x0, 0x0, 231, 691, 249, 0, 0, -1 },
+ { 0x1, 0x1, 231, 692, 127, 33, 1, 19 },
+ { 0x0, 0x0, 231, 693, 252, 0, 0, -1 },
+ { 0x0, 0x0, 231, 694, 256, 0, 0, -1 },
+ { 0x1, 0x1, 231, 695, 129, 33, 1, 20 },
+ { 0x8000001, 0x8000001, 231, 696, 129, 6, 1, 20 },
+ { 0x0, 0x0, 231, 697, 260, 0, 0, -1 },
+ { 0x1, 0x1, 231, 698, 130, 33, 1, 21 },
+ { 0x0, 0x0, 231, 699, 264, 0, 0, -1 },
+ { 0x0, 0x0, 231, 700, 268, 0, 0, -1 },
+ { 0x1, 0x1, 231, 701, 131, 33, 1, 22 },
+ { 0x8000001, 0x8000001, 231, 702, 131, 6, 1, 22 },
+ { 0x0, 0x0, 231, 703, 272, 0, 0, -1 },
+ { 0x1, 0x1, 231, 704, 132, 33, 1, 23 },
+ { 0x0, 0x0, 232, -1, 230, 0, 0, -1 },
+ { 0x0, 0x0, 232, -1, 237, 0, 0, -1 },
+ { 0x0, 0x0, 232, -1, 122, 0, 1, 8 },
+ { 0x1, 0x1, 232, -1, 124, 6, 1, 9 },
+ { 0x0, 0x0, 232, -1, 241, 0, 0, -1 },
+ { 0x0, 0x0, 232, -1, 125, 0, 1, 10 },
+ { 0x0, 0x0, 232, -1, 245, 0, 0, -1 },
+ { 0x0, 0x0, 232, -1, 126, 0, 1, 17 },
+ { 0x0, 0x0, 232, -1, 246, 0, 0, -1 },
+ { 0x0, 0x0, 232, -1, 127, 0, 1, 19 },
+ { 0x0, 0x0, 232, -1, 253, 0, 0, -1 },
+ { 0x0, 0x0, 232, -1, 257, 0, 0, -1 },
+ { 0x0, 0x0, 232, -1, 129, 0, 1, 20 },
+ { 0x1, 0x1, 232, -1, 129, 6, 1, 20 },
+ { 0x0, 0x0, 232, -1, 261, 0, 0, -1 },
+ { 0x0, 0x0, 232, -1, 130, 0, 1, 21 },
+ { 0x0, 0x0, 232, -1, 265, 0, 0, -1 },
+ { 0x0, 0x0, 232, -1, 269, 0, 0, -1 },
+ { 0x0, 0x0, 232, -1, 131, 0, 1, 22 },
+ { 0x1, 0x1, 232, -1, 131, 6, 1, 22 },
+ { 0x0, 0x0, 232, -1, 273, 0, 0, -1 },
+ { 0x0, 0x0, 232, -1, 132, 0, 1, 23 },
+ { 0x1, 0x1, 232, -1, 316, 27, 1, 18 },
+ { 0x0, 0x0, 232, -1, 316, 0, 1, 18 },
+ { 0x0, 0x0, 232, -1, 317, 0, 1, 24 },
+ { 0x0, 0x1, 232, -1, 318, 20, 1, 69 },
+ { 0x0, 0x0, 232, -1, 318, 0, 1, 69 },
+ { 0x1, 0x1, 235, 731, -1, 29, 1, 0 },
+ { 0x0, 0x0, 235, -1, -1, 0, 1, 0 },
+ { 0x1, 0x1, 235, 732, -1, 27, 1, 0 },
+ { 0x0, 0x0, 256, -1, 547, 0, 0, -1 },
+ { 0x0, 0x0, 256, -1, 549, 0, 0, -1 },
+ { 0x1, 0x1, 256, -1, -1, 28, 1, 31 },
+ { 0x0, 0x0, 258, -1, -1, 0, 1, 0 },
+ { 0x0, 0x1, 258, -1, -1, 29, 1, 0 },
+ { 0x1, 0x1, 259, -1, -1, 12, 1, 4 },
+ { 0x1, 0x1, 259, -1, -1, 12, 1, 66 },
+ { 0x0, 0x0, 259, -1, 537, 0, 0, -1 },
+ { 0x0, 0x0, 259, -1, 539, 0, 0, -1 },
+ { 0x0, 0x0, 259, -1, 541, 0, 0, -1 },
+ { 0x0, 0x0, 259, -1, 543, 0, 0, -1 },
+ { 0x1, 0x1, 259, -1, -1, 12, 1, 61 },
+ { 0x1, 0x1, 259, -1, -1, 12, 1, 51 },
+ { 0x0, 0x0, 259, -1, 545, 0, 0, -1 },
+ { 0x0, 0x0, 260, -1, 544, 0, 0, -1 },
+ { 0x9, 0x9, 260, -1, 725, 33, 1, 51 },
+ { 0x0, 0x0, 260, -1, 561, 0, 0, -1 },
+ { 0x3, 0x3, 260, -1, -1, 27, 1, 51 },
+ { 0x0, 0x0, 264, -1, -1, 0, 1, 0 },
+ { 0x3, 0x3, 265, 733, -1, 27, 1, 0 },
+ { 0x1, 0x1, 266, -1, -1, 28, 1, 0 },
+ { 0x1, 0x1, 267, -1, -1, 27, 1, 95 },
+ { 0x0, 0x0, 267, -1, 229, 0, 0, -1 },
+ { 0x0, 0x0, 268, 738, 165, 0, 0, -1 },
+ { 0x0, 0x0, 268, 739, 167, 0, 0, -1 },
+ { 0x0, 0x0, 269, -1, 166, 0, 0, -1 },
+ { 0x0, 0x0, 269, -1, 168, 0, 0, -1 },
+ { 0x0, 0x0, 270, -1, -1, 0, 1, 42 },
+ { 0x0, 0x0, 275, -1, -1, 0, 1, 35 },
+ { 0x0, 0x0, 279, -1, 142, 0, 1, 31 },
+ { 0x0, 0x0, 280, -1, -1, 0, 1, 73 },
+ { 0x0, 0x0, 280, -1, 97, 0, 1, 3 },
+ { 0x0, 0x0, 280, -1, 99, 0, 0, -1 },
+};
+
+static const struct ia64_main_table
+main_table[] = {
+ { 5, 1, 1, 0x10000000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+ { 5, 1, 1, 0x10008000000ull, 0x1eff8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 0, },
+ { 5, 7, 1, 0x0ull, 0x0ull, { 23, 65, 25, 0, 0 }, 0x0, 0, },
+ { 6, 1, 1, 0x12000000000ull, 0x1e000000000ull, { 23, 65, 26, 0, 0 }, 0x0, 1, },
+ { 7, 1, 1, 0x10040000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+ { 7, 1, 1, 0x10c00000000ull, 0x1ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 0, },
+ { 8, 1, 1, 0x10800000000ull, 0x1ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 1, },
+ { 9, 3, 1, 0x2c00000000ull, 0x1ee00000000ull, { 23, 2, 51, 52, 53 }, 0x221, 2, },
+ { 10, 1, 1, 0x10060000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+ { 10, 1, 1, 0x10160000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, },
+ { 11, 1, 1, 0x10068000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+ { 11, 1, 1, 0x10168000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, },
+ { 14, 4, 0, 0x100000000ull, 0x1eff80011ffull, { 15, 0, 0, 0, 0 }, 0x40, 3, },
+ { 14, 4, 0, 0x100000000ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x0, 136, },
+ { 14, 4, 0, 0x100000000ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x40, 137, },
+ { 14, 4, 0, 0x108000100ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x200, 514, },
+ { 14, 4, 0, 0x108000100ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x240, 515, },
+ { 14, 4, 1, 0x2000000000ull, 0x1ee00001000ull, { 14, 15, 0, 0, 0 }, 0x0, 114, },
+ { 14, 4, 1, 0x2000000000ull, 0x1ee00001000ull, { 14, 15, 0, 0, 0 }, 0x40, 115, },
+ { 14, 4, 0, 0x8000000000ull, 0x1ee000011ffull, { 80, 0, 0, 0, 0 }, 0x40, 4, },
+ { 14, 4, 0, 0x8000000000ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x0, 138, },
+ { 14, 4, 0, 0x8000000000ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x40, 139, },
+ { 14, 4, 0, 0x8000000080ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x210, 736, },
+ { 14, 4, 0, 0x8000000080ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x250, 737, },
+ { 14, 4, 0, 0x8000000140ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x30, 120, },
+ { 14, 4, 0, 0x8000000140ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x70, 121, },
+ { 14, 4, 0, 0x8000000180ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x230, 118, },
+ { 14, 4, 0, 0x8000000180ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x270, 119, },
+ { 14, 4, 1, 0xa000000000ull, 0x1ee00001000ull, { 14, 80, 0, 0, 0 }, 0x0, 116, },
+ { 14, 4, 1, 0xa000000000ull, 0x1ee00001000ull, { 14, 80, 0, 0, 0 }, 0x40, 117, },
+ { 15, 4, 0, 0x0ull, 0x1e1f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 108, },
+ { 15, 5, 0, 0x0ull, 0x1e3f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 224, },
+ { 15, 2, 0, 0x0ull, 0x1eff8000000ull, { 64, 0, 0, 0, 0 }, 0x2, 306, },
+ { 15, 3, 0, 0x0ull, 0x1eff8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 355, },
+ { 15, 6, 0, 0x0ull, 0x1eff8000000ull, { 68, 0, 0, 0, 0 }, 0x0, 740, },
+ { 15, 7, 0, 0x0ull, 0x0ull, { 64, 0, 0, 0, 0 }, 0x0, 5, },
+ { 16, 6, 0, 0x18000000000ull, 0x1ee000011ffull, { 81, 0, 0, 0, 0 }, 0x40, 4, },
+ { 16, 6, 0, 0x18000000000ull, 0x1ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x0, 138, },
+ { 16, 6, 0, 0x18000000000ull, 0x1ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x40, 139, },
+ { 16, 6, 1, 0x1a000000000ull, 0x1ee00001000ull, { 14, 81, 0, 0, 0 }, 0x0, 116, },
+ { 16, 6, 1, 0x1a000000000ull, 0x1ee00001000ull, { 14, 81, 0, 0, 0 }, 0x40, 117, },
+ { 17, 4, 0, 0x4080000000ull, 0x1e9f8000018ull, { 15, 76, 0, 0, 0 }, 0x20, 202, },
+ { 17, 4, 0, 0xe000000000ull, 0x1e800000018ull, { 80, 76, 0, 0, 0 }, 0x20, 203, },
+ { 18, 4, 0, 0x60000000ull, 0x1e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x2c, 75, },
+ { 22, 2, 0, 0x200000000ull, 0x1ee00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 519, },
+ { 22, 3, 0, 0x800000000ull, 0x1ee00000000ull, { 23, 80, 0, 0, 0 }, 0x0, 77, },
+ { 22, 3, 0, 0xc00000000ull, 0x1ee00000000ull, { 17, 80, 0, 0, 0 }, 0x0, 77, },
+ { 22, 3, 0, 0x2200000000ull, 0x1ee00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 520, },
+ { 22, 3, 0, 0x2600000000ull, 0x1ee00000000ull, { 18, 79, 0, 0, 0 }, 0x0, 521, },
+ { 22, 7, 0, 0x0ull, 0x0ull, { 24, 79, 0, 0, 0 }, 0x0, 522, },
+ { 25, 4, 0, 0x20000000ull, 0x1e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 6, },
+ { 26, 1, 2, 0x18000000000ull, 0x1fe00001000ull, { 21, 22, 24, 25, 0 }, 0x0, 208, },
+ { 26, 1, 2, 0x18000000000ull, 0x1fe00001000ull, { 22, 21, 25, 24, 0 }, 0x0, 329, },
+ { 26, 1, 2, 0x18000000000ull, 0x1fe00001000ull, { 21, 22, 25, 24, 0 }, 0x0, 291, },
+ { 26, 1, 2, 0x18000000000ull, 0x1fe00001000ull, { 22, 21, 24, 25, 0 }, 0x0, 282, },
+ { 26, 1, 2, 0x18200000000ull, 0x1fe00001000ull, { 21, 22, 24, 25, 0 }, 0x40, 209, },
+ { 26, 1, 2, 0x19000000000ull, 0x1fe00001000ull, { 21, 22, 6, 25, 0 }, 0x0, 283, },
+ { 26, 1, 2, 0x19000000000ull, 0x1fe00001000ull, { 21, 22, 6, 25, 0 }, 0x40, 284, },
+ { 26, 1, 2, 0x18800000000ull, 0x1ee00001000ull, { 21, 22, 54, 25, 0 }, 0x0, 208, },
+ { 26, 1, 2, 0x18800000000ull, 0x1ee00001000ull, { 21, 22, 56, 25, 0 }, 0x0, 332, },
+ { 26, 1, 2, 0x18800000000ull, 0x1ee00001000ull, { 22, 21, 56, 25, 0 }, 0x0, 294, },
+ { 26, 1, 2, 0x18800000000ull, 0x1ee00001000ull, { 22, 21, 54, 25, 0 }, 0x0, 282, },
+ { 26, 1, 2, 0x18a00000000ull, 0x1ee00001000ull, { 21, 22, 54, 25, 0 }, 0x40, 209, },
+ { 26, 1, 2, 0x1a800000000ull, 0x1ee00001000ull, { 21, 22, 58, 25, 0 }, 0x0, 339, },
+ { 26, 1, 2, 0x1a800000000ull, 0x1ee00001000ull, { 22, 21, 58, 25, 0 }, 0x0, 300, },
+ { 26, 1, 2, 0x1c200000000ull, 0x1fe00001000ull, { 22, 21, 24, 25, 0 }, 0x40, 210, },
+ { 26, 1, 2, 0x1d000000000ull, 0x1fe00001000ull, { 22, 21, 6, 25, 0 }, 0x40, 285, },
+ { 26, 1, 2, 0x1ca00000000ull, 0x1ee00001000ull, { 22, 21, 54, 25, 0 }, 0x40, 210, },
+ { 27, 1, 2, 0x18400000000ull, 0x1fe00001000ull, { 21, 22, 24, 25, 0 }, 0x0, 208, },
+ { 27, 1, 2, 0x18400000000ull, 0x1fe00001000ull, { 22, 21, 25, 24, 0 }, 0x0, 329, },
+ { 27, 1, 2, 0x18400000000ull, 0x1fe00001000ull, { 21, 22, 25, 24, 0 }, 0x0, 291, },
+ { 27, 1, 2, 0x18400000000ull, 0x1fe00001000ull, { 22, 21, 24, 25, 0 }, 0x0, 282, },
+ { 27, 1, 2, 0x18600000000ull, 0x1fe00001000ull, { 21, 22, 24, 25, 0 }, 0x40, 209, },
+ { 27, 1, 2, 0x19400000000ull, 0x1fe00001000ull, { 21, 22, 6, 25, 0 }, 0x0, 283, },
+ { 27, 1, 2, 0x19400000000ull, 0x1fe00001000ull, { 21, 22, 6, 25, 0 }, 0x40, 284, },
+ { 27, 1, 2, 0x18c00000000ull, 0x1ee00001000ull, { 21, 22, 54, 25, 0 }, 0x0, 211, },
+ { 27, 1, 2, 0x18c00000000ull, 0x1ee00001000ull, { 21, 22, 56, 25, 0 }, 0x0, 332, },
+ { 27, 1, 2, 0x18c00000000ull, 0x1ee00001000ull, { 22, 21, 56, 25, 0 }, 0x0, 294, },
+ { 27, 1, 2, 0x18c00000000ull, 0x1ee00001000ull, { 22, 21, 54, 25, 0 }, 0x0, 286, },
+ { 27, 1, 2, 0x18e00000000ull, 0x1ee00001000ull, { 21, 22, 54, 25, 0 }, 0x40, 209, },
+ { 27, 1, 2, 0x1ac00000000ull, 0x1ee00001000ull, { 21, 22, 55, 25, 0 }, 0x0, 352, },
+ { 27, 1, 2, 0x1ac00000000ull, 0x1ee00001000ull, { 21, 22, 57, 25, 0 }, 0x0, 339, },
+ { 27, 1, 2, 0x1ac00000000ull, 0x1ee00001000ull, { 22, 21, 57, 25, 0 }, 0x0, 300, },
+ { 27, 1, 2, 0x1ac00000000ull, 0x1ee00001000ull, { 22, 21, 55, 25, 0 }, 0x0, 290, },
+ { 27, 1, 2, 0x1c600000000ull, 0x1fe00001000ull, { 22, 21, 24, 25, 0 }, 0x40, 210, },
+ { 27, 1, 2, 0x1d400000000ull, 0x1fe00001000ull, { 22, 21, 6, 25, 0 }, 0x40, 285, },
+ { 27, 1, 2, 0x1ce00000000ull, 0x1ee00001000ull, { 22, 21, 54, 25, 0 }, 0x40, 210, },
+ { 28, 3, 1, 0x8008000000ull, 0x1fff8000000ull, { 23, 32, 24, 1, 0 }, 0x0, 82, },
+ { 29, 3, 1, 0x8048000000ull, 0x1fff8000000ull, { 23, 32, 24, 1, 0 }, 0x0, 82, },
+ { 30, 3, 1, 0x8088000000ull, 0x1fff8000000ull, { 23, 32, 24, 1, 0 }, 0x0, 82, },
+ { 31, 3, 1, 0x80c8000000ull, 0x1fff8000000ull, { 23, 32, 24, 1, 0 }, 0x0, 82, },
+ { 33, 4, 0, 0x10000000ull, 0x1e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 7, },
+ { 35, 2, 1, 0xc0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 321, },
+ { 36, 2, 1, 0xc8000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 321, },
+ { 38, 2, 1, 0x8000000000ull, 0x1e000000000ull, { 23, 24, 25, 46, 71 }, 0x0, 8, },
+ { 38, 2, 1, 0xa600000000ull, 0x1ee04000000ull, { 23, 24, 44, 72, 0 }, 0x0, 743, },
+ { 38, 2, 1, 0xa604000000ull, 0x1ee04000000ull, { 23, 54, 44, 72, 0 }, 0x0, 743, },
+ { 38, 2, 1, 0xae00000000ull, 0x1ee00000000ull, { 23, 47, 25, 45, 72 }, 0x0, 8, },
+ { 42, 4, 0, 0x80000000ull, 0x1e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x20, 9, },
+ { 47, 2, 1, 0xa400000000ull, 0x1ee00002000ull, { 23, 25, 75, 72, 0 }, 0x0, 10, },
+ { 49, 5, 1, 0x80000000ull, 0x1e3f80fe000ull, { 17, 19, 0, 0, 0 }, 0x40, 11, },
+ { 50, 5, 1, 0x10008000000ull, 0x1fff8000000ull, { 17, 19, 18, 0, 0 }, 0x40, 12, },
+ { 51, 5, 1, 0xb8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+ { 51, 5, 1, 0xb8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+ { 52, 5, 1, 0xb0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+ { 52, 5, 1, 0xb0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+ { 53, 5, 1, 0x160000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 11, },
+ { 54, 5, 1, 0x168000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 11, },
+ { 56, 3, 0, 0x2180000000ull, 0x1eff8000000ull, { 25, 0, 0, 0, 0 }, 0x0, 14, },
+ { 57, 5, 0, 0x40000000ull, 0x1eff8000000ull, { 78, 0, 0, 0, 0 }, 0x0, 535, },
+ { 57, 5, 0, 0x40000000ull, 0x1eff8000000ull, { 78, 0, 0, 0, 0 }, 0x40, 15, },
+ { 58, 5, 2, 0xa000000000ull, 0x1e000001000ull, { 21, 22, 18, 59, 0 }, 0x0, 357, },
+ { 58, 5, 2, 0xa000000000ull, 0x1e000001000ull, { 22, 21, 18, 59, 0 }, 0x40, 428, },
+ { 59, 5, 0, 0x28000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 536, },
+ { 59, 5, 0, 0x28000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x40, 16, },
+ { 60, 5, 2, 0x8000000000ull, 0x1fe00001000ull, { 21, 22, 18, 19, 0 }, 0x0, 212, },
+ { 60, 5, 2, 0x8000000000ull, 0x1fe00001000ull, { 21, 22, 18, 19, 0 }, 0x40, 213, },
+ { 60, 5, 2, 0x9000000000ull, 0x1fe00001000ull, { 21, 22, 19, 18, 0 }, 0x0, 287, },
+ { 60, 5, 2, 0x9000000000ull, 0x1fe00001000ull, { 21, 22, 19, 18, 0 }, 0x40, 288, },
+ { 60, 5, 2, 0x8000000000ull, 0x1fe00001000ull, { 22, 21, 18, 19, 0 }, 0x0, 411, },
+ { 60, 5, 2, 0x8000000000ull, 0x1fe00001000ull, { 22, 21, 18, 19, 0 }, 0x40, 412, },
+ { 60, 5, 2, 0x9000000000ull, 0x1fe00001000ull, { 22, 21, 19, 18, 0 }, 0x0, 415, },
+ { 60, 5, 2, 0x9000000000ull, 0x1fe00001000ull, { 22, 21, 19, 18, 0 }, 0x40, 416, },
+ { 61, 5, 1, 0xc0000000ull, 0x1eff8000000ull, { 17, 18, 0, 0, 0 }, 0x0, 276, },
+ { 61, 5, 1, 0xc0000000ull, 0x1eff8000000ull, { 17, 18, 0, 0, 0 }, 0x40, 277, },
+ { 61, 5, 1, 0xe0000000ull, 0x1e3f8000000ull, { 17, 18, 0, 0, 0 }, 0x0, 741, },
+ { 61, 5, 1, 0x10008000000ull, 0x1fff80fe000ull, { 17, 19, 0, 0, 0 }, 0x40, 742, },
+ { 62, 3, 1, 0x8488000000ull, 0x1fff8000000ull, { 23, 32, 70, 0, 0 }, 0x0, 83, },
+ { 63, 3, 1, 0x84c8000000ull, 0x1fff8000000ull, { 23, 32, 70, 0, 0 }, 0x0, 83, },
+ { 66, 3, 0, 0x60000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x21, 17, },
+ { 67, 5, 1, 0x10000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 143, },
+ { 67, 5, 1, 0x10000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 18, },
+ { 68, 5, 1, 0xa8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+ { 68, 5, 1, 0xa8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+ { 69, 5, 1, 0x80000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 430, },
+ { 70, 5, 1, 0xa0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+ { 70, 5, 1, 0xa0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+ { 71, 5, 1, 0x1c8000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 322, },
+ { 72, 5, 1, 0x10000000000ull, 0x1fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 12, },
+ { 73, 5, 1, 0x14000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 145, },
+ { 73, 5, 1, 0x14000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 19, },
+ { 74, 5, 1, 0x88000000ull, 0x1e3f8000000ull, { 17, 19, 0, 0, 0 }, 0xc0, 11, },
+ { 75, 5, 1, 0x88000000ull, 0x1e3f80fe000ull, { 17, 19, 0, 0, 0 }, 0x40, 11, },
+ { 76, 5, 1, 0x18000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 145, },
+ { 76, 5, 1, 0x18000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 19, },
+ { 77, 5, 1, 0x18000000000ull, 0x1fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 12, },
+ { 78, 5, 1, 0x10008000000ull, 0x1fff80fe000ull, { 17, 19, 0, 0, 0 }, 0x40, 12, },
+ { 79, 5, 1, 0x170000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 11, },
+ { 80, 5, 1, 0x2080000000ull, 0x1e3f80fe000ull, { 17, 19, 0, 0, 0 }, 0x40, 11, },
+ { 81, 5, 1, 0x140000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 11, },
+ { 82, 5, 1, 0x20b8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+ { 82, 5, 1, 0x20b8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+ { 83, 5, 1, 0x20b0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+ { 83, 5, 1, 0x20b0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+ { 84, 5, 1, 0x2180000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 214, },
+ { 84, 5, 1, 0x2180000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 215, },
+ { 85, 5, 1, 0x20c0000000ull, 0x1eff8000000ull, { 17, 18, 0, 0, 0 }, 0x0, 276, },
+ { 85, 5, 1, 0x20c0000000ull, 0x1eff8000000ull, { 17, 18, 0, 0, 0 }, 0x40, 277, },
+ { 86, 5, 1, 0x13000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 533, },
+ { 86, 5, 1, 0x13000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 13, },
+ { 87, 5, 1, 0x20a8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+ { 87, 5, 1, 0x20a8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+ { 88, 5, 1, 0x2080000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 430, },
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+ { 241, 3, 1, 0xcc40000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 69, },
+ { 241, 3, 1, 0xec40000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 69, },
+ { 242, 3, 1, 0xccc0000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 69, },
+ { 242, 3, 1, 0xecc0000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 69, },
+ { 243, 3, 1, 0xcc00000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 69, },
+ { 243, 3, 1, 0xec00000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 69, },
+ { 244, 3, 1, 0xcc80000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 69, },
+ { 244, 3, 1, 0xec80000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 69, },
+ { 245, 1, 1, 0x10028000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+ { 245, 1, 1, 0x10020000000ull, 0x1eff8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 0, },
+ { 245, 1, 1, 0x10128000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, },
+ { 246, 3, 0, 0x20000000ull, 0x1ee78000000ull, { 66, 0, 0, 0, 0 }, 0x0, 70, },
+ { 247, 2, 1, 0xa0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+ { 248, 2, 1, 0xa8000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+ { 249, 2, 1, 0xb0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+ { 250, 3, 0, 0x198000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 306, },
+ { 251, 3, 1, 0x20f8000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 71, },
+ { 252, 2, 2, 0xa000000000ull, 0x1fe00003000ull, { 21, 22, 25, 75, 0 }, 0x0, 477, },
+ { 252, 2, 2, 0xa000000000ull, 0x1fe00003000ull, { 22, 21, 25, 75, 0 }, 0x40, 478, },
+ { 253, 3, 1, 0x20d0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 72, },
+ { 254, 2, 2, 0xa000002000ull, 0x1fe00003000ull, { 21, 22, 25, 0, 0 }, 0x0, 477, },
+ { 254, 2, 2, 0xa000002000ull, 0x1fe00003000ull, { 22, 21, 25, 0, 0 }, 0x40, 478, },
+ { 255, 3, 1, 0x20f0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 71, },
+ { 257, 3, 1, 0x20d8000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 73, },
+ { 261, 2, 1, 0xe840000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 301, },
+ { 262, 2, 1, 0xea40000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 301, },
+ { 263, 2, 1, 0xf840000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 301, },
+ { 271, 3, 1, 0x8208000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 74, },
+ { 272, 3, 1, 0x8248000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 74, },
+ { 273, 3, 1, 0x8288000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 74, },
+ { 274, 3, 1, 0x82c8000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 74, },
+ { 276, 5, 1, 0x1d000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 302, },
+ { 276, 5, 1, 0x1d000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 353, },
+ { 277, 5, 1, 0x1d000000000ull, 0x1fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 303, },
+ { 278, 1, 1, 0x10078000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+ { 278, 1, 1, 0x10178000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, },
+ { 281, 2, 1, 0x80000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+ { 282, 2, 1, 0x88000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+ { 283, 2, 1, 0x90000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+};
+
+static const char dis_table[] = {
+0xa0, 0xc2, 0x60, 0xa0, 0x2c, 0x80, 0xa0, 0x2a, 0x80, 0xa0, 0x1a, 0x70,
+0x98, 0xb0, 0x01, 0x40, 0x90, 0x50, 0x90, 0x28, 0x24, 0x20, 0x28, 0x24,
+0x20, 0x20, 0x90, 0x28, 0x24, 0x20, 0x18, 0x24, 0x20, 0x10, 0x90, 0x50,
+0x90, 0x28, 0x24, 0x20, 0x00, 0x24, 0x1f, 0xf8, 0x90, 0x28, 0x24, 0x1f,
+0xf0, 0x24, 0x1f, 0xe8, 0xa8, 0x0b, 0x28, 0x15, 0x00, 0x97, 0x00, 0x95,
+0xa8, 0x9a, 0x98, 0x05, 0x18, 0x90, 0xf8, 0x90, 0x80, 0x90, 0x40, 0x80,
+0xa4, 0x06, 0x50, 0x37, 0x13, 0x80, 0xa4, 0x2d, 0x18, 0x33, 0xfa, 0x90,
+0x50, 0x90, 0x28, 0x80, 0x35, 0xac, 0x80, 0x31, 0x08, 0x81, 0x34, 0xec,
+0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x00, 0x00, 0x33, 0xdb, 0xa4,
+0x1e, 0xc0, 0x33, 0xd9, 0x90, 0x38, 0xa4, 0x26, 0xd0, 0x34, 0xcf, 0xa4,
+0x2d, 0xe0, 0x35, 0xb6, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x2e, 0xd0, 0x35,
+0xde, 0xa4, 0x28, 0xd8, 0x35, 0x23, 0x80, 0xa4, 0x2e, 0xc8, 0x35, 0xdd,
+0x92, 0x18, 0x91, 0xc0, 0x80, 0x91, 0x80, 0x90, 0xf8, 0xdb, 0x84, 0x60,
+0xf8, 0x80, 0xc0, 0xc0, 0x80, 0xa4, 0x40, 0x80, 0x8c, 0x41, 0x50, 0x84,
+0x38, 0x5a, 0xc0, 0xc0, 0x80, 0xa4, 0x40, 0x70, 0x8c, 0x41, 0x30, 0x84,
+0x38, 0x56, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x37, 0xf8, 0x50,
+0xc0, 0xc0, 0x81, 0x37, 0xf6, 0xa4, 0x08, 0x30, 0x31, 0x07, 0x80, 0x90,
+0x28, 0x80, 0x30, 0xe5, 0x80, 0x30, 0xe7, 0x81, 0x90, 0x38, 0xa4, 0x07,
+0x70, 0x30, 0xea, 0xa4, 0x07, 0x40, 0x30, 0xe6, 0xc0, 0x40, 0x10, 0x10,
+0x90, 0x38, 0xa4, 0x04, 0x30, 0x30, 0x3f, 0xa4, 0x04, 0x38, 0x30, 0x7b,
+0x18, 0x24, 0x34, 0xd0, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0,
+0x80, 0xa4, 0x40, 0xb0, 0x38, 0x36, 0xc0, 0xc0, 0x80, 0xa4, 0x40, 0xa0,
+0x38, 0x32, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x37, 0xfe, 0x50,
+0xc0, 0xc0, 0x81, 0x37, 0xfc, 0x92, 0xb8, 0x99, 0x84, 0x07, 0x60, 0x90,
+0x78, 0x90, 0x50, 0x10, 0x10, 0x80, 0xa4, 0x2d, 0x10, 0x33, 0xf9, 0x82,
+0x35, 0xab, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x26, 0xc8, 0x34,
+0xce, 0xa4, 0x2d, 0xd8, 0x35, 0xb5, 0x80, 0x90, 0x38, 0xa4, 0x28, 0xf8,
+0x35, 0x27, 0xa4, 0x28, 0xd0, 0x35, 0x22, 0x83, 0x90, 0xa8, 0xd3, 0x82,
+0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x40, 0xe0, 0x38, 0x42, 0xc0, 0xc0, 0x80,
+0xa4, 0x40, 0xd0, 0x38, 0x3e, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81,
+0x38, 0x04, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x02, 0x18, 0x24, 0x07, 0x68,
+0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x41, 0x10,
+0x38, 0x4e, 0xc0, 0xc0, 0x80, 0xa4, 0x41, 0x00, 0x38, 0x4a, 0xd3, 0x82,
+0x40, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x0a, 0x50, 0xc0, 0xc0, 0x81, 0x38,
+0x08, 0x94, 0x50, 0x92, 0xf8, 0x99, 0x84, 0x34, 0xc0, 0x90, 0x78, 0x90,
+0x50, 0x10, 0x10, 0x80, 0xa4, 0x2d, 0x08, 0x33, 0xf8, 0x82, 0x35, 0xaa,
+0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x26, 0xc0, 0x34, 0xcd, 0xa4,
+0x2d, 0xd0, 0x35, 0xb4, 0x80, 0x90, 0x38, 0xa4, 0x28, 0xf0, 0x35, 0x26,
+0xa4, 0x28, 0xc8, 0x35, 0x21, 0x83, 0x90, 0xe8, 0xd3, 0x83, 0xc0, 0xc0,
+0xc0, 0x80, 0xa4, 0x40, 0x90, 0x8c, 0x41, 0x70, 0x84, 0x38, 0x58, 0xc0,
+0xc0, 0x80, 0xa4, 0x40, 0x78, 0x8c, 0x41, 0x40, 0x84, 0x38, 0x57, 0xd3,
+0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x37, 0xfa, 0x50, 0xc0, 0xc0, 0x81,
+0x37, 0xf7, 0x18, 0x24, 0x34, 0xc8, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0,
+0xc0, 0xc0, 0x80, 0xa4, 0x40, 0xc0, 0x38, 0x3a, 0xc0, 0xc0, 0x80, 0xa4,
+0x40, 0xa8, 0x38, 0x34, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x38,
+0x00, 0x50, 0xc0, 0xc0, 0x81, 0x37, 0xfd, 0x92, 0xb8, 0x99, 0x84, 0x34,
+0xb0, 0x90, 0x78, 0x90, 0x50, 0x10, 0x10, 0x80, 0xa4, 0x2d, 0x00, 0x33,
+0xf7, 0x82, 0x35, 0xa9, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x26,
+0xb8, 0x34, 0xcc, 0xa4, 0x2d, 0xc8, 0x35, 0xb3, 0x80, 0x90, 0x38, 0xa4,
+0x28, 0xe8, 0x35, 0x25, 0xa4, 0x28, 0xc0, 0x35, 0x20, 0x83, 0x90, 0xa8,
+0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x40, 0xf0, 0x38, 0x46, 0xc0,
+0xc0, 0x80, 0xa4, 0x40, 0xd8, 0x38, 0x40, 0xd3, 0x82, 0x40, 0x50, 0xc0,
+0xc0, 0x81, 0x38, 0x06, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x03, 0x18, 0x20,
+0x01, 0x48, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4,
+0x41, 0x20, 0x38, 0x52, 0xc0, 0xc0, 0x80, 0xa4, 0x41, 0x08, 0x38, 0x4c,
+0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x0c, 0x50, 0xc0, 0xc0,
+0x81, 0x38, 0x09, 0xda, 0x06, 0xe1, 0xa5, 0xc0, 0x90, 0x60, 0x90, 0x38,
+0xa4, 0x07, 0xd8, 0x30, 0xf0, 0x80, 0x30, 0xf9, 0x90, 0x38, 0xa4, 0x07,
+0x90, 0x30, 0xf3, 0x80, 0x30, 0xf6, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x07,
+0xc0, 0x30, 0xf1, 0x80, 0x30, 0xfa, 0x90, 0x38, 0xa4, 0x07, 0xa8, 0x30,
+0xf4, 0x80, 0x30, 0xf7, 0xc8, 0x40, 0x18, 0x00, 0x91, 0x38, 0x90, 0x40,
+0x82, 0xa4, 0x06, 0x68, 0x37, 0x16, 0x90, 0xc0, 0x80, 0x90, 0x90, 0x90,
+0x48, 0xc9, 0xe1, 0x34, 0xc0, 0x85, 0x35, 0xce, 0xc9, 0xe1, 0x35, 0x40,
+0x85, 0x34, 0xaa, 0x80, 0x34, 0xd2, 0x10, 0x10, 0x81, 0x35, 0x17, 0x90,
+0xa8, 0x10, 0x10, 0x90, 0x28, 0x81, 0x34, 0x89, 0x90, 0x38, 0xa4, 0x2d,
+0x88, 0x35, 0xb2, 0xa4, 0x1f, 0x08, 0x34, 0x8b, 0x90, 0x70, 0x10, 0x10,
+0x90, 0x38, 0xa4, 0x1f, 0x30, 0x33, 0xe7, 0x80, 0x33, 0xe5, 0x90, 0x60,
+0x90, 0x28, 0x24, 0x26, 0x50, 0xa4, 0x26, 0x58, 0x34, 0xc9, 0x80, 0xa4,
+0x1f, 0x20, 0x33, 0xe3, 0x80, 0x90, 0xf8, 0x90, 0x90, 0x90, 0x50, 0x90,
+0x28, 0x80, 0x37, 0x17, 0x80, 0x35, 0xe1, 0x80, 0xa4, 0x34, 0x90, 0x36,
+0x93, 0x90, 0x28, 0x81, 0x30, 0x88, 0x80, 0xa4, 0x34, 0xd8, 0x36, 0x9c,
+0x83, 0x35, 0xd3, 0x98, 0xb0, 0x01, 0x40, 0x90, 0x50, 0x90, 0x28, 0x24,
+0x20, 0x78, 0x24, 0x20, 0x70, 0x90, 0x28, 0x24, 0x20, 0x68, 0x24, 0x20,
+0x60, 0x90, 0x50, 0x90, 0x28, 0x24, 0x20, 0x50, 0x24, 0x20, 0x48, 0x90,
+0x28, 0x24, 0x20, 0x40, 0x24, 0x20, 0x38, 0xa8, 0x08, 0xe0, 0x0d, 0xe0,
+0x96, 0x38, 0x95, 0xe8, 0x9b, 0x48, 0x05, 0xa8, 0x91, 0xa0, 0x90, 0xd0,
+0x90, 0x70, 0x90, 0x38, 0xa4, 0x06, 0xd8, 0x30, 0xdc, 0xa4, 0x06, 0xc8,
+0x30, 0xda, 0x90, 0x38, 0xa4, 0x06, 0xb8, 0x30, 0xd8, 0x80, 0x30, 0xd6,
+0x90, 0x60, 0x90, 0x28, 0x24, 0x04, 0x68, 0xa4, 0x04, 0x58, 0x30, 0x8c,
+0x90, 0x38, 0xa4, 0x04, 0x48, 0x30, 0x8a, 0xa4, 0x1e, 0xa0, 0x33, 0xd5,
+0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x06, 0xa0, 0x30, 0xd5, 0xa4,
+0x06, 0x90, 0x30, 0xd3, 0x90, 0x38, 0xa4, 0x21, 0x98, 0x34, 0x29, 0xa4,
+0x24, 0x30, 0x34, 0x80, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x22, 0x20, 0x34,
+0x50, 0xa4, 0x21, 0xf0, 0x34, 0x4a, 0x10, 0x10, 0xa4, 0x01, 0xf0, 0x30,
+0x1d, 0x91, 0x50, 0x90, 0x90, 0x90, 0x50, 0x90, 0x28, 0x24, 0x06, 0xe8,
+0x80, 0x30, 0xe3, 0x80, 0xa4, 0x06, 0xf0, 0x30, 0xe1, 0x90, 0x50, 0x90,
+0x28, 0x24, 0x06, 0xf8, 0x80, 0x30, 0xe4, 0x90, 0x38, 0xa4, 0x07, 0x00,
+0x30, 0xe2, 0xa4, 0x1e, 0xb0, 0x33, 0xd7, 0x90, 0xe0, 0x90, 0x70, 0x90,
+0x38, 0xa4, 0x23, 0x88, 0x35, 0xae, 0xa4, 0x22, 0xb0, 0x34, 0x77, 0x90,
+0x38, 0xa4, 0x23, 0x08, 0x34, 0x6b, 0xa4, 0x22, 0xe0, 0x34, 0x66, 0x81,
+0xa4, 0x05, 0x30, 0x30, 0xa7, 0xe4, 0xe1, 0xf7, 0x80, 0x37, 0xe0, 0xed,
+0x21, 0xf9, 0x21, 0xa5, 0x40, 0x37, 0xe6, 0x92, 0x40, 0x99, 0x18, 0x02,
+0x00, 0x10, 0x10, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x21, 0x90,
+0x34, 0x28, 0xa4, 0x24, 0x28, 0x34, 0x7f, 0x80, 0x90, 0x38, 0xa4, 0x22,
+0x18, 0x34, 0x4f, 0xa4, 0x21, 0xe8, 0x34, 0x49, 0x10, 0x10, 0x80, 0x90,
+0x70, 0x90, 0x38, 0xa4, 0x23, 0x80, 0x34, 0x7c, 0xa4, 0x22, 0xa8, 0x34,
+0x76, 0x90, 0x38, 0xa4, 0x23, 0x00, 0x34, 0x6a, 0xa4, 0x22, 0xd8, 0x34,
+0x65, 0xe4, 0xe1, 0xfa, 0x80, 0x37, 0xec, 0xed, 0x21, 0xfc, 0x21, 0xa5,
+0x00, 0x37, 0xf2, 0x92, 0x80, 0x92, 0x40, 0x99, 0x18, 0x02, 0x00, 0x10,
+0x10, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x21, 0x88, 0x34, 0x27,
+0xa4, 0x24, 0x20, 0x34, 0x7e, 0x80, 0x90, 0x38, 0xa4, 0x22, 0x10, 0x34,
+0x4e, 0xa4, 0x21, 0xe0, 0x34, 0x48, 0x10, 0x10, 0x80, 0x90, 0x70, 0x90,
+0x38, 0xa4, 0x23, 0x78, 0x34, 0x7b, 0xa4, 0x22, 0xa0, 0x34, 0x75, 0x90,
+0x38, 0xa4, 0x22, 0xf8, 0x34, 0x69, 0xa4, 0x22, 0xd0, 0x34, 0x64, 0xe4,
+0xe1, 0xf7, 0xc0, 0x37, 0xe2, 0xe5, 0x21, 0xf9, 0x40, 0x37, 0xe8, 0x92,
+0x50, 0x99, 0x18, 0x02, 0x00, 0x10, 0x10, 0x90, 0x80, 0x10, 0x10, 0x90,
+0x38, 0xa4, 0x21, 0x80, 0x34, 0x26, 0xa4, 0x24, 0x18, 0x34, 0x7d, 0x80,
+0x90, 0x38, 0xa4, 0x22, 0x08, 0x34, 0x4d, 0xa4, 0x21, 0xd8, 0x34, 0x47,
+0x10, 0x10, 0x80, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x23, 0x70, 0x34, 0x7a,
+0xa4, 0x22, 0x98, 0x34, 0x74, 0x90, 0x38, 0xa4, 0x22, 0xf0, 0x34, 0x68,
+0xa4, 0x22, 0xc8, 0x34, 0x63, 0xec, 0xe1, 0xfa, 0xe2, 0x18, 0x00, 0x37,
+0xee, 0xe5, 0x21, 0xfc, 0x40, 0x37, 0xf4, 0xc0, 0x40, 0x80, 0x10, 0x10,
+0x81, 0x90, 0x90, 0x90, 0x48, 0xc9, 0xe1, 0x0b, 0x40, 0x85, 0x34, 0x8a,
+0xc9, 0xe1, 0x0b, 0x80, 0x85, 0x34, 0x1b, 0x80, 0x34, 0x2c, 0x80, 0xd8,
+0x47, 0x80, 0x0d, 0xc0, 0xc0, 0x80, 0x10, 0x10, 0x82, 0x90, 0x58, 0xd5,
+0x81, 0x80, 0x80, 0x36, 0xa5, 0x80, 0x36, 0xab, 0xd5, 0x81, 0x80, 0x80,
+0x36, 0xa7, 0x80, 0x36, 0xa9, 0xc0, 0x80, 0x10, 0x10, 0x82, 0x90, 0x58,
+0xd5, 0x81, 0x80, 0x80, 0x36, 0xa6, 0x80, 0x36, 0xac, 0xd5, 0x81, 0x80,
+0x80, 0x36, 0xa8, 0x80, 0x36, 0xaa, 0xc0, 0x80, 0x84, 0x30, 0xce, 0xa0,
+0x56, 0x50, 0xa0, 0x40, 0x70, 0xa8, 0x1d, 0x40, 0x33, 0x18, 0xa0, 0x12,
+0x38, 0xa0, 0x0b, 0x48, 0x96, 0x00, 0x9a, 0xf0, 0x05, 0xc0, 0x91, 0x70,
+0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x2f, 0xb8, 0x33, 0xd3, 0xa4,
+0x2f, 0xc8, 0x33, 0xc0, 0x10, 0x10, 0xa4, 0x2f, 0xc0, 0x33, 0xbf, 0x90,
+0x70, 0x90, 0x38, 0xa4, 0x2f, 0x88, 0x33, 0x82, 0xa4, 0x2f, 0x98, 0x33,
+0x6f, 0x10, 0x10, 0xa4, 0x2f, 0x90, 0x33, 0x6e, 0x90, 0xb8, 0x90, 0x70,
+0x90, 0x38, 0xa4, 0x2f, 0x58, 0x33, 0x31, 0xa4, 0x2f, 0x68, 0x33, 0x1e,
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+0x81, 0x37, 0x05, 0xc0, 0xc0, 0x81, 0x37, 0x01, 0x91, 0x70, 0x90, 0xd8,
+0xd5, 0x03, 0x80, 0xc8, 0xe1, 0x92, 0x80, 0x81, 0x8c, 0x37, 0x28, 0x84,
+0x37, 0x0f, 0xc8, 0xe1, 0x93, 0x80, 0x81, 0x8c, 0x36, 0xf8, 0x84, 0x37,
+0x0e, 0xd5, 0x02, 0x80, 0xc8, 0xe1, 0x96, 0x00, 0x81, 0x36, 0xf1, 0xc8,
+0xe1, 0x92, 0x00, 0x81, 0x36, 0xeb, 0x90, 0x98, 0xd5, 0x02, 0x80, 0xc8,
+0xe1, 0x7f, 0x80, 0x81, 0x36, 0xfd, 0xc8, 0xe1, 0x80, 0x80, 0x81, 0x36,
+0xf7, 0xd5, 0x02, 0x80, 0xc8, 0xe1, 0x83, 0x00, 0x81, 0x37, 0x09, 0xc8,
+0xe1, 0x7f, 0x00, 0x81, 0x37, 0x03, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x90,
+0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x21, 0x9f, 0x00, 0x36, 0x78,
+0xe5, 0x21, 0x9c, 0x80, 0x36, 0x8c, 0xcb, 0x61, 0x2a, 0x00, 0x85, 0x34,
+0x97, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x21, 0x8c, 0x00, 0x36, 0x2c, 0xe5,
+0x21, 0x89, 0x80, 0x36, 0x40, 0xcb, 0x61, 0x29, 0xc0, 0x85, 0x34, 0x96,
+0x90, 0x48, 0xcb, 0xa1, 0x29, 0x80, 0x85, 0x34, 0x95, 0xcb, 0xa1, 0x29,
+0x40, 0x85, 0x34, 0x94, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80,
+0xe5, 0x21, 0x98, 0x00, 0x36, 0x66, 0xe5, 0x21, 0x96, 0x80, 0x36, 0x6c,
+0xcb, 0x61, 0x06, 0x40, 0x85, 0x34, 0x14, 0x98, 0x50, 0x00, 0x80, 0xe5,
+0x21, 0x85, 0x00, 0x36, 0x1a, 0xe5, 0x21, 0x83, 0x80, 0x36, 0x20, 0xcb,
+0x61, 0x06, 0x00, 0x85, 0x34, 0x13, 0x90, 0x48, 0xcb, 0xa1, 0x05, 0xc0,
+0x85, 0x34, 0x12, 0xcb, 0xa1, 0x05, 0x80, 0x85, 0x34, 0x11, 0x91, 0x00,
+0x90, 0x80, 0x90, 0x40, 0xe5, 0x21, 0xab, 0x40, 0x36, 0xb3, 0xe5, 0x21,
+0xae, 0xc0, 0x36, 0xbf, 0x90, 0x40, 0xe5, 0x21, 0xb1, 0x40, 0x36, 0xcb,
+0xe5, 0x21, 0xb4, 0xc0, 0x36, 0xd7, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x21,
+0xab, 0x80, 0x36, 0xb5, 0xe5, 0x21, 0xaf, 0x00, 0x36, 0xc1, 0x90, 0x40,
+0xe5, 0x21, 0xb1, 0x80, 0x36, 0xcd, 0xe5, 0x21, 0xb5, 0x00, 0x36, 0xd9,
+0x80, 0x99, 0x28, 0x02, 0xf0, 0x8c, 0x1f, 0xe0, 0x90, 0x80, 0x90, 0x40,
+0xe5, 0x21, 0xa2, 0x80, 0x36, 0x88, 0xe5, 0x21, 0x9d, 0x00, 0x36, 0x8e,
+0x90, 0x40, 0xe5, 0x21, 0x8f, 0x80, 0x36, 0x3c, 0xe5, 0x21, 0x8a, 0x00,
+0x36, 0x42, 0x91, 0x48, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x21,
+0x98, 0x80, 0x36, 0x68, 0xe5, 0x21, 0x97, 0x00, 0x36, 0x6e, 0xcb, 0x60,
+0x01, 0xc0, 0x85, 0x30, 0x03, 0x90, 0x40, 0xe5, 0x21, 0x85, 0x80, 0x36,
+0x1c, 0xe5, 0x21, 0x84, 0x00, 0x36, 0x22, 0x90, 0x48, 0xcb, 0xa0, 0x02,
+0x40, 0x85, 0x30, 0x05, 0xcb, 0xa0, 0x02, 0x80, 0x85, 0x30, 0x06, 0x10,
+0x10, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x21, 0x95, 0x00, 0x36, 0x52, 0xe5,
+0x21, 0x91, 0x80, 0x36, 0x56, 0x90, 0x40, 0xe5, 0x21, 0x82, 0x00, 0x36,
+0x06, 0xe5, 0x21, 0x7e, 0x80, 0x36, 0x0a,
+};
+
+static const struct ia64_dis_names ia64_dis_names[] = {
+{ 0x1, 389, 0 },
+{ 0x1, 387, 0 },
+{ 0x1, 386, 0 },
+{ 0x4, 385, 1 },
+{ 0x8, 385, 0 },
+{ 0x2, 385, 0 },
+{ 0x1, 385, 0 },
+{ 0x4, 383, 1 },
+{ 0x1, 384, 0 },
+{ 0x2, 383, 0 },
+{ 0x1, 383, 0 },
+{ 0x4, 382, 0 },
+{ 0x2, 382, 0 },
+{ 0x1, 382, 0 },
+{ 0x4, 381, 0 },
+{ 0x2, 381, 0 },
+{ 0x1, 381, 0 },
+{ 0x4, 380, 0 },
+{ 0x2, 380, 0 },
+{ 0x1, 380, 0 },
+{ 0x4, 379, 0 },
+{ 0x2, 379, 0 },
+{ 0x1, 379, 0 },
+{ 0x2, 378, 0 },
+{ 0x1, 378, 0 },
+{ 0x2, 377, 0 },
+{ 0x1, 377, 0 },
+{ 0x2, 376, 0 },
+{ 0x1, 376, 0 },
+{ 0x1, 374, 0 },
+{ 0x2, 372, 1 },
+{ 0x1, 373, 0 },
+{ 0x12, 372, 1 },
+{ 0x11, 373, 0 },
+{ 0xa, 372, 1 },
+{ 0x9, 373, 0 },
+{ 0x1a, 372, 1 },
+{ 0x7, 373, 0 },
+{ 0x6, 372, 1 },
+{ 0x5, 373, 0 },
+{ 0x5, 372, 1 },
+{ 0x12, 373, 0 },
+{ 0xd, 372, 1 },
+{ 0xe, 373, 0 },
+{ 0x3, 372, 1 },
+{ 0xa, 373, 0 },
+{ 0x2, 369, 1 },
+{ 0x1, 370, 0 },
+{ 0x12, 369, 1 },
+{ 0x11, 370, 0 },
+{ 0xa, 369, 1 },
+{ 0x9, 370, 0 },
+{ 0x1a, 369, 1 },
+{ 0x7, 370, 0 },
+{ 0x6, 369, 1 },
+{ 0x5, 370, 0 },
+{ 0x5, 369, 1 },
+{ 0x12, 370, 0 },
+{ 0xd, 369, 1 },
+{ 0xe, 370, 0 },
+{ 0x3, 369, 1 },
+{ 0xa, 370, 0 },
+{ 0x1, 368, 0 },
+{ 0x1, 363, 0 },
+{ 0x1, 362, 0 },
+{ 0x1, 361, 0 },
+{ 0x1, 360, 0 },
+{ 0x2, 359, 0 },
+{ 0x1, 359, 0 },
+{ 0x2, 358, 0 },
+{ 0x1, 358, 0 },
+{ 0x2, 357, 0 },
+{ 0x1, 357, 0 },
+{ 0x2, 356, 0 },
+{ 0x1, 356, 0 },
+{ 0x2, 355, 0 },
+{ 0x1, 355, 0 },
+{ 0x2, 354, 0 },
+{ 0x1, 354, 0 },
+{ 0x2, 353, 0 },
+{ 0x1, 353, 0 },
+{ 0x2, 352, 0 },
+{ 0x1, 352, 0 },
+{ 0x1, 351, 0 },
+{ 0x3, 351, 0 },
+{ 0x1, 350, 0 },
+{ 0x3, 350, 0 },
+{ 0x8, 349, 0 },
+{ 0x18, 349, 0 },
+{ 0x4, 349, 0 },
+{ 0xc, 349, 0 },
+{ 0x2, 349, 0 },
+{ 0x1, 349, 0 },
+{ 0x8, 348, 0 },
+{ 0x18, 348, 0 },
+{ 0x4, 348, 0 },
+{ 0xc, 348, 0 },
+{ 0x2, 348, 0 },
+{ 0x1, 348, 0 },
+{ 0x4, 347, 0 },
+{ 0xc, 347, 0 },
+{ 0x2, 347, 0 },
+{ 0x1, 347, 0 },
+{ 0x4, 346, 0 },
+{ 0xc, 346, 0 },
+{ 0x2, 346, 0 },
+{ 0x1, 346, 0 },
+{ 0x4, 345, 0 },
+{ 0xc, 345, 0 },
+{ 0x2, 345, 0 },
+{ 0x1, 345, 0 },
+{ 0x4, 344, 0 },
+{ 0xc, 344, 0 },
+{ 0x2, 344, 0 },
+{ 0x1, 344, 0 },
+{ 0x4, 343, 0 },
+{ 0xc, 343, 0 },
+{ 0x2, 343, 0 },
+{ 0x1, 343, 0 },
+{ 0x4, 342, 0 },
+{ 0xc, 342, 0 },
+{ 0x2, 342, 0 },
+{ 0x1, 342, 0 },
+{ 0x1, 341, 0 },
+{ 0x1, 339, 0 },
+{ 0x2, 338, 0 },
+{ 0x1, 338, 0 },
+{ 0x1, 336, 0 },
+{ 0x1, 335, 0 },
+{ 0x1, 334, 0 },
+{ 0x8, 332, 0 },
+{ 0x4, 332, 0 },
+{ 0x2, 332, 0 },
+{ 0x1, 332, 0 },
+{ 0x1, 331, 0 },
+{ 0x1, 330, 0 },
+{ 0x1, 329, 0 },
+{ 0x2, 328, 0 },
+{ 0x1, 328, 0 },
+{ 0x2, 326, 0 },
+{ 0x1, 326, 0 },
+{ 0x1, 325, 0 },
+{ 0x1, 324, 0 },
+{ 0x8, 323, 0 },
+{ 0x4, 323, 0 },
+{ 0x2, 323, 0 },
+{ 0x1, 323, 0 },
+{ 0x8, 322, 0 },
+{ 0x4, 322, 0 },
+{ 0x2, 322, 0 },
+{ 0x1, 322, 0 },
+{ 0x1, 321, 0 },
+{ 0x2, 320, 0 },
+{ 0x1, 320, 0 },
+{ 0x2, 319, 0 },
+{ 0x1, 319, 0 },
+{ 0x2, 318, 0 },
+{ 0x1, 318, 0 },
+{ 0x2, 317, 0 },
+{ 0x1, 317, 0 },
+{ 0x1, 316, 0 },
+{ 0x1, 315, 0 },
+{ 0x1, 314, 0 },
+{ 0x1, 313, 0 },
+{ 0x1, 312, 0 },
+{ 0x1, 311, 0 },
+{ 0x2, 308, 0 },
+{ 0x1, 308, 0 },
+{ 0x1, 307, 0 },
+{ 0x2, 306, 0 },
+{ 0x1, 306, 0 },
+{ 0x2, 305, 0 },
+{ 0x1, 305, 0 },
+{ 0x1, 304, 0 },
+{ 0x1, 303, 0 },
+{ 0x1, 302, 0 },
+{ 0x1, 301, 0 },
+{ 0x2, 300, 0 },
+{ 0x1, 300, 0 },
+{ 0x2, 299, 0 },
+{ 0x1, 299, 0 },
+{ 0x2, 298, 0 },
+{ 0x1, 298, 0 },
+{ 0x1, 297, 0 },
+{ 0x1, 296, 0 },
+{ 0x2, 295, 0 },
+{ 0x1, 295, 0 },
+{ 0x2, 294, 0 },
+{ 0x1, 294, 0 },
+{ 0x1, 293, 0 },
+{ 0x8, 292, 0 },
+{ 0x4, 292, 0 },
+{ 0x2, 292, 0 },
+{ 0x1, 292, 0 },
+{ 0x8, 291, 0 },
+{ 0x4, 291, 0 },
+{ 0x1, 291, 0 },
+{ 0x1, 290, 0 },
+{ 0x2, 289, 0 },
+{ 0x1, 289, 0 },
+{ 0x1, 288, 0 },
+{ 0x1, 287, 0 },
+{ 0x1, 283, 1 },
+{ 0x1, 284, 1 },
+{ 0x1, 285, 0 },
+{ 0x1, 282, 0 },
+{ 0x1, 281, 0 },
+{ 0x1, 280, 0 },
+{ 0x1, 279, 0 },
+{ 0x1, 278, 0 },
+{ 0x1, 270, 0 },
+{ 0x1, 269, 0 },
+{ 0x1, 268, 0 },
+{ 0x1, 267, 0 },
+{ 0x1, 266, 0 },
+{ 0x1, 265, 0 },
+{ 0x1, 264, 0 },
+{ 0x1, 263, 0 },
+{ 0x1, 262, 0 },
+{ 0x1, 261, 0 },
+{ 0x1, 260, 0 },
+{ 0x1, 259, 0 },
+{ 0x1, 258, 0 },
+{ 0x1, 257, 0 },
+{ 0x1, 256, 0 },
+{ 0x1, 255, 0 },
+{ 0x1, 254, 0 },
+{ 0x1, 253, 0 },
+{ 0x1, 252, 0 },
+{ 0x1, 251, 0 },
+{ 0x1, 250, 0 },
+{ 0x1, 248, 0 },
+{ 0x1, 247, 1 },
+{ 0x1, 367, 0 },
+{ 0x1, 246, 1 },
+{ 0x1, 340, 0 },
+{ 0x1, 245, 0 },
+{ 0x1, 244, 0 },
+{ 0x1, 243, 1 },
+{ 0x2, 340, 0 },
+{ 0x10, 242, 0 },
+{ 0x30, 242, 0 },
+{ 0x8, 242, 0 },
+{ 0x48, 242, 0 },
+{ 0xc8, 242, 0 },
+{ 0x28, 242, 0 },
+{ 0x18, 242, 0 },
+{ 0x38, 242, 0 },
+{ 0x4, 242, 0 },
+{ 0x2, 242, 0 },
+{ 0x6, 242, 0 },
+{ 0x1, 241, 1 },
+{ 0x1, 242, 0 },
+{ 0x1, 239, 0 },
+{ 0x1, 238, 0 },
+{ 0x1, 237, 0 },
+{ 0x2, 236, 0 },
+{ 0x1, 236, 0 },
+{ 0x2, 235, 0 },
+{ 0x1, 235, 0 },
+{ 0x2, 234, 0 },
+{ 0x1, 234, 0 },
+{ 0x2, 233, 0 },
+{ 0x1, 233, 0 },
+{ 0x1, 232, 1 },
+{ 0x1, 249, 0 },
+{ 0x20, 231, 0 },
+{ 0x10, 231, 0 },
+{ 0x8, 231, 0 },
+{ 0x4, 231, 0 },
+{ 0x44, 231, 0 },
+{ 0x24, 231, 0 },
+{ 0x14, 231, 0 },
+{ 0xc, 231, 0 },
+{ 0x4c, 231, 0 },
+{ 0x2c, 231, 0 },
+{ 0x1c, 231, 0 },
+{ 0x2, 231, 0 },
+{ 0x12, 231, 0 },
+{ 0xa, 231, 0 },
+{ 0x6, 231, 0 },
+{ 0x1, 231, 0 },
+{ 0x20, 230, 0 },
+{ 0x10, 230, 0 },
+{ 0x8, 230, 0 },
+{ 0x4, 230, 0 },
+{ 0x44, 230, 0 },
+{ 0x24, 230, 0 },
+{ 0x14, 230, 0 },
+{ 0xc, 230, 0 },
+{ 0x4c, 230, 0 },
+{ 0x2c, 230, 0 },
+{ 0x1c, 230, 0 },
+{ 0x2, 230, 0 },
+{ 0x12, 230, 0 },
+{ 0xa, 230, 0 },
+{ 0x6, 230, 0 },
+{ 0x1, 230, 0 },
+{ 0x20, 229, 0 },
+{ 0x10, 229, 0 },
+{ 0x8, 229, 0 },
+{ 0x4, 229, 0 },
+{ 0x44, 229, 0 },
+{ 0x24, 229, 0 },
+{ 0x14, 229, 0 },
+{ 0xc, 229, 0 },
+{ 0x4c, 229, 0 },
+{ 0x2c, 229, 0 },
+{ 0x1c, 229, 0 },
+{ 0x2, 229, 0 },
+{ 0x12, 229, 0 },
+{ 0xa, 229, 0 },
+{ 0x6, 229, 0 },
+{ 0x1, 229, 0 },
+{ 0x40, 228, 0 },
+{ 0x140, 228, 0 },
+{ 0xc0, 228, 0 },
+{ 0x20, 228, 0 },
+{ 0xa0, 228, 0 },
+{ 0x60, 228, 0 },
+{ 0x10, 228, 0 },
+{ 0x8, 228, 0 },
+{ 0x14, 228, 0 },
+{ 0x54, 228, 0 },
+{ 0x34, 228, 0 },
+{ 0xc, 228, 0 },
+{ 0x2c, 228, 0 },
+{ 0x1c, 228, 0 },
+{ 0x2, 228, 0 },
+{ 0xa, 228, 0 },
+{ 0x6, 228, 0 },
+{ 0x1, 228, 0 },
+{ 0x40, 227, 0 },
+{ 0x140, 227, 0 },
+{ 0xc0, 227, 0 },
+{ 0x20, 227, 0 },
+{ 0xa0, 227, 0 },
+{ 0x60, 227, 0 },
+{ 0x10, 227, 0 },
+{ 0x8, 227, 0 },
+{ 0x14, 227, 0 },
+{ 0x54, 227, 0 },
+{ 0x34, 227, 0 },
+{ 0xc, 227, 0 },
+{ 0x2c, 227, 0 },
+{ 0x1c, 227, 0 },
+{ 0x2, 227, 0 },
+{ 0xa, 227, 0 },
+{ 0x6, 227, 0 },
+{ 0x1, 227, 0 },
+{ 0x40, 226, 0 },
+{ 0x140, 226, 0 },
+{ 0xc0, 226, 0 },
+{ 0x20, 226, 0 },
+{ 0xa0, 226, 0 },
+{ 0x60, 226, 0 },
+{ 0x10, 226, 0 },
+{ 0x8, 226, 0 },
+{ 0x14, 226, 0 },
+{ 0x54, 226, 0 },
+{ 0x34, 226, 0 },
+{ 0xc, 226, 0 },
+{ 0x2c, 226, 0 },
+{ 0x1c, 226, 0 },
+{ 0x2, 226, 0 },
+{ 0xa, 226, 0 },
+{ 0x6, 226, 0 },
+{ 0x1, 226, 0 },
+{ 0x40, 225, 0 },
+{ 0x140, 225, 0 },
+{ 0xc0, 225, 0 },
+{ 0x20, 225, 0 },
+{ 0xa0, 225, 0 },
+{ 0x60, 225, 0 },
+{ 0x10, 225, 0 },
+{ 0x8, 225, 0 },
+{ 0x14, 225, 0 },
+{ 0x54, 225, 0 },
+{ 0x34, 225, 0 },
+{ 0xc, 225, 0 },
+{ 0x2c, 225, 0 },
+{ 0x1c, 225, 0 },
+{ 0x2, 225, 0 },
+{ 0xa, 225, 0 },
+{ 0x6, 225, 0 },
+{ 0x1, 225, 0 },
+{ 0x40, 224, 0 },
+{ 0x140, 224, 0 },
+{ 0xc0, 224, 0 },
+{ 0x20, 224, 0 },
+{ 0xa0, 224, 0 },
+{ 0x60, 224, 0 },
+{ 0x10, 224, 0 },
+{ 0x8, 224, 0 },
+{ 0x14, 224, 0 },
+{ 0x54, 224, 0 },
+{ 0x34, 224, 0 },
+{ 0xc, 224, 0 },
+{ 0x2c, 224, 0 },
+{ 0x1c, 224, 0 },
+{ 0x2, 224, 0 },
+{ 0xa, 224, 0 },
+{ 0x6, 224, 0 },
+{ 0x1, 224, 0 },
+{ 0x40, 223, 0 },
+{ 0x140, 223, 0 },
+{ 0xc0, 223, 0 },
+{ 0x20, 223, 0 },
+{ 0xa0, 223, 0 },
+{ 0x60, 223, 0 },
+{ 0x10, 223, 0 },
+{ 0x8, 223, 0 },
+{ 0x14, 223, 0 },
+{ 0x54, 223, 0 },
+{ 0x34, 223, 0 },
+{ 0xc, 223, 0 },
+{ 0x2c, 223, 0 },
+{ 0x1c, 223, 0 },
+{ 0x2, 223, 0 },
+{ 0xa, 223, 0 },
+{ 0x6, 223, 0 },
+{ 0x1, 223, 0 },
+{ 0x40, 222, 0 },
+{ 0x140, 222, 0 },
+{ 0xc0, 222, 0 },
+{ 0x20, 222, 0 },
+{ 0xa0, 222, 0 },
+{ 0x60, 222, 0 },
+{ 0x10, 222, 0 },
+{ 0x8, 222, 0 },
+{ 0x14, 222, 0 },
+{ 0x54, 222, 0 },
+{ 0x34, 222, 0 },
+{ 0xc, 222, 0 },
+{ 0x2c, 222, 0 },
+{ 0x1c, 222, 0 },
+{ 0x2, 222, 0 },
+{ 0xa, 222, 0 },
+{ 0x6, 222, 0 },
+{ 0x1, 222, 0 },
+{ 0x40, 221, 0 },
+{ 0x140, 221, 0 },
+{ 0xc0, 221, 0 },
+{ 0x20, 221, 0 },
+{ 0xa0, 221, 0 },
+{ 0x60, 221, 0 },
+{ 0x10, 221, 0 },
+{ 0x8, 221, 0 },
+{ 0x14, 221, 0 },
+{ 0x54, 221, 0 },
+{ 0x34, 221, 0 },
+{ 0xc, 221, 0 },
+{ 0x2c, 221, 0 },
+{ 0x1c, 221, 0 },
+{ 0x2, 221, 0 },
+{ 0xa, 221, 0 },
+{ 0x6, 221, 0 },
+{ 0x1, 221, 0 },
+{ 0x40, 220, 0 },
+{ 0x140, 220, 0 },
+{ 0xc0, 220, 0 },
+{ 0x20, 220, 0 },
+{ 0xa0, 220, 0 },
+{ 0x60, 220, 0 },
+{ 0x10, 220, 0 },
+{ 0x8, 220, 0 },
+{ 0x14, 220, 0 },
+{ 0x54, 220, 0 },
+{ 0x34, 220, 0 },
+{ 0xc, 220, 0 },
+{ 0x2c, 220, 0 },
+{ 0x1c, 220, 0 },
+{ 0x2, 220, 0 },
+{ 0xa, 220, 0 },
+{ 0x6, 220, 0 },
+{ 0x1, 220, 0 },
+{ 0x40, 219, 0 },
+{ 0x140, 219, 0 },
+{ 0xc0, 219, 0 },
+{ 0x20, 219, 0 },
+{ 0xa0, 219, 0 },
+{ 0x60, 219, 0 },
+{ 0x10, 219, 0 },
+{ 0x8, 219, 0 },
+{ 0x14, 219, 0 },
+{ 0x54, 219, 0 },
+{ 0x34, 219, 0 },
+{ 0xc, 219, 0 },
+{ 0x2c, 219, 0 },
+{ 0x1c, 219, 0 },
+{ 0x2, 219, 0 },
+{ 0xa, 219, 0 },
+{ 0x6, 219, 0 },
+{ 0x1, 219, 0 },
+{ 0x40, 218, 0 },
+{ 0x140, 218, 0 },
+{ 0xc0, 218, 0 },
+{ 0x20, 218, 0 },
+{ 0xa0, 218, 0 },
+{ 0x60, 218, 0 },
+{ 0x10, 218, 0 },
+{ 0x8, 218, 0 },
+{ 0x14, 218, 0 },
+{ 0x54, 218, 0 },
+{ 0x34, 218, 0 },
+{ 0xc, 218, 0 },
+{ 0x2c, 218, 0 },
+{ 0x1c, 218, 0 },
+{ 0x2, 218, 0 },
+{ 0xa, 218, 0 },
+{ 0x6, 218, 0 },
+{ 0x1, 218, 0 },
+{ 0x40, 217, 0 },
+{ 0x140, 217, 0 },
+{ 0xc0, 217, 0 },
+{ 0x20, 217, 0 },
+{ 0xa0, 217, 0 },
+{ 0x60, 217, 0 },
+{ 0x10, 217, 0 },
+{ 0x8, 217, 0 },
+{ 0x14, 217, 0 },
+{ 0x54, 217, 0 },
+{ 0x34, 217, 0 },
+{ 0xc, 217, 0 },
+{ 0x2c, 217, 0 },
+{ 0x1c, 217, 0 },
+{ 0x2, 217, 0 },
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+{ 0x31, 25, 0 },
+{ 0x29, 24, 0 },
+{ 0x69, 24, 0 },
+{ 0x19, 24, 1 },
+{ 0x9, 25, 0 },
+{ 0x39, 24, 1 },
+{ 0x19, 25, 0 },
+{ 0x15, 24, 0 },
+{ 0x35, 24, 0 },
+{ 0xd, 24, 1 },
+{ 0x5, 25, 0 },
+{ 0x1d, 24, 1 },
+{ 0xd, 25, 0 },
+{ 0xb, 24, 0 },
+{ 0x1b, 24, 0 },
+{ 0x7, 24, 1 },
+{ 0x3, 25, 0 },
+{ 0xf, 24, 1 },
+{ 0x7, 25, 0 },
+{ 0xa2, 22, 0 },
+{ 0x1a2, 22, 0 },
+{ 0x62, 22, 1 },
+{ 0x22, 23, 0 },
+{ 0xe2, 22, 1 },
+{ 0x62, 23, 0 },
+{ 0x52, 22, 0 },
+{ 0xd2, 22, 0 },
+{ 0x32, 22, 1 },
+{ 0x12, 23, 0 },
+{ 0x72, 22, 1 },
+{ 0x32, 23, 0 },
+{ 0x2a, 22, 0 },
+{ 0x6a, 22, 0 },
+{ 0x1a, 22, 1 },
+{ 0xa, 23, 0 },
+{ 0x3a, 22, 1 },
+{ 0x1a, 23, 0 },
+{ 0x16, 22, 0 },
+{ 0x36, 22, 0 },
+{ 0xe, 22, 1 },
+{ 0x6, 23, 0 },
+{ 0x1e, 22, 1 },
+{ 0xe, 23, 0 },
+{ 0x51, 22, 0 },
+{ 0xd1, 22, 0 },
+{ 0x31, 22, 1 },
+{ 0x11, 23, 0 },
+{ 0x71, 22, 1 },
+{ 0x31, 23, 0 },
+{ 0x29, 22, 0 },
+{ 0x69, 22, 0 },
+{ 0x19, 22, 1 },
+{ 0x9, 23, 0 },
+{ 0x39, 22, 1 },
+{ 0x19, 23, 0 },
+{ 0x15, 22, 0 },
+{ 0x35, 22, 0 },
+{ 0xd, 22, 1 },
+{ 0x5, 23, 0 },
+{ 0x1d, 22, 1 },
+{ 0xd, 23, 0 },
+{ 0xb, 22, 0 },
+{ 0x1b, 22, 0 },
+{ 0x7, 22, 1 },
+{ 0x3, 23, 0 },
+{ 0xf, 22, 1 },
+{ 0x7, 23, 0 },
+{ 0x51, 20, 1 },
+{ 0x50, 20, 0 },
+{ 0xd1, 20, 1 },
+{ 0xd0, 20, 0 },
+{ 0x31, 20, 1 },
+{ 0x30, 20, 1 },
+{ 0x11, 21, 1 },
+{ 0x10, 21, 0 },
+{ 0x71, 20, 1 },
+{ 0x70, 20, 1 },
+{ 0x31, 21, 1 },
+{ 0x30, 21, 0 },
+{ 0x29, 20, 1 },
+{ 0x28, 20, 0 },
+{ 0x69, 20, 1 },
+{ 0x68, 20, 0 },
+{ 0x19, 20, 1 },
+{ 0x18, 20, 1 },
+{ 0x9, 21, 1 },
+{ 0x8, 21, 0 },
+{ 0x39, 20, 1 },
+{ 0x38, 20, 1 },
+{ 0x19, 21, 1 },
+{ 0x18, 21, 0 },
+{ 0x15, 20, 1 },
+{ 0x14, 20, 0 },
+{ 0x35, 20, 1 },
+{ 0x34, 20, 0 },
+{ 0xd, 20, 1 },
+{ 0xc, 20, 1 },
+{ 0x5, 21, 1 },
+{ 0x4, 21, 0 },
+{ 0x1d, 20, 1 },
+{ 0x1c, 20, 1 },
+{ 0xd, 21, 1 },
+{ 0xc, 21, 0 },
+{ 0xb, 20, 1 },
+{ 0xa, 20, 0 },
+{ 0x1b, 20, 1 },
+{ 0x1a, 20, 0 },
+{ 0x7, 20, 1 },
+{ 0x6, 20, 1 },
+{ 0x3, 21, 1 },
+{ 0x2, 21, 0 },
+{ 0xf, 20, 1 },
+{ 0xe, 20, 1 },
+{ 0x7, 21, 1 },
+{ 0x6, 21, 0 },
+{ 0x8, 19, 0 },
+{ 0x18, 19, 0 },
+{ 0x2, 19, 1 },
+{ 0xc, 19, 0 },
+{ 0x1, 19, 1 },
+{ 0x4, 19, 0 },
+{ 0x51, 17, 0 },
+{ 0xd1, 17, 0 },
+{ 0x31, 17, 1 },
+{ 0x11, 18, 0 },
+{ 0x71, 17, 1 },
+{ 0x31, 18, 0 },
+{ 0x29, 17, 0 },
+{ 0x69, 17, 0 },
+{ 0x19, 17, 1 },
+{ 0x9, 18, 0 },
+{ 0x39, 17, 1 },
+{ 0x19, 18, 0 },
+{ 0x15, 17, 0 },
+{ 0x35, 17, 0 },
+{ 0xd, 17, 1 },
+{ 0x5, 18, 0 },
+{ 0x1d, 17, 1 },
+{ 0xd, 18, 0 },
+{ 0xb, 17, 0 },
+{ 0x1b, 17, 0 },
+{ 0x7, 17, 1 },
+{ 0x3, 18, 0 },
+{ 0xf, 17, 1 },
+{ 0x7, 18, 0 },
+{ 0x51, 15, 0 },
+{ 0xd1, 15, 0 },
+{ 0x31, 15, 1 },
+{ 0x11, 16, 0 },
+{ 0x71, 15, 1 },
+{ 0x31, 16, 0 },
+{ 0x29, 15, 0 },
+{ 0x69, 15, 0 },
+{ 0x19, 15, 1 },
+{ 0x9, 16, 0 },
+{ 0x39, 15, 1 },
+{ 0x19, 16, 0 },
+{ 0x15, 15, 0 },
+{ 0x35, 15, 0 },
+{ 0xd, 15, 1 },
+{ 0x5, 16, 0 },
+{ 0x1d, 15, 1 },
+{ 0xd, 16, 0 },
+{ 0xb, 15, 0 },
+{ 0x1b, 15, 0 },
+{ 0x7, 15, 1 },
+{ 0x3, 16, 0 },
+{ 0xf, 15, 1 },
+{ 0x7, 16, 0 },
+{ 0x288, 13, 0 },
+{ 0x688, 13, 0 },
+{ 0x188, 13, 1 },
+{ 0x88, 14, 0 },
+{ 0x388, 13, 1 },
+{ 0x188, 14, 0 },
+{ 0x148, 13, 0 },
+{ 0x348, 13, 0 },
+{ 0xc8, 13, 1 },
+{ 0x48, 14, 0 },
+{ 0x1c8, 13, 1 },
+{ 0xc8, 14, 0 },
+{ 0xa8, 13, 0 },
+{ 0x1a8, 13, 0 },
+{ 0x68, 13, 1 },
+{ 0x28, 14, 0 },
+{ 0xe8, 13, 1 },
+{ 0x68, 14, 0 },
+{ 0x58, 13, 0 },
+{ 0xd8, 13, 0 },
+{ 0x38, 13, 1 },
+{ 0x18, 14, 0 },
+{ 0x78, 13, 1 },
+{ 0x38, 14, 0 },
+{ 0x51, 13, 1 },
+{ 0xa0, 13, 0 },
+{ 0xd1, 13, 1 },
+{ 0x1a0, 13, 0 },
+{ 0x31, 13, 1 },
+{ 0x60, 13, 1 },
+{ 0x11, 14, 1 },
+{ 0x20, 14, 0 },
+{ 0x71, 13, 1 },
+{ 0xe0, 13, 1 },
+{ 0x31, 14, 1 },
+{ 0x60, 14, 0 },
+{ 0x29, 13, 1 },
+{ 0x50, 13, 0 },
+{ 0x69, 13, 1 },
+{ 0xd0, 13, 0 },
+{ 0x19, 13, 1 },
+{ 0x30, 13, 1 },
+{ 0x9, 14, 1 },
+{ 0x10, 14, 0 },
+{ 0x39, 13, 1 },
+{ 0x70, 13, 1 },
+{ 0x19, 14, 1 },
+{ 0x30, 14, 0 },
+{ 0x15, 13, 1 },
+{ 0x14, 13, 0 },
+{ 0x35, 13, 1 },
+{ 0x34, 13, 0 },
+{ 0xd, 13, 1 },
+{ 0xc, 13, 1 },
+{ 0x5, 14, 1 },
+{ 0x4, 14, 0 },
+{ 0x1d, 13, 1 },
+{ 0x1c, 13, 1 },
+{ 0xd, 14, 1 },
+{ 0xc, 14, 0 },
+{ 0xb, 13, 1 },
+{ 0xa, 13, 0 },
+{ 0x1b, 13, 1 },
+{ 0x1a, 13, 0 },
+{ 0x7, 13, 1 },
+{ 0x6, 13, 1 },
+{ 0x3, 14, 1 },
+{ 0x2, 14, 0 },
+{ 0xf, 13, 1 },
+{ 0xe, 13, 1 },
+{ 0x7, 14, 1 },
+{ 0x6, 14, 0 },
+{ 0x8, 12, 0 },
+{ 0x18, 12, 0 },
+{ 0x2, 12, 1 },
+{ 0xc, 12, 0 },
+{ 0x1, 12, 1 },
+{ 0x4, 12, 0 },
+{ 0x1, 11, 0 },
+{ 0x1, 10, 0 },
+{ 0x1, 9, 0 },
+{ 0x1, 8, 0 },
+{ 0x1, 7, 0 },
+{ 0x1, 6, 0 },
+{ 0x1, 5, 0 },
+{ 0x1, 4, 0 },
+{ 0x1, 3, 0 },
+{ 0x1, 1, 0 },
+{ 0x1, 0, 0 },
+};
+
--- /dev/null
+/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables.
+ Copyright (C) 1999 Free Software Foundation, Inc.
+ Contributed by Bob Manson of Cygnus Support <manson@cygnus.com>
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 2, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+#ifndef IA64_ASMTAB_H
+#define IA64_ASMTAB_H
+
+#include "opcode/ia64.h"
+
+/* The primary opcode table is made up of the following: */
+struct ia64_main_table
+{
+ /* The entry in the string table that corresponds to the name of this
+ opcode. */
+ unsigned short name_index;
+
+ /* The type of opcode; corresponds to the TYPE field in
+ struct ia64_opcode. */
+ unsigned char opcode_type;
+
+ /* The number of outputs for this opcode. */
+ unsigned char num_outputs;
+
+ /* The base insn value for this opcode. It may be modified by completers. */
+ ia64_insn opcode;
+
+ /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */
+ ia64_insn mask;
+
+ /* The operands of this instruction. Corresponds to the OPERANDS field
+ in struct ia64_opcode. */
+ unsigned char operands[5];
+
+ /* The flags for this instruction. Corresponds to the FLAGS field in
+ struct ia64_opcode. */
+ short flags;
+
+ /* The tree of completers for this instruction; this is an offset into
+ completer_table. */
+ short completers;
+};
+
+/* Each instruction has a set of possible "completers", or additional
+ suffixes that can alter the instruction's behavior, and which has
+ potentially different dependencies.
+
+ The completer entries modify certain bits in the instruction opcode.
+ Which bits are to be modified are marked by the BITS, MASK and
+ OFFSET fields. The completer entry may also note dependencies for the
+ opcode.
+
+ These completers are arranged in a DAG; the pointers are indexes
+ into the completer_table array. The completer DAG is searched by
+ find_completer () and ia64_find_matching_opcode ().
+
+ Note that each completer needs to be applied in turn, so that if we
+ have the instruction
+ cmp.lt.unc
+ the completer entries for both "lt" and "unc" would need to be applied
+ to the opcode's value.
+
+ Some instructions do not require any completers; these contain an
+ empty completer entry. Instructions that require a completer do
+ not contain an empty entry.
+
+ Terminal completers (those completers that validly complete an
+ instruction) are marked by having the TERMINAL_COMPLETER flag set.
+
+ Only dependencies listed in the terminal completer for an opcode are
+ considered to apply to that opcode instance. */
+
+struct ia64_completer_table
+{
+ /* The bit value that this completer sets. */
+ unsigned int bits;
+
+ /* And its mask. 1s are bits that are to be modified in the
+ instruction. */
+ unsigned int mask;
+
+ /* The entry in the string table that corresponds to the name of this
+ completer. */
+ unsigned short name_index;
+
+ /* An alternative completer, or -1 if this is the end of the chain. */
+ short alternative;
+
+ /* A pointer to the DAG of completers that can potentially follow
+ this one, or -1. */
+ short subentries;
+
+ /* The bit offset in the instruction where BITS and MASK should be
+ applied. */
+ unsigned char offset : 7;
+
+ unsigned char terminal_completer : 1;
+
+ /* Index into the dependency list table */
+ short dependencies;
+};
+
+/* This contains sufficient information for the disassembler to resolve
+ the complete name of the original instruction. */
+struct ia64_dis_names
+{
+ /* COMPLETER_INDEX represents the tree of completers that make up
+ the instruction. The LSB represents the top of the tree for the
+ specified instruction.
+
+ A 0 bit indicates to go to the next alternate completer via the
+ alternative field; a 1 bit indicates that the current completer
+ is part of the instruction, and to go down the subentries index.
+ We know we've reached the final completer when we run out of 1
+ bits.
+
+ There is always at least one 1 bit. */
+ unsigned int completer_index : 20;
+
+ /* The index in the main_table[] array for the instruction. */
+ unsigned short insn_index : 11;
+
+ /* If set, the next entry in this table is an alternate possibility
+ for this instruction encoding. Which one to use is determined by
+ the instruction type and other factors (see opcode_verify ()). */
+ unsigned int next_flag : 1;
+};
+
+#endif
--- /dev/null
+/* ia64-dis.c -- Disassemble ia64 instructions
+ Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 2, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+#include <assert.h>
+#include <string.h>
+
+#include "dis-asm.h"
+#include "opcode/ia64.h"
+
+#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0])))
+
+/* Disassemble ia64 instruction. */
+
+/* Return the instruction type for OPCODE found in unit UNIT. */
+
+static enum ia64_insn_type
+unit_to_type (ia64_insn opcode, enum ia64_unit unit)
+{
+ enum ia64_insn_type type;
+ int op;
+
+ op = IA64_OP (opcode);
+
+ if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M))
+ {
+ type = IA64_TYPE_A;
+ }
+ else
+ {
+ switch (unit)
+ {
+ case IA64_UNIT_I:
+ type = IA64_TYPE_I; break;
+ case IA64_UNIT_M:
+ type = IA64_TYPE_M; break;
+ case IA64_UNIT_B:
+ type = IA64_TYPE_B; break;
+ case IA64_UNIT_F:
+ type = IA64_TYPE_F; break;
+ case IA64_UNIT_L:
+ case IA64_UNIT_X:
+ type = IA64_TYPE_X; break;
+ default:
+ type = -1;
+ }
+ }
+ return type;
+}
+
+int
+print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
+{
+ ia64_insn t0, t1, slot[3], template, s_bit, insn;
+ int slotnum, j, status, need_comma, retval, slot_multiplier;
+ const struct ia64_operand *odesc;
+ const struct ia64_opcode *idesc;
+ const char *err, *str, *tname;
+ BFD_HOST_U_64_BIT value;
+ bfd_byte bundle[16];
+ enum ia64_unit unit;
+ char regname[16];
+
+ if (info->bytes_per_line == 0)
+ info->bytes_per_line = 6;
+ info->display_endian = info->endian;
+
+ slot_multiplier = info->bytes_per_line;
+ retval = slot_multiplier;
+
+ slotnum = (((long) memaddr) & 0xf) / slot_multiplier;
+ if (slotnum > 2)
+ return -1;
+
+ memaddr -= (memaddr & 0xf);
+ status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, memaddr, info);
+ return -1;
+ }
+ /* bundles are always in little-endian byte order */
+ t0 = bfd_getl64 (bundle);
+ t1 = bfd_getl64 (bundle + 8);
+ s_bit = t0 & 1;
+ template = (t0 >> 1) & 0xf;
+ slot[0] = (t0 >> 5) & 0x1ffffffffffLL;
+ slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
+ slot[2] = (t1 >> 23) & 0x1ffffffffffLL;
+
+ tname = ia64_templ_desc[template].name;
+ if (slotnum == 0)
+ (*info->fprintf_func) (info->stream, "[%s] ", tname);
+ else
+ (*info->fprintf_func) (info->stream, " ", tname);
+
+ unit = ia64_templ_desc[template].exec_unit[slotnum];
+
+ if (template == 2 && slotnum == 1)
+ {
+ /* skip L slot in MLI template: */
+ slotnum = 2;
+ retval += slot_multiplier;
+ }
+
+ insn = slot[slotnum];
+
+ if (unit == IA64_UNIT_NIL)
+ goto decoding_failed;
+
+ idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit));
+ if (idesc == NULL)
+ goto decoding_failed;
+
+ /* print predicate, if any: */
+
+ if ((idesc->flags & IA64_OPCODE_NO_PRED)
+ || (insn & 0x3f) == 0)
+ (*info->fprintf_func) (info->stream, " ");
+ else
+ (*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f));
+
+ /* now the actual instruction: */
+
+ (*info->fprintf_func) (info->stream, "%s", idesc->name);
+ if (idesc->operands[0])
+ (*info->fprintf_func) (info->stream, " ");
+
+ need_comma = 0;
+ for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j)
+ {
+ odesc = elf64_ia64_operands + idesc->operands[j];
+
+ if (need_comma)
+ (*info->fprintf_func) (info->stream, ",");
+
+ if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
+ {
+ /* special case of 64 bit immediate load: */
+ value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7)
+ | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21)
+ | (slot[1] << 22) | (((insn >> 36) & 0x1) << 63);
+ }
+ else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
+ {
+ /* 62-bit immediate for nop.x/break.x */
+ value = ((slot[1] & 0x1ffffffffffLL) << 21)
+ | (((insn >> 36) & 0x1) << 20)
+ | ((insn >> 6) & 0xfffff);
+ }
+ else
+ {
+ err = (*odesc->extract) (odesc, insn, &value);
+ if (err)
+ {
+ (*info->fprintf_func) (info->stream, "%s", err);
+ goto done;
+ }
+ }
+
+ switch (odesc->class)
+ {
+ case IA64_OPND_CLASS_CST:
+ (*info->fprintf_func) (info->stream, "%s", odesc->str);
+ break;
+
+ case IA64_OPND_CLASS_REG:
+ if (odesc->str[0] == 'a' && odesc->str[1] == 'r')
+ {
+ switch (value)
+ {
+ case 0: case 1: case 2: case 3:
+ case 4: case 5: case 6: case 7:
+ sprintf (regname, "ar.k%u", (unsigned int) value);
+ break;
+ case 16: strcpy (regname, "ar.rsc"); break;
+ case 17: strcpy (regname, "ar.bsp"); break;
+ case 18: strcpy (regname, "ar.bspstore"); break;
+ case 19: strcpy (regname, "ar.rnat"); break;
+ case 32: strcpy (regname, "ar.ccv"); break;
+ case 36: strcpy (regname, "ar.unat"); break;
+ case 40: strcpy (regname, "ar.fpsr"); break;
+ case 44: strcpy (regname, "ar.itc"); break;
+ case 64: strcpy (regname, "ar.pfs"); break;
+ case 65: strcpy (regname, "ar.lc"); break;
+ case 66: strcpy (regname, "ar.ec"); break;
+ default:
+ sprintf (regname, "ar%u", (unsigned int) value);
+ break;
+ }
+ (*info->fprintf_func) (info->stream, "%s", regname);
+ }
+ else
+ (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value);
+ break;
+
+ case IA64_OPND_CLASS_IND:
+ (*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value);
+ break;
+
+ case IA64_OPND_CLASS_ABS:
+ str = 0;
+ if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4)
+ switch (value)
+ {
+ case 0x0: str = "@brcst"; break;
+ case 0x8: str = "@mix"; break;
+ case 0x9: str = "@shuf"; break;
+ case 0xa: str = "@alt"; break;
+ case 0xb: str = "@rev"; break;
+ }
+
+ if (str)
+ (*info->fprintf_func) (info->stream, "%s", str);
+ else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED)
+ (*info->fprintf_func) (info->stream, "%lld", value);
+ else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED)
+ (*info->fprintf_func) (info->stream, "%llu", value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%llx", value);
+ break;
+
+ case IA64_OPND_CLASS_REL:
+ (*info->print_address_func) (memaddr + value, info);
+ break;
+ }
+
+ need_comma = 1;
+ if (j + 1 == idesc->num_outputs)
+ {
+ (*info->fprintf_func) (info->stream, "=");
+ need_comma = 0;
+ }
+ }
+ if (slotnum + 1 == ia64_templ_desc[template].group_boundary
+ || ((slotnum == 2) && s_bit))
+ (*info->fprintf_func) (info->stream, ";;");
+
+ done:
+ if (slotnum == 2)
+ retval += 16 - 3*slot_multiplier;
+ return retval;
+
+ decoding_failed:
+ (*info->fprintf_func) (info->stream, " data8 %#011llx", insn);
+ goto done;
+}
--- /dev/null
+/* ia64-gen.c -- Generate a shrunk set of opcode tables
+ Copyright (c) 1999 Free Software Foundation, Inc.
+ Written by Bob Manson, Cygnus Solutions, <manson@cygnus.com>
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 2, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+/* While the ia64-opc-* set of opcode tables are easy to maintain,
+ they waste a tremendous amount of space. ia64-gen rearranges the
+ instructions into a directed acyclic graph (DAG) of instruction opcodes and
+ their possible completers, as well as compacting the set of strings used.
+
+ The disassembler table consists of a state machine that does
+ branching based on the bits of the opcode being disassembled. The
+ state encodings have been chosen to minimize the amount of space
+ required.
+
+ The resource table is constructed based on some text dependency tables,
+ which are also easier to maintain than the final representation.
+
+*/
+
+#include <stdio.h>
+#include <ctype.h>
+
+#include "ansidecl.h"
+#include "libiberty.h"
+#include "sysdep.h"
+#include "ia64-opc.h"
+#include "ia64-opc-a.c"
+#include "ia64-opc-i.c"
+#include "ia64-opc-m.c"
+#include "ia64-opc-b.c"
+#include "ia64-opc-f.c"
+#include "ia64-opc-x.c"
+#include "ia64-opc-d.c"
+
+int debug = 0;
+
+#define tmalloc(X) (X *) xmalloc (sizeof (X))
+
+/* The main opcode table entry. Each entry is a unique combination of
+ name and flags (no two entries in the table compare as being equal
+ via opcodes_eq). */
+struct main_entry
+{
+ /* The base name of this opcode. The names of its completers are
+ appended to it to generate the full instruction name. */
+ struct string_entry *name;
+ /* The base opcode entry. Which one to use is a fairly arbitrary choice;
+ it uses the first one passed to add_opcode_entry. */
+ struct ia64_opcode *opcode;
+ /* The list of completers that can be applied to this opcode. */
+ struct completer_entry *completers;
+ /* Next entry in the chain. */
+ struct main_entry *next;
+} *maintable;
+
+/* The set of possible completers for an opcode. */
+struct completer_entry
+{
+ /* This entry's index in the ia64_completer_table[] array. */
+ int num;
+
+ /* The name of the completer. */
+ struct string_entry *name;
+
+ /* This entry's parent. */
+ struct completer_entry *parent;
+
+ /* Set if this is a terminal completer (occurs at the end of an
+ opcode). */
+ int is_terminal;
+
+ /* An alternative completer. */
+ struct completer_entry *alternative;
+
+ /* Additional completers that can be appended to this one. */
+ struct completer_entry *addl_entries;
+
+ /* Before compute_completer_bits () is invoked, this contains the actual
+ instruction opcode for this combination of opcode and completers.
+ Afterwards, it contains those bits that are different from its
+ parent opcode. */
+ ia64_insn bits;
+
+ /* Bits set to 1 correspond to those bits in this completer's opcode
+ that are different from its parent completer's opcode (or from
+ the base opcode if the entry is the root of the opcode's completer
+ list). This field is filled in by compute_completer_bits (). */
+ ia64_insn mask;
+
+ /* Index into the opcode dependency list, or -1 if none */
+ int dependencies;
+};
+
+/* One entry in the disassembler name table. */
+struct disent
+{
+ /* The index into the ia64_name_dis array for this entry. */
+ int ournum;
+
+ /* The index into the main_table[] array. */
+ int insn;
+
+ /* The completer_index value for this entry. */
+ int completer_index;
+
+ /* How many other entries share this decode. */
+ int nextcnt;
+
+ /* The next entry sharing the same decode. */
+ struct disent *nexte;
+
+ /* The next entry in the name list. */
+ struct disent *next_ent;
+} *disinsntable = NULL;
+
+/* A state machine that will eventually be used to generate the
+ disassembler table. */
+struct bittree
+{
+ struct disent *disent;
+ struct bittree *bits[3];
+ int bits_to_skip;
+ int skip_flag;
+} *bittree;
+
+/* The string table contains all opcodes and completers sorted in
+ alphabetical order. */
+
+/* One entry in the string table. */
+struct string_entry
+{
+ /* The index in the ia64_strings[] array for this entry. */
+ int num;
+ /* And the string. */
+ char *s;
+} **string_table = NULL;
+int strtablen = 0;
+int strtabtotlen = 0;
+
+\f
+/* resource dependency entries */
+struct rdep
+{
+ char *name; /* resource name */
+ unsigned
+ mode:2, /* RAW, WAW, or WAR */
+ semantics:3; /* dependency semantics */
+ char *extra; /* additional semantics info */
+ int nchks;
+ int total_chks; /* total #of terminal insns */
+ int *chks; /* insn classes which read (RAW), write
+ (WAW), or write (WAR) this rsrc */ //
+ int *chknotes; /* dependency notes for each class */
+ int nregs;
+ int total_regs; /* total #of terminal insns */
+ int *regs; /* insn class which write (RAW), write2
+ (WAW), or read (WAR) this rsrc */
+ int *regnotes; /* dependency notes for each class */
+
+ int waw_special; /* special WAW dependency note */
+} **rdeps = NULL;
+
+static int rdepslen = 0;
+static int rdepstotlen = 0;
+
+/* array of all instruction classes */
+struct iclass
+{
+ char *name; /* instruction class name */
+ int is_class; /* is a class, not a terminal */
+ int nsubs;
+ int *subs; /* other classes within this class */
+ int nxsubs;
+ int xsubs[4]; /* exclusions */
+ char *comment; /* optional comment */
+ int note; /* optional note */
+ int terminal_resolved; /* did we match this with anything? */
+ int orphan; /* detect class orphans */
+} **ics = NULL;
+
+static int iclen = 0;
+static int ictotlen = 0;
+
+/* an opcode dependency (chk/reg pair of dependency lists) */
+struct opdep
+{
+ int chk; /* index into dlists */
+ int reg; /* index into dlists */
+} **opdeps;
+
+static int opdeplen = 0;
+static int opdeptotlen = 0;
+
+/* a generic list of dependencies w/notes encoded. these may be shared. */
+struct deplist
+{
+ int len;
+ unsigned short *deps;
+} **dlists;
+
+static int dlistlen = 0;
+static int dlisttotlen = 0;
+
+/* add NAME to the resource table, where TYPE is RAW or WAW */
+static struct rdep *
+insert_resource (const char *name, enum ia64_dependency_mode type)
+{
+ if (rdepslen == rdepstotlen)
+ {
+ rdepstotlen += 20;
+ rdeps = (struct rdep **)
+ xrealloc (rdeps, sizeof(struct rdep **) * rdepstotlen);
+ }
+ rdeps[rdepslen] = tmalloc(struct rdep);
+ memset((void *)rdeps[rdepslen], 0, sizeof(struct rdep));
+ rdeps[rdepslen]->name = xstrdup (name);
+ rdeps[rdepslen]->mode = type;
+ rdeps[rdepslen]->waw_special = 0;
+
+ return rdeps[rdepslen++];
+}
+
+/* are the lists of dependency indexes equivalent? */
+static int
+deplist_equals (struct deplist *d1, struct deplist *d2)
+{
+ int i;
+
+ if (d1->len != d2->len)
+ return 0;
+
+ for (i=0;i < d1->len;i++)
+ {
+ if (d1->deps[i] != d2->deps[i])
+ return 0;
+ }
+
+ return 1;
+}
+
+/* add the list of dependencies to the list of dependency lists */
+static short
+insert_deplist(int count, unsigned short *deps)
+{
+ /* sort the list, then see if an equivalent list exists already.
+ this results in a much smaller set of dependency lists
+ */
+ struct deplist *list;
+ char set[0x10000];
+ int i;
+
+ memset ((void *)set, 0, sizeof(set));
+ for (i=0;i < count;i++)
+ set[deps[i]] = 1;
+ count = 0;
+ for (i=0;i < sizeof(set);i++)
+ if (set[i])
+ ++count;
+
+ list = tmalloc(struct deplist);
+ list->len = count;
+ list->deps = (unsigned short *)malloc (sizeof(unsigned short) * count);
+ for (i=0, count=0;i < sizeof(set);i++)
+ {
+ if (set[i])
+ {
+ list->deps[count++] = i;
+ }
+ }
+
+ /* does this list exist already? */
+ for (i=0;i < dlistlen;i++)
+ {
+ if (deplist_equals (list, dlists[i]))
+ {
+ free (list->deps);
+ free (list);
+ return i;
+ }
+ }
+
+ if (dlistlen == dlisttotlen)
+ {
+ dlisttotlen += 20;
+ dlists = (struct deplist **)
+ xrealloc (dlists, sizeof(struct deplist **) * dlisttotlen);
+ }
+ dlists[dlistlen] = list;
+
+ return dlistlen++;
+}
+
+/* add the given pair of dependency lists to the opcode dependency list */
+static short
+insert_dependencies (int nchks, unsigned short *chks,
+ int nregs, unsigned short *regs)
+{
+ struct opdep *pair;
+ int i;
+ int regind = -1;
+ int chkind = -1;
+
+ if (nregs > 0)
+ regind = insert_deplist (nregs, regs);
+ if (nchks > 0)
+ chkind = insert_deplist (nchks, chks);
+
+ for (i=0;i < opdeplen;i++)
+ {
+ if (opdeps[i]->chk == chkind
+ && opdeps[i]->reg == regind)
+ return i;
+ }
+ pair = tmalloc(struct opdep);
+ pair->chk = chkind;
+ pair->reg = regind;
+
+ if (opdeplen == opdeptotlen)
+ {
+ opdeptotlen += 20;
+ opdeps = (struct opdep **)
+ xrealloc (opdeps, sizeof(struct opdep **) * opdeptotlen);
+ }
+ opdeps[opdeplen] = pair;
+
+ return opdeplen++;
+}
+
+static void
+mark_used (struct iclass *ic, int clear_terminals)
+{
+ int i;
+
+ ic->orphan = 0;
+ if (clear_terminals)
+ ic->terminal_resolved = 1;
+
+ for (i=0;i < ic->nsubs;i++)
+ {
+ mark_used (ics[ic->subs[i]], clear_terminals);
+ }
+ for (i=0;i < ic->nxsubs;i++)
+ {
+ mark_used (ics[ic->xsubs[i]], clear_terminals);
+ }
+}
+
+/* look up an instruction class; if CREATE make a new one if none found;
+ returns the index into the insn class array */
+static int
+fetch_insn_class(const char *full_name, int create)
+{
+ char *name;
+ char *notestr;
+ char *xsect;
+ char *comment;
+ int i, note = 0;
+ int ind;
+ int is_class = 0;
+
+ if (strncmp (full_name, "IC:", 3) == 0)
+ {
+ name = xstrdup (full_name + 3);
+ is_class = 1;
+ }
+ else
+ name = xstrdup (full_name);
+
+ if ((xsect = strchr(name, '\\')) != NULL)
+ is_class = 1;
+ if ((comment = strchr(name, '[')) != NULL)
+ is_class = 1;
+ if ((notestr = strchr(name, '+')) != NULL)
+ {
+ char *nextnotestr;
+ is_class = 1;
+ note = atoi (notestr + 1);
+ if ((nextnotestr = strchr (notestr + 1, '+')) != NULL)
+ {
+ if (strcmp (notestr, "+1+13") == 0)
+ note = 13;
+ else if (!xsect || nextnotestr < xsect)
+ fprintf (stderr, "Warning: multiple note %s not handled\n",
+ notestr);
+ }
+ }
+
+ /* if it's a composite class, leave the notes and comments in place so that
+ we have a unique name for the composite class */
+ if (!xsect)
+ {
+ if (notestr)
+ *notestr = 0;
+ if (comment)
+ *comment = 0;
+ }
+
+ for (i=0;i < iclen;i++)
+ if (strcmp(name, ics[i]->name) == 0
+ && ((comment == NULL && ics[i]->comment == NULL)
+ || (comment != NULL && ics[i]->comment != NULL
+ && strncmp (ics[i]->comment, comment,
+ strlen (ics[i]->comment)) == 0))
+ && note == ics[i]->note)
+ return i;
+
+ if (!create)
+ return -1;
+
+ /* doesn't exist, so make a new one */
+ if (iclen == ictotlen)
+ {
+ ictotlen += 20;
+ ics = (struct iclass **)
+ xrealloc(ics, (ictotlen)*sizeof(struct iclass *));
+ }
+ ind = iclen++;
+ ics[ind] = tmalloc(struct iclass);
+ memset((void *)ics[ind], 0, sizeof(struct iclass));
+ ics[ind]->name = xstrdup(name);
+ ics[ind]->is_class = is_class;
+ ics[ind]->orphan = 1;
+
+ if (comment)
+ {
+ ics[ind]->comment = xstrdup (comment + 1);
+ ics[ind]->comment[strlen(ics[ind]->comment)-1] = 0;
+ }
+ if (notestr)
+ ics[ind]->note = note;
+
+ /* if it's a composite class, there's a comment or note, look for an
+ existing class or terminal with the same name. */
+ if ((xsect || comment || notestr) && is_class)
+ {
+ // first, populate with the class we're based on
+ char *subname = name;
+ if (xsect)
+ *xsect = 0;
+ else if (comment)
+ *comment = 0;
+ else if (notestr)
+ *notestr = 0;
+ ics[ind]->nsubs = 1;
+ ics[ind]->subs = tmalloc(int);
+ ics[ind]->subs[0] = fetch_insn_class (subname, 1);;
+ }
+
+ while (xsect)
+ {
+ char *subname = xsect + 1;
+ xsect = strchr (subname, '\\');
+ if (xsect)
+ *xsect = 0;
+ ics[ind]->xsubs[ics[ind]->nxsubs] = fetch_insn_class (subname,1);
+ ics[ind]->nxsubs++;
+ }
+ free (name);
+
+ return ind;
+}
+
+/* for sorting a class's sub-class list only; make sure classes appear before
+ terminals */
+static int
+sub_compare (const void *e1, const void *e2)
+{
+ struct iclass *ic1 = ics[*(int *)e1];
+ struct iclass *ic2 = ics[*(int *)e2];
+
+ if (ic1->is_class)
+ {
+ if (!ic2->is_class)
+ return -1;
+ }
+ else if (ic2->is_class)
+ return 1;
+
+ return strcmp (ic1->name, ic2->name);
+}
+
+static void
+load_insn_classes()
+{
+ FILE *fp = fopen("ia64-ic.tbl", "r");
+ char buf[2048];
+
+ /* discard first line */
+ fgets (buf, sizeof(buf), fp);
+
+ while (!feof(fp))
+ {
+ int iclass;
+ char *name;
+ char *tmp;
+
+ if (fgets (buf, sizeof(buf), fp) == NULL)
+ break;
+
+ while (isspace(buf[strlen(buf)-1]))
+ buf[strlen(buf)-1] = '\0';
+
+ name = tmp = buf;
+ while (*tmp != ';')
+ {
+ ++tmp;
+ if (tmp == buf + sizeof(buf))
+ abort ();
+ }
+ *tmp++ = '\0';
+
+ iclass = fetch_insn_class(name, 1);
+ ics[iclass]->is_class = 1;
+
+ if (strcmp (name, "none") == 0)
+ {
+ ics[iclass]->is_class = 0;
+ ics[iclass]->terminal_resolved = 1;
+ continue;
+ }
+
+ /* for this class, record all sub-classes */
+ while (*tmp)
+ {
+ char *subname;
+ int sub;
+
+ while (*tmp && isspace(*tmp))
+ {
+ ++tmp;
+ if (tmp == buf + sizeof(buf))
+ abort();
+ }
+ subname = tmp;
+ while (*tmp && *tmp != ',')
+ {
+ ++tmp;
+ if (tmp == buf + sizeof(buf))
+ abort();
+ }
+ if (*tmp == ',')
+ *tmp++ = '\0';
+
+ ics[iclass]->subs = (int *)
+ xrealloc((void *)ics[iclass]->subs,
+ (ics[iclass]->nsubs+1)*sizeof(int));
+
+ sub = fetch_insn_class(subname, 1);
+ ics[iclass]->subs = (int *)
+ xrealloc(ics[iclass]->subs, (ics[iclass]->nsubs+1)*sizeof(int));
+ ics[iclass]->subs[ics[iclass]->nsubs++] = sub;
+ }
+ /* make sure classes come before terminals */
+ qsort ((void *)ics[iclass]->subs,
+ ics[iclass]->nsubs, sizeof(int), sub_compare);
+ }
+ fclose(fp);
+
+ if (debug)
+ {
+ printf ("%d classes\n", iclen);
+ }
+}
+
+/* extract the insn classes from the given line */
+static void
+parse_resource_users(ref, usersp, nusersp, notesp)
+ char *ref;
+ int **usersp;
+ int *nusersp;
+ int **notesp;
+{
+ int c;
+ char *line = xstrdup (ref);
+ char *tmp = line;
+ int *users = *usersp;
+ int count = *nusersp;
+ int *notes = *notesp;
+
+ c = *tmp;
+ while (c != 0)
+ {
+ char *notestr;
+ int note;
+ char *xsect;
+ int iclass;
+ int create = 0;
+ char *name;
+
+ while (isspace(*tmp))
+ ++tmp;
+ name = tmp;
+ while (*tmp && *tmp != ',')
+ ++tmp;
+ c = *tmp;
+ *tmp++ = '\0';
+
+ xsect = strchr(name, '\\');
+ if ((notestr = strstr(name, "+")) != NULL)
+ {
+ char *nextnotestr;
+ note = atoi (notestr + 1);
+ if ((nextnotestr = strchr (notestr + 1, '+')) != NULL)
+ {
+ /* note 13 always implies note 1 */
+ if (strcmp (notestr, "+1+13") == 0)
+ note = 13;
+ else if (!xsect || nextnotestr < xsect)
+ fprintf (stderr, "Warning: multiple note %s not handled\n",
+ notestr);
+ }
+ if (!xsect)
+ *notestr = '\0';
+ }
+ else
+ note = 0;
+
+ /* All classes are created when the insn class table is parsed;
+ Individual instructions might not appear until the dependency tables
+ are read. Only create new classes if it's *not* an insn class,
+ or if it's a composite class (which wouldn't necessarily be in the IC
+ table).
+ */
+ if (strncmp(name, "IC:", 3) != 0 || xsect != NULL)
+ create = 1;
+
+ iclass = fetch_insn_class(name, create);
+ if (iclass != -1)
+ {
+ users = (int *)
+ xrealloc ((void *)users,(count+1)*sizeof(int));
+ notes = (int *)
+ xrealloc ((void *)notes,(count+1)*sizeof(int));
+ notes[count] = note;
+ users[count++] = iclass;
+ mark_used (ics[iclass], 0);
+ }
+ else
+ {
+ if (debug)
+ printf("Class %s not found\n", name);
+ }
+ }
+ /* update the return values */
+ *usersp = users;
+ *nusersp = count;
+ *notesp = notes;
+
+ free (line);
+}
+
+static int
+parse_semantics (char *sem)
+{
+ if (strcmp (sem, "none") == 0)
+ return IA64_DVS_NONE;
+ else if (strcmp (sem, "implied") == 0)
+ return IA64_DVS_IMPLIED;
+ else if (strcmp (sem, "impliedF") == 0)
+ return IA64_DVS_IMPLIEDF;
+ else if (strcmp (sem, "data") == 0)
+ return IA64_DVS_DATA;
+ else if (strcmp (sem, "instr") == 0)
+ return IA64_DVS_INSTR;
+ else if (strcmp (sem, "specific") == 0)
+ return IA64_DVS_SPECIFIC;
+ else
+ return IA64_DVS_OTHER;
+}
+
+static void
+add_dep (const char *name, const char *chk, const char *reg,
+ int semantics, int mode, char *extra, int flag)
+{
+ struct rdep *rs;
+
+ rs = insert_resource (name, mode);
+ parse_resource_users (chk, &rs->chks, &rs->nchks,
+ &rs->chknotes);
+ parse_resource_users (reg, &rs->regs, &rs->nregs,
+ &rs->regnotes);
+ rs->semantics = semantics;
+ rs->extra = extra;
+ rs->waw_special = flag;
+}
+
+static void
+load_depfile (const char *filename, enum ia64_dependency_mode mode)
+{
+ FILE *fp = fopen(filename, "r");
+ char buf[1024];
+
+ fgets(buf, sizeof(buf), fp);
+ while (!feof(fp))
+ {
+ char *name, *tmp;
+ int semantics;
+ char *extra;
+ char *regp, *chkp;
+
+ if (fgets (buf, sizeof(buf), fp) == NULL)
+ break;
+
+ while (isspace(buf[strlen(buf)-1]))
+ buf[strlen(buf)-1] = '\0';
+
+ name = tmp = buf;
+ while (*tmp != ';')
+ ++tmp;
+ *tmp++ = '\0';
+
+ while (isspace (*tmp))
+ ++tmp;
+ regp = tmp;
+ tmp = strchr (tmp, ';');
+ if (!tmp)
+ abort ();
+ *tmp++ = 0;
+ while (isspace (*tmp))
+ ++tmp;
+ chkp = tmp;
+ tmp = strchr (tmp, ';');
+ if (!tmp)
+ abort ();
+ *tmp++ = 0;
+ while (isspace (*tmp))
+ ++tmp;
+ semantics = parse_semantics (tmp);
+ extra = semantics == IA64_DVS_OTHER ? xstrdup (tmp) : NULL;
+
+ /* For WAW entries, if the chks and regs differ, we need to enter the
+ entries in both positions so that the tables will be parsed properly,
+ without a lot of extra work */
+ if (mode == IA64_DV_WAW && strcmp (regp, chkp) != 0)
+ {
+ add_dep (name, chkp, regp, semantics, mode, extra, 0);
+ add_dep (name, regp, chkp, semantics, mode, extra, 1);
+ }
+ else
+ {
+ add_dep (name, chkp, regp, semantics, mode, extra, 0);
+ }
+ }
+ fclose(fp);
+}
+
+static void
+load_dependencies()
+{
+ load_depfile ("ia64-raw.tbl", IA64_DV_RAW);
+ load_depfile ("ia64-waw.tbl", IA64_DV_WAW);
+ load_depfile ("ia64-war.tbl", IA64_DV_WAR);
+
+ if (debug)
+ printf ("%d RAW/WAW/WAR dependencies\n", rdepslen);
+}
+
+/* is the given operand an indirect register file operand? */
+static int
+irf_operand (int op, const char *field)
+{
+ if (!field)
+ {
+ return op == IA64_OPND_RR_R3 || op == IA64_OPND_DBR_R3
+ || op == IA64_OPND_IBR_R3 || op == IA64_OPND_PKR_R3
+ || op == IA64_OPND_PMC_R3 || op == IA64_OPND_PMD_R3
+ || op == IA64_OPND_MSR_R3 || op == IA64_OPND_CPUID_R3;
+ }
+ else
+ {
+ return ((op == IA64_OPND_RR_R3 && strstr (field, "rr"))
+ || (op == IA64_OPND_DBR_R3 && strstr (field, "dbr"))
+ || (op == IA64_OPND_IBR_R3 && strstr (field, "ibr"))
+ || (op == IA64_OPND_PKR_R3 && strstr (field, "pkr"))
+ || (op == IA64_OPND_PMC_R3 && strstr (field, "pmc"))
+ || (op == IA64_OPND_PMD_R3 && strstr (field, "pmd"))
+ || (op == IA64_OPND_MSR_R3 && strstr (field, "msr"))
+ || (op == IA64_OPND_CPUID_R3 && strstr (field, "cpuid")));
+ }
+}
+
+/* handle mov_ar, mov_br, mov_cr, mov_indirect, mov_ip, mov_pr, mov_psr, and
+ mov_um insn classes */
+static int
+in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic,
+ const char *format, const char *field)
+{
+ int plain_mov = strcmp (idesc->name, "mov") == 0;
+
+ if (!format)
+ return 0;
+
+ switch (ic->name[4])
+ {
+ default:
+ abort ();
+ case 'a':
+ {
+ int i = strcmp (idesc->name, "mov.i") == 0;
+ int m = strcmp (idesc->name, "mov.m") == 0;
+ int i2627 = i && idesc->operands[0] == IA64_OPND_AR3;
+ int i28 = i && idesc->operands[1] == IA64_OPND_AR3;
+ int m2930 = m && idesc->operands[0] == IA64_OPND_AR3;
+ int m31 = m && idesc->operands[1] == IA64_OPND_AR3;
+ int pseudo0 = plain_mov && idesc->operands[1] == IA64_OPND_AR3;
+ int pseudo1 = plain_mov && idesc->operands[0] == IA64_OPND_AR3;
+
+ /* IC:mov ar */
+ if (i2627)
+ return strstr (format, "I26") || strstr (format, "I27");
+ if (i28)
+ return strstr (format, "I28") != NULL;
+ if (m2930)
+ return strstr (format, "M29") || strstr (format, "M30");
+ if (m31)
+ return strstr (format, "M31") != NULL;
+ if (pseudo0 || pseudo1)
+ return 1;
+ }
+ break;
+ case 'b':
+ {
+ int i21 = idesc->operands[0] == IA64_OPND_B1;
+ int i22 = plain_mov && idesc->operands[1] == IA64_OPND_B2;
+ if (i22)
+ return strstr (format, "I22") != NULL;
+ if (i21)
+ return strstr (format, "I21") != NULL;
+ }
+ break;
+ case 'c':
+ {
+ int m32 = plain_mov && idesc->operands[0] == IA64_OPND_CR3;
+ int m33 = plain_mov && idesc->operands[1] == IA64_OPND_CR3;
+ if (m32)
+ return strstr (format, "M32") != NULL;
+ if (m33)
+ return strstr (format, "M33") != NULL;
+ }
+ break;
+ case 'i':
+ if (ic->name[5] == 'n')
+ {
+ int m42 = plain_mov && irf_operand (idesc->operands[0], field);
+ int m43 = plain_mov && irf_operand (idesc->operands[1], field);
+ if (m42)
+ return strstr (format, "M42") != NULL;
+ if (m43)
+ return strstr (format, "M43") != NULL;
+ }
+ else if (ic->name[5] == 'p')
+ {
+ return idesc->operands[1] == IA64_OPND_IP;
+ }
+ else
+ abort ();
+ break;
+ case 'p':
+ if (ic->name[5] == 'r')
+ {
+ int i25 = plain_mov && idesc->operands[1] == IA64_OPND_PR;
+ int i23 = plain_mov && idesc->operands[0] == IA64_OPND_PR;
+ int i24 = plain_mov && idesc->operands[0] == IA64_OPND_PR_ROT;
+ if (i23)
+ return strstr (format, "I23") != NULL;
+ if (i24)
+ return strstr (format, "I24") != NULL;
+ if (i25)
+ return strstr (format, "I25") != NULL;
+ }
+ else if (ic->name[5] == 's')
+ {
+ int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_L;
+ int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR;
+ if (m35)
+ return strstr (format, "M35") != NULL;
+ if (m36)
+ return strstr (format, "M36") != NULL;
+ }
+ else
+ abort ();
+ break;
+ case 'u':
+ {
+ int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_UM;
+ int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR_UM;
+ if (m35)
+ return strstr (format, "M35") != NULL;
+ if (m36)
+ return strstr (format, "M36") != NULL;
+ }
+ break;
+ }
+ return 0;
+}
+
+
+/* is the given opcode in the given insn class? */
+static int
+in_iclass(struct ia64_opcode *idesc, struct iclass *ic,
+ const char *format, const char *field, int *notep)
+{
+ int i;
+ int resolved = 0;
+
+ if (ic->comment)
+ {
+ if (!strncmp (ic->comment, "Format", 6))
+ {
+ /* assume that the first format seen is the most restrictive, and
+ only keep a later one if it looks like it's more restrictive. */
+ if (format)
+ {
+ if (strlen (ic->comment) < strlen (format))
+ {
+ fprintf (stderr, "Warning: most recent format '%s'\n"
+ "appears more restrictive than '%s'\n",
+ ic->comment, format);
+ format = ic->comment;
+ }
+ }
+ else
+ format = ic->comment;
+ }
+ else if (!strncmp (ic->comment, "Field", 5))
+ {
+ if (field)
+ fprintf (stderr, "Overlapping field %s->%s\n",
+ ic->comment, field);
+ field = ic->comment;
+ }
+ }
+
+ /* an insn class matches anything that is the same followed by completers,
+ except when the absence and presence of completers constitutes different
+ instructions */
+ if (ic->nsubs == 0 && ic->nxsubs == 0)
+ {
+ int is_mov = strncmp (idesc->name, "mov", 3) == 0;
+ int plain_mov = strcmp (idesc->name, "mov") == 0;
+ int len = strlen(ic->name);
+
+ resolved = ((strncmp (ic->name, idesc->name, len) == 0)
+ && (idesc->name[len] == '\0'
+ || idesc->name[len] == '.'));
+
+ /* all break and nop variations must match exactly */
+ if (resolved &&
+ (strcmp (ic->name, "break") == 0
+ || strcmp (ic->name, "nop") == 0))
+ resolved = strcmp (ic->name, idesc->name) == 0;
+
+ /* assume restrictions in the FORMAT/FIELD negate resolution,
+ unless specifically allowed by clauses in this block */
+ if (resolved && field)
+ {
+ /* check Field(sf)==sN against opcode sN */
+ if (strstr(field, "(sf)==") != NULL)
+ {
+ char *sf;
+ if ((sf = strstr (idesc->name, ".s")) != 0)
+ {
+ resolved = strcmp (sf + 1, strstr (field, "==") + 2) == 0;
+ }
+ }
+ /* check Field(lftype)==XXX */
+ else if (strstr (field, "(lftype)") != NULL)
+ {
+ if (strstr (idesc->name, "fault") != NULL)
+ resolved = strstr (field, "fault") != NULL;
+ else
+ resolved = strstr (field, "fault") == NULL;
+ }
+ /* handle Field(ctype)==XXX */
+ else if (strstr (field, "(ctype)") != NULL)
+ {
+ if (strstr (idesc->name, "or.andcm"))
+ resolved = strstr (field, "or.andcm") != NULL;
+ else if (strstr (idesc->name, "and.orcm"))
+ resolved = strstr (field, "and.orcm") != NULL;
+ else if (strstr (idesc->name, "orcm"))
+ resolved = strstr (field, "or orcm") != NULL;
+ else if (strstr (idesc->name, "or"))
+ resolved = strstr (field, "or orcm") != NULL;
+ else if (strstr (idesc->name, "andcm"))
+ resolved = strstr (field, "and andcm") != NULL;
+ else if (strstr (idesc->name, "and"))
+ resolved = strstr (field, "and andcm") != NULL;
+ else if (strstr (idesc->name, "unc"))
+ resolved = strstr (field, "unc") != NULL;
+ else
+ resolved = strcmp (field, "Field(ctype)==") == 0;
+ }
+ }
+ if (resolved && format)
+ {
+ if (strncmp (idesc->name, "dep", 3) == 0
+ && strstr (format, "I13") != NULL)
+ resolved = idesc->operands[1] == IA64_OPND_IMM8;
+ else if (strncmp (idesc->name, "chk", 3) == 0
+ && strstr (format, "M21") != NULL)
+ resolved = idesc->operands[0] == IA64_OPND_F2;
+ else if (strncmp (idesc->name, "lfetch", 6) == 0)
+ resolved = (strstr (format, "M14 M15") != NULL
+ && (idesc->operands[1] == IA64_OPND_R2
+ || idesc->operands[1] == IA64_OPND_IMM9b));
+ else if (strncmp (idesc->name, "br.call", 7) == 0
+ && strstr (format, "B5") != NULL)
+ resolved = idesc->operands[1] == IA64_OPND_B2;
+ else if (strncmp (idesc->name, "br.call", 7) == 0
+ && strstr (format, "B3") != NULL)
+ resolved = idesc->operands[1] == IA64_OPND_TGT25c;
+ else if (strncmp (idesc->name, "brp", 3) == 0
+ && strstr (format, "B7") != NULL)
+ resolved = idesc->operands[0] == IA64_OPND_B2;
+ else if (strcmp (ic->name, "invala") == 0)
+ resolved = strcmp (idesc->name, ic->name) == 0;
+ else
+ resolved = 0;
+ }
+
+ /* misc brl variations ('.cond' is optional);
+ plain brl matches brl.cond */
+ if (!resolved
+ && (strcmp (idesc->name, "brl") == 0
+ || strncmp (idesc->name, "brl.", 4) == 0)
+ && strcmp (ic->name, "brl.cond") == 0)
+ {
+ resolved = 1;
+ }
+
+ /* misc br variations ('.cond' is optional) */
+ if (!resolved
+ && (strcmp (idesc->name, "br") == 0
+ || strncmp (idesc->name, "br.", 3) == 0)
+ && strcmp (ic->name, "br.cond") == 0)
+ {
+ if (format)
+ resolved = (strstr (format, "B4") != NULL
+ && idesc->operands[0] == IA64_OPND_B2)
+ || (strstr (format, "B1") != NULL
+ && idesc->operands[0] == IA64_OPND_TGT25c);
+ else
+ resolved = 1;
+ }
+
+ /* probe variations */
+ if (!resolved && strncmp (idesc->name, "probe", 5) == 0)
+ {
+ resolved = strcmp (ic->name, "probe") == 0
+ && !((strstr (idesc->name, "fault") != NULL)
+ ^ (format && strstr (format, "M40") != NULL));
+ }
+ /* mov variations */
+ if (!resolved && is_mov)
+ {
+ if (plain_mov)
+ {
+ /* mov alias for fmerge */
+ if (strcmp (ic->name, "fmerge") == 0)
+ {
+ resolved = idesc->operands[0] == IA64_OPND_F1
+ && idesc->operands[1] == IA64_OPND_F3;
+ }
+ /* mov alias for adds (r3 or imm14) */
+ else if (strcmp (ic->name, "adds") == 0)
+ {
+ resolved = (idesc->operands[0] == IA64_OPND_R1
+ && (idesc->operands[1] == IA64_OPND_R3
+ || (idesc->operands[1] == IA64_OPND_IMM14)));
+ }
+ /* mov alias for addl */
+ else if (strcmp (ic->name, "addl") == 0)
+ {
+ resolved = idesc->operands[0] == IA64_OPND_R1
+ && idesc->operands[1] == IA64_OPND_IMM22;
+ }
+ }
+ /* some variants of mov and mov.[im] */
+ if (!resolved && strncmp (ic->name, "mov_", 4) == 0)
+ {
+ resolved = in_iclass_mov_x (idesc, ic, format, field);
+ }
+ }
+
+ /* keep track of this so we can flag any insn classes which aren't
+ mapped onto at least one real insn */
+ if (resolved)
+ {
+ ic->terminal_resolved = 1;
+ }
+ }
+ else for (i=0;i < ic->nsubs;i++)
+ {
+ if (in_iclass(idesc, ics[ic->subs[i]], format, field, notep))
+ {
+ int j;
+ for (j=0;j < ic->nxsubs;j++)
+ {
+ if (in_iclass(idesc, ics[ic->xsubs[j]], NULL, NULL, NULL))
+ return 0;
+ }
+ if (debug > 1)
+ printf ("%s is in IC %s\n",
+ idesc->name, ic->name);
+ resolved = 1;
+ break;
+ }
+ }
+
+ /* If it's in this IC, add the IC note (if any) to the insn */
+ if (resolved)
+ {
+ if (ic->note && notep)
+ {
+ if (*notep && *notep != ic->note)
+ {
+ fprintf (stderr, "Warning: overwriting note %d with note %d"
+ "(IC:%s)\n",
+ *notep, ic->note, ic->name);
+ }
+ *notep = ic->note;
+ }
+ }
+
+ return resolved;
+}
+
+\f
+static int
+lookup_regindex (const char *name, int specifier)
+{
+ switch (specifier)
+ {
+ case IA64_RS_ARX:
+ if (strstr (name, "[RSC]"))
+ return 16;
+ if (strstr (name, "[BSP]"))
+ return 17;
+ else if (strstr (name, "[BSPSTORE]"))
+ return 18;
+ else if (strstr (name, "[RNAT]"))
+ return 19;
+ else if (strstr (name, "[CCV]"))
+ return 32;
+ else if (strstr (name, "[ITC]"))
+ return 44;
+ else if (strstr (name, "[PFS]"))
+ return 64;
+ else if (strstr (name, "[LC]"))
+ return 65;
+ else if (strstr (name, "[EC]"))
+ return 66;
+ abort ();
+ case IA64_RS_CRX:
+ if (strstr (name, "[DCR]"))
+ return 0;
+ else if (strstr (name, "[ITM]"))
+ return 1;
+ else if (strstr (name, "[IVA]"))
+ return 2;
+ else if (strstr (name, "[PTA]"))
+ return 8;
+ else if (strstr (name, "[GPTA]"))
+ return 9;
+ else if (strstr (name, "[IPSR]"))
+ return 16;
+ else if (strstr (name, "[ISR]"))
+ return 17;
+ else if (strstr (name, "[IIP]"))
+ return 19;
+ else if (strstr (name, "[IFA]"))
+ return 20;
+ else if (strstr (name, "[ITIR]"))
+ return 21;
+ else if (strstr (name, "[IIPA]"))
+ return 22;
+ else if (strstr (name, "[IFS]"))
+ return 23;
+ else if (strstr (name, "[IIM]"))
+ return 24;
+ else if (strstr (name, "[IHA]"))
+ return 25;
+ else if (strstr (name, "[LID]"))
+ return 64;
+ else if (strstr (name, "[IVR]"))
+ return 65;
+ else if (strstr (name, "[TPR]"))
+ return 66;
+ else if (strstr (name, "[EOI]"))
+ return 67;
+ else if (strstr (name, "[ITV]"))
+ return 72;
+ else if (strstr (name, "[PMV]"))
+ return 73;
+ else if (strstr (name, "[CMCV]"))
+ return 74;
+ abort ();
+ case IA64_RS_PSR:
+ if (strstr (name, ".be"))
+ return 1;
+ else if (strstr (name, ".up"))
+ return 2;
+ else if (strstr (name, ".ac"))
+ return 3;
+ else if (strstr (name, ".mfl"))
+ return 4;
+ else if (strstr (name, ".mfh"))
+ return 5;
+ else if (strstr (name, ".ic"))
+ return 13;
+ else if (strstr (name, ".i"))
+ return 14;
+ else if (strstr (name, ".pk"))
+ return 15;
+ else if (strstr (name, ".dt"))
+ return 17;
+ else if (strstr (name, ".dfl"))
+ return 18;
+ else if (strstr (name, ".dfh"))
+ return 19;
+ else if (strstr (name, ".sp"))
+ return 20;
+ else if (strstr (name, ".pp"))
+ return 21;
+ else if (strstr (name, ".di"))
+ return 22;
+ else if (strstr (name, ".si"))
+ return 23;
+ else if (strstr (name, ".db"))
+ return 24;
+ else if (strstr (name, ".lp"))
+ return 25;
+ else if (strstr (name, ".tb"))
+ return 26;
+ else if (strstr (name, ".rt"))
+ return 27;
+ else if (strstr (name, ".cpl"))
+ return 32;
+ else if (strstr (name, ".rs"))
+ return 34;
+ else if (strstr (name, ".mc"))
+ return 35;
+ else if (strstr (name, ".it"))
+ return 36;
+ else if (strstr (name, ".id"))
+ return 37;
+ else if (strstr (name, ".da"))
+ return 38;
+ else if (strstr (name, ".dd"))
+ return 39;
+ else if (strstr (name, ".ss"))
+ return 40;
+ else if (strstr (name, ".ri"))
+ return 41;
+ else if (strstr (name, ".ed"))
+ return 43;
+ else if (strstr (name, ".bn"))
+ return 44;
+ else if (strstr (name, ".ia"))
+ return 45;
+ else
+ abort ();
+ default:
+ break;
+ }
+ return REG_NONE;
+}
+
+static int
+lookup_specifier (const char *name)
+{
+ if (strchr (name, '%'))
+ {
+ if (strstr (name, "AR[K%]") != NULL)
+ return IA64_RS_AR_K;
+ if (strstr (name, "AR[UNAT]") != NULL)
+ return IA64_RS_AR_UNAT;
+ if (strstr (name, "AR%, % in 8") != NULL)
+ return IA64_RS_AR;
+ if (strstr (name, "AR%, % in 48") != NULL)
+ return IA64_RS_ARb;
+ if (strstr (name, "BR%") != NULL)
+ return IA64_RS_BR;
+ if (strstr (name, "CR[IRR%]") != NULL)
+ return IA64_RS_CR_IRR;
+ if (strstr (name, "CR[LRR%]") != NULL)
+ return IA64_RS_CR_LRR;
+ if (strstr (name, "CR%") != NULL)
+ return IA64_RS_CR;
+ if (strstr (name, "FR%, % in 0") != NULL)
+ return IA64_RS_FR;
+ if (strstr (name, "FR%, % in 2") != NULL)
+ return IA64_RS_FRb;
+ if (strstr (name, "GR%") != NULL)
+ return IA64_RS_GR;
+ if (strstr (name, "PR%") != NULL)
+ return IA64_RS_PR;
+
+ fprintf (stderr, "Warning! Don't know how to specify %% dependency %s\n",
+ name);
+ }
+ else if (strchr (name, '#'))
+ {
+ if (strstr (name, "CPUID#") != NULL)
+ return IA64_RS_CPUID;
+ if (strstr (name, "DBR#") != NULL)
+ return IA64_RS_DBR;
+ if (strstr (name, "IBR#") != NULL)
+ return IA64_RS_IBR;
+ if (strstr (name, "MSR#") != NULL)
+ return IA64_RS_MSR;
+ if (strstr (name, "PKR#") != NULL)
+ return IA64_RS_PKR;
+ if (strstr (name, "PMC#") != NULL)
+ return IA64_RS_PMC;
+ if (strstr (name, "PMD#") != NULL)
+ return IA64_RS_PMD;
+ if (strstr (name, "RR#") != NULL)
+ return IA64_RS_RR;
+
+ fprintf (stderr, "Warning! Don't know how to specify # dependency %s\n",
+ name);
+ }
+ else if (strncmp (name, "AR[FPSR]", 8) == 0)
+ return IA64_RS_AR_FPSR;
+ else if (strncmp (name, "AR[", 3) == 0)
+ return IA64_RS_ARX;
+ else if (strncmp (name, "CR[", 3) == 0)
+ return IA64_RS_CRX;
+ else if (strncmp (name, "PSR.", 4) == 0)
+ return IA64_RS_PSR;
+ else if (strcmp (name, "InService*") == 0)
+ return IA64_RS_INSERVICE;
+ else if (strcmp (name, "GR0") == 0)
+ return IA64_RS_GR0;
+ else if (strcmp (name, "CFM") == 0)
+ return IA64_RS_CFM;
+ else if (strcmp (name, "PR63") == 0)
+ return IA64_RS_PR63;
+ else if (strcmp (name, "RSE") == 0)
+ return IA64_RS_RSE;
+
+ return IA64_RS_ANY;
+}
+
+void
+print_dependency_table ()
+{
+ int i, j;
+
+ if (debug)
+ {
+ for (i=0;i < iclen;i++)
+ {
+ if (ics[i]->is_class)
+ {
+ if (!ics[i]->nsubs)
+ {
+ fprintf (stderr, "Warning: IC:%s", ics[i]->name);
+ if (ics[i]->comment)
+ fprintf (stderr, "[%s]", ics[i]->comment);
+ fprintf (stderr, " has no terminals or sub-classes\n");
+ }
+ }
+ else
+ {
+ if (!ics[i]->terminal_resolved && !ics[i]->orphan)
+ {
+ fprintf(stderr, "Warning: no insns mapped directly to "
+ "terminal IC %s", ics[i]->name);
+ if (ics[i]->comment)
+ fprintf(stderr, "[%s] ", ics[i]->comment);
+ fprintf(stderr, "\n");
+ }
+ }
+ }
+
+ for (i=0;i < iclen;i++)
+ {
+ if (ics[i]->orphan)
+ {
+ mark_used (ics[i], 1);
+ fprintf (stderr, "Warning: class %s is defined but not used\n",
+ ics[i]->name);
+ }
+ }
+
+ if (debug > 1) for (i=0;i < rdepslen;i++)
+ {
+ static const char *mode_str[] = { "RAW", "WAW", "WAR" };
+ if (rdeps[i]->total_chks == 0)
+ {
+ fprintf (stderr, "Warning: rsrc %s (%s) has no chks%s\n",
+ rdeps[i]->name, mode_str[rdeps[i]->mode],
+ rdeps[i]->total_regs ? "" : " or regs");
+ }
+ else if (rdeps[i]->total_regs == 0)
+ {
+ fprintf (stderr, "Warning: rsrc %s (%s) has no regs\n",
+ rdeps[i]->name, mode_str[rdeps[i]->mode]);
+ }
+ }
+ }
+
+ /* the dependencies themselves */
+ printf ("static const struct ia64_dependency\ndependencies[] = {\n");
+ for (i=0;i < rdepslen;i++)
+ {
+ /* '%', '#', AR[], CR[], or PSR. indicates we need to specify the actual
+ resource used */
+ int specifier = lookup_specifier (rdeps[i]->name);
+ int regindex = lookup_regindex (rdeps[i]->name, specifier);
+
+ printf (" { \"%s\", %d, %d, %d, %d, ",
+ rdeps[i]->name, specifier,
+ (int)rdeps[i]->mode, (int)rdeps[i]->semantics, regindex);
+ if (rdeps[i]->semantics == IA64_DVS_OTHER)
+ printf ("\"%s\", ", rdeps[i]->extra);
+ printf("},\n");
+ }
+ printf ("};\n\n");
+
+ /* and dependency lists */
+ for (i=0;i < dlistlen;i++)
+ {
+ int len = 2;
+ printf ("static const short dep%d[] = {\n ", i);
+ for (j=0;j < dlists[i]->len; j++)
+ {
+ len += printf ("%d, ", dlists[i]->deps[j]);
+ if (len > 75)
+ {
+ printf("\n ");
+ len = 2;
+ }
+ }
+ printf ("\n};\n\n");
+ }
+
+ /* and opcode dependency list */
+ printf ("#define NELS(X) (sizeof(X)/sizeof(X[0]))\n");
+ printf ("static const struct ia64_opcode_dependency\n");
+ printf ("op_dependencies[] = {\n");
+ for (i=0;i < opdeplen;i++)
+ {
+ printf (" { ");
+ if (opdeps[i]->chk == -1)
+ printf ("0, NULL, ");
+ else
+ printf ("NELS(dep%d), dep%d, ", opdeps[i]->chk, opdeps[i]->chk);
+ if (opdeps[i]->reg == -1)
+ printf ("0, NULL, ");
+ else
+ printf ("NELS(dep%d), dep%d, ", opdeps[i]->reg, opdeps[i]->reg);
+ printf ("},\n");
+ }
+ printf ("};\n\n");
+}
+
+\f
+/* Add STR to the string table. */
+
+static struct string_entry *
+insert_string (str)
+ char *str;
+{
+ int start = 0, end = strtablen;
+ int i, x;
+
+ if (strtablen == strtabtotlen)
+ {
+ strtabtotlen += 20;
+ string_table = (struct string_entry **)
+ xrealloc (string_table,
+ sizeof (struct string_entry **) * strtabtotlen);
+ }
+
+ if (strtablen == 0)
+ {
+ strtablen = 1;
+ string_table[0] = tmalloc (struct string_entry);
+ string_table[0]->s = xstrdup (str);
+ string_table[0]->num = 0;
+ return string_table[0];
+ }
+
+ if (strcmp (str, string_table[strtablen - 1]->s) > 0)
+ {
+ i = end;
+ }
+ else if (strcmp (str, string_table[0]->s) < 0)
+ {
+ i = 0;
+ }
+ else
+ {
+ while (1)
+ {
+ int c;
+
+ i = (start + end) / 2;
+ c = strcmp (str, string_table[i]->s);
+ if (c < 0)
+ {
+ end = i - 1;
+ }
+ else if (c == 0)
+ {
+ return string_table[i];
+ }
+ else
+ {
+ start = i + 1;
+ }
+ if (start > end)
+ {
+ break;
+ }
+ }
+ }
+ for (; i > 0 && i < strtablen; i--)
+ {
+ if (strcmp (str, string_table[i - 1]->s) > 0)
+ {
+ break;
+ }
+ }
+ for (; i < strtablen; i++)
+ {
+ if (strcmp (str, string_table[i]->s) < 0)
+ {
+ break;
+ }
+ }
+ for (x = strtablen - 1; x >= i; x--)
+ {
+ string_table[x + 1] = string_table[x];
+ string_table[x + 1]->num = x + 1;
+ }
+ string_table[i] = tmalloc (struct string_entry);
+ string_table[i]->s = xstrdup (str);
+ string_table[i]->num = i;
+ strtablen++;
+ return string_table[i];
+}
+\f
+struct bittree *
+make_bittree_entry ()
+{
+ struct bittree *res = tmalloc (struct bittree);
+
+ res->disent = NULL;
+ res->bits[0] = NULL;
+ res->bits[1] = NULL;
+ res->bits[2] = NULL;
+ res->skip_flag = 0;
+ res->bits_to_skip = 0;
+ return res;
+}
+\f
+struct disent *
+add_dis_table_ent (which, insn, completer_index)
+ struct disent *which;
+ int insn;
+ int completer_index;
+{
+ int ci = 0;
+ struct disent *ent;
+
+ if (which != NULL)
+ {
+ ent = which;
+
+ ent->nextcnt++;
+ while (ent->nexte != NULL)
+ {
+ ent = ent->nexte;
+ }
+ ent = (ent->nexte = tmalloc (struct disent));
+ }
+ else
+ {
+ ent = tmalloc (struct disent);
+ ent->next_ent = disinsntable;
+ disinsntable = ent;
+ which = ent;
+ }
+ ent->nextcnt = 0;
+ ent->nexte = NULL;
+ ent->insn = insn;
+ while (completer_index != 1)
+ {
+ ci = (ci << 1) | (completer_index & 1);
+ completer_index >>= 1;
+ }
+ ent->completer_index = ci;
+ return which;
+}
+\f
+void
+finish_distable ()
+{
+ struct disent *ent = disinsntable;
+ struct disent *prev = ent;
+
+ ent->ournum = 32768;
+ while ((ent = ent->next_ent) != NULL)
+ {
+ ent->ournum = prev->ournum + prev->nextcnt + 1;
+ prev = ent;
+ }
+}
+\f
+void
+insert_bit_table_ent (curr_ent, bit, opcode, mask, opcodenum, completer_index)
+ struct bittree *curr_ent;
+ int bit;
+ ia64_insn opcode;
+ ia64_insn mask;
+ int opcodenum;
+ int completer_index;
+{
+ ia64_insn m;
+ int b;
+ struct bittree *next;
+
+ if (bit == -1)
+ {
+ struct disent *nent = add_dis_table_ent (curr_ent->disent, opcodenum,
+ completer_index);
+ curr_ent->disent = nent;
+ return;
+ }
+
+ m = ((ia64_insn) 1) << bit;
+
+ if (mask & m)
+ {
+ b = (opcode & m) ? 1 : 0;
+ }
+ else
+ {
+ b = 2;
+ }
+ next = curr_ent->bits[b];
+ if (next == NULL)
+ {
+ next = make_bittree_entry ();
+ curr_ent->bits[b] = next;
+ }
+ insert_bit_table_ent (next, bit - 1, opcode, mask, opcodenum,
+ completer_index);
+}
+\f
+void
+add_dis_entry (first, opcode, mask, opcodenum, ent, completer_index)
+ int first;
+ ia64_insn opcode;
+ ia64_insn mask;
+ int opcodenum;
+ struct completer_entry *ent;
+ int completer_index;
+{
+ if (completer_index & (1 << 20))
+ {
+ abort ();
+ }
+ while (ent != NULL)
+ {
+ ia64_insn newopcode = (opcode & (~ ent->mask)) | ent->bits;
+ add_dis_entry (first, newopcode, mask, opcodenum, ent->addl_entries,
+ (completer_index << 1) | 1);
+ if (ent->is_terminal)
+ {
+ insert_bit_table_ent (bittree, 40, newopcode, mask, opcodenum,
+ (completer_index << 1) | 1);
+ }
+ completer_index <<= 1;
+ ent = ent->alternative;
+ }
+}
+\f
+/* This optimization pass combines multiple "don't care" nodes. */
+void
+compact_distree (ent)
+ struct bittree *ent;
+{
+#define IS_SKIP(ent) \
+ ((ent->bits[2] !=NULL) \
+ && (ent->bits[0] == NULL && ent->bits[1] == NULL && ent->skip_flag == 0))
+
+ int bitcnt = 0;
+ struct bittree *nent = ent;
+ int x;
+
+ while (IS_SKIP (nent))
+ {
+ bitcnt++;
+ nent = nent->bits[2];
+ }
+
+ if (bitcnt)
+ {
+ struct bittree *next = ent->bits[2];
+
+ ent->bits[0] = nent->bits[0];
+ ent->bits[1] = nent->bits[1];
+ ent->bits[2] = nent->bits[2];
+ ent->disent = nent->disent;
+ ent->skip_flag = 1;
+ ent->bits_to_skip = bitcnt;
+ while (next != nent)
+ {
+ struct bittree *b = next;
+ next = next->bits[2];
+ free (b);
+ }
+ free (nent);
+ }
+
+ for (x = 0; x < 3; x++)
+ {
+ struct bittree *i = ent->bits[x];
+ if (i != NULL)
+ {
+ compact_distree (i);
+ }
+ }
+}
+\f
+static unsigned char *insn_list;
+static int insn_list_len = 0;
+static int tot_insn_list_len = 0;
+
+/* Generate the disassembler state machine corresponding to the tree
+ in ENT. */
+void
+gen_dis_table (ent)
+ struct bittree *ent;
+{
+ int x;
+ int our_offset = insn_list_len;
+ int bitsused = 5;
+ int totbits = bitsused;
+ int needed_bytes;
+ int zero_count = 0;
+ int zero_dest = 0; /* initialize this with 0 to keep gcc quiet... */
+
+ /* If this is a terminal entry, there's no point in skipping any
+ bits. */
+ if (ent->skip_flag && ent->bits[0] == NULL && ent->bits[1] == NULL &&
+ ent->bits[2] == NULL)
+ {
+ if (ent->disent == NULL)
+ {
+ abort ();
+ }
+ else
+ {
+ ent->skip_flag = 0;
+ }
+ }
+
+ /* Calculate the amount of space needed for this entry, or at least
+ a conservatively large approximation. */
+ if (ent->skip_flag)
+ {
+ totbits += 5;
+ }
+ for (x = 1; x < 3; x++)
+ {
+ if (ent->bits[x] != NULL)
+ {
+ totbits += 16;
+ }
+ }
+
+ if (ent->disent != NULL)
+ {
+ if (ent->bits[2] != NULL)
+ {
+ abort ();
+ }
+ totbits += 16;
+ }
+
+ /* Now allocate the space. */
+ needed_bytes = (totbits + 7) / 8;
+ if ((needed_bytes + insn_list_len) > tot_insn_list_len)
+ {
+ tot_insn_list_len += 256;
+ insn_list = (char *) xrealloc (insn_list, tot_insn_list_len);
+ }
+ our_offset = insn_list_len;
+ insn_list_len += needed_bytes;
+ memset (insn_list + our_offset, 0, needed_bytes);
+
+ /* Encode the skip entry by setting bit 6 set in the state op field,
+ and store the # of bits to skip immediately after. */
+ if (ent->skip_flag)
+ {
+ bitsused += 5;
+ insn_list[our_offset + 0] |= 0x40 | ((ent->bits_to_skip >> 2) & 0xf);
+ insn_list[our_offset + 1] |= ((ent->bits_to_skip & 3) << 6);
+ }
+
+#define IS_ONLY_IFZERO(ENT) \
+ ((ENT)->bits[0] != NULL && (ENT)->bits[1] == NULL && (ENT)->bits[2] == NULL \
+ && (ENT)->disent == NULL && (ENT)->skip_flag == 0)
+
+ /* Store an "if (bit is zero)" instruction by setting bit 7 in the
+ state op field. */
+
+ if (ent->bits[0] != NULL)
+ {
+ struct bittree *nent = ent->bits[0];
+ zero_count = 0;
+
+ insn_list[our_offset] |= 0x80;
+
+ /* We can encode sequences of multiple "if (bit is zero)" tests
+ by storing the # of zero bits to check in the lower 3 bits of
+ the instruction. However, this only applies if the state
+ solely tests for a zero bit. */
+
+ if (IS_ONLY_IFZERO (ent))
+ {
+ while (IS_ONLY_IFZERO (nent) && zero_count < 7)
+ {
+ nent = nent->bits[0];
+ zero_count++;
+ }
+
+ insn_list[our_offset + 0] |= zero_count;
+ }
+ zero_dest = insn_list_len;
+ gen_dis_table (nent);
+ }
+
+ /* Now store the remaining tests. We also handle a sole "termination
+ entry" by storing it as an "any bit" test. */
+
+ for (x = 1; x < 3; x++)
+ {
+ if (ent->bits[x] != NULL || (x == 2 && ent->disent != NULL))
+ {
+ struct bittree *i = ent->bits[x];
+ int idest;
+ int currbits = 15;
+
+ if (i != NULL)
+ {
+ /* If the instruction being branched to only consists of
+ a termination entry, use the termination entry as the
+ place to branch to instead. */
+ if (i->bits[0] == NULL && i->bits[1] == NULL
+ && i->bits[2] == NULL && i->disent != NULL)
+ {
+ idest = i->disent->ournum;
+ i = NULL;
+ }
+ else
+ {
+ idest = insn_list_len - our_offset;
+ }
+ }
+ else
+ {
+ idest = ent->disent->ournum;
+ }
+
+ /* If the destination offset for the if (bit is 1) test is less
+ than 256 bytes away, we can store it as 8-bits instead of 16;
+ the instruction has bit 5 set for the 16-bit address, and bit
+ 4 for the 8-bit address. Since we've already allocated 16
+ bits for the address we need to deallocate the space.
+
+ Note that branchings within the table are relative, and
+ there are no branches that branch past our instruction yet
+ so we do not need to adjust any other offsets. */
+
+ if (x == 1)
+ {
+ if (idest <= 256)
+ {
+ int start = our_offset + bitsused / 8 + 1;
+
+ memmove (insn_list + start,
+ insn_list + start + 1,
+ insn_list_len - (start + 1));
+ currbits = 7;
+ totbits -= 8;
+ needed_bytes--;
+ insn_list_len--;
+ insn_list[our_offset] |= 0x10;
+ idest--;
+ }
+ else
+ {
+ insn_list[our_offset] |= 0x20;
+ }
+ }
+ else
+ {
+ /* An instruction which solely consists of a termination
+ marker and whose disassembly name index is < 4096
+ can be stored in 16 bits. The encoding is slightly
+ odd; the upper 4 bits of the instruction are 0x3, and
+ bit 3 loses its normal meaning. */
+
+ if (ent->bits[0] == NULL && ent->bits[1] == NULL
+ && ent->bits[2] == NULL && ent->skip_flag == 0
+ && ent->disent != NULL
+ && ent->disent->ournum < (32768 + 4096))
+ {
+ int start = our_offset + bitsused / 8 + 1;
+
+ memmove (insn_list + start,
+ insn_list + start + 1,
+ insn_list_len - (start + 1));
+ currbits = 11;
+ totbits -= 5;
+ bitsused--;
+ needed_bytes--;
+ insn_list_len--;
+ insn_list[our_offset] |= 0x30;
+ idest &= ~32768;
+ }
+ else
+ {
+ insn_list[our_offset] |= 0x08;
+ }
+ }
+ if (debug)
+ {
+ int id = idest;
+
+ if (i == NULL)
+ {
+ id |= 32768;
+ }
+ else if (! (id & 32768))
+ {
+ id += our_offset;
+ }
+ if (x == 1)
+ {
+ printf ("%d: if (1) goto %d\n", our_offset, id);
+ }
+ else
+ {
+ printf ("%d: try %d\n", our_offset, id);
+ }
+ }
+
+ /* Store the address of the entry being branched to. */
+ while (currbits >= 0)
+ {
+ char *byte = insn_list + our_offset + bitsused / 8;
+
+ if (idest & (1 << currbits))
+ {
+ *byte |= (1 << (7 - (bitsused % 8)));
+ }
+ bitsused++;
+ currbits--;
+ }
+
+ /* Now generate the states for the entry being branched to. */
+ if (i != NULL)
+ {
+ gen_dis_table (i);
+ }
+
+ }
+ }
+ if (debug)
+ {
+ if (ent->skip_flag)
+ {
+ printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip);
+ }
+
+ if (ent->bits[0] != NULL)
+ {
+ printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1,
+ zero_dest);
+ }
+ }
+ if (bitsused != totbits)
+ {
+ abort ();
+ }
+}
+\f
+void
+print_dis_table ()
+{
+ int x;
+ struct disent *cent = disinsntable;
+
+ printf ("static const char dis_table[] = {\n");
+ for (x = 0; x < insn_list_len; x++)
+ {
+ if ((x > 0) && ((x % 12) == 0))
+ {
+ printf ("\n");
+ }
+ printf ("0x%02x, ", insn_list[x]);
+ }
+ printf ("\n};\n\n");
+
+ printf ("static const struct ia64_dis_names ia64_dis_names[] = {\n");
+ while (cent != NULL)
+ {
+ struct disent *ent = cent;
+
+ while (ent != NULL)
+ {
+ printf ("{ 0x%x, %d, %d },\n", ent->completer_index,
+ ent->insn,
+ (ent->nexte != NULL ? 1 : 0));
+ ent = ent->nexte;
+ }
+ cent = cent->next_ent;
+ }
+ printf ("};\n\n");
+}
+\f
+void
+generate_disassembler ()
+{
+ int mainnum = 0;
+ struct main_entry *ptr = maintable;
+
+ bittree = make_bittree_entry ();
+
+ while (ptr != NULL)
+ {
+ if (ptr->opcode->type != IA64_TYPE_DYN)
+ {
+ add_dis_entry (bittree,
+ ptr->opcode->opcode, ptr->opcode->mask, mainnum,
+ ptr->completers, 1);
+ }
+ mainnum++;
+ ptr = ptr->next;
+ }
+
+ compact_distree (bittree);
+ finish_distable ();
+ gen_dis_table (bittree);
+
+ print_dis_table ();
+}
+\f
+void
+print_string_table ()
+{
+ int x;
+ char lbuf[80], buf[80];
+ int blen = 0;
+
+ printf ("static const char *ia64_strings[] = {\n");
+ lbuf[0] = '\0';
+ for (x = 0; x < strtablen; x++)
+ {
+ int len;
+
+ if (strlen (string_table[x]->s) > 75)
+ {
+ abort ();
+ }
+ sprintf (buf, " \"%s\",", string_table[x]->s);
+ len = strlen (buf);
+ if ((blen + len) > 75)
+ {
+ printf (" %s\n", lbuf);
+ lbuf[0] = '\0';
+ blen = 0;
+ }
+ strcat (lbuf, buf);
+ blen += len;
+ }
+ if (blen > 0)
+ {
+ printf (" %s\n", lbuf);
+ }
+ printf ("};\n\n");
+}
+\f
+static struct completer_entry **glist;
+static int glistlen = 0;
+static int glisttotlen = 0;
+
+/* If the completer trees ENT1 and ENT2 are equal, return 1. */
+
+int
+completer_entries_eq (ent1, ent2)
+ struct completer_entry *ent1, *ent2;
+{
+ while (ent1 != NULL && ent2 != NULL)
+ {
+ if (ent1->name->num != ent2->name->num
+ || ent1->bits != ent2->bits
+ || ent1->mask != ent2->mask
+ || ent1->is_terminal != ent2->is_terminal
+ || ent1->dependencies != ent2->dependencies)
+ {
+ return 0;
+ }
+ if (! completer_entries_eq (ent1->addl_entries, ent2->addl_entries))
+ {
+ return 0;
+ }
+ ent1 = ent1->alternative;
+ ent2 = ent2->alternative;
+ }
+ return ent1 == ent2;
+}
+\f
+/* Insert ENT into the global list of completers and return it. If an
+ equivalent entry (according to completer_entries_eq) already exists,
+ it is returned instead. */
+struct completer_entry *
+insert_gclist (ent)
+ struct completer_entry *ent;
+{
+ if (ent != NULL)
+ {
+ int i;
+ int x;
+ int start = 0, end;
+
+ ent->addl_entries = insert_gclist (ent->addl_entries);
+ ent->alternative = insert_gclist (ent->alternative);
+
+ i = glistlen / 2;
+ end = glistlen;
+
+ if (glisttotlen == glistlen)
+ {
+ glisttotlen += 20;
+ glist = (struct completer_entry **)
+ xrealloc (glist, sizeof (struct completer_entry *) * glisttotlen);
+ }
+
+ if (glistlen == 0)
+ {
+ glist[0] = ent;
+ glistlen = 1;
+ return ent;
+ }
+
+ if (ent->name->num < glist[0]->name->num)
+ {
+ i = 0;
+ }
+ else if (ent->name->num > glist[end - 1]->name->num)
+ {
+ i = end;
+ }
+ else
+ {
+ int c;
+
+ while (1)
+ {
+ i = (start + end) / 2;
+ c = ent->name->num - glist[i]->name->num;
+ if (c < 0)
+ {
+ end = i - 1;
+ }
+ else if (c == 0)
+ {
+ while (i > 0
+ && ent->name->num == glist[i - 1]->name->num)
+ {
+ i--;
+ }
+ break;
+ }
+ else
+ {
+ start = i + 1;
+ }
+ if (start > end)
+ {
+ break;
+ }
+ }
+ if (c == 0)
+ {
+ while (i < glistlen)
+ {
+ if (ent->name->num != glist[i]->name->num)
+ {
+ break;
+ }
+ if (completer_entries_eq (ent, glist[i]))
+ {
+ return glist[i];
+ }
+ i++;
+ }
+ }
+ }
+ for (; i > 0 && i < glistlen; i--)
+ {
+ if (ent->name->num >= glist[i - 1]->name->num)
+ {
+ break;
+ }
+ }
+ for (; i < glistlen; i++)
+ {
+ if (ent->name->num < glist[i]->name->num)
+ {
+ break;
+ }
+ }
+ for (x = glistlen - 1; x >= i; x--)
+ {
+ glist[x + 1] = glist[x];
+ }
+ glist[i] = ent;
+ glistlen++;
+ }
+ return ent;
+}
+\f
+static int
+get_prefix_len (name)
+ const char *name;
+{
+ char *c;
+
+ if (name[0] == '\0')
+ {
+ return 0;
+ }
+
+ c = strchr (name, '.');
+ if (c != NULL)
+ {
+ return c - name;
+ }
+ else
+ {
+ return strlen (name);
+ }
+}
+\f
+static void
+compute_completer_bits (ment, ent)
+ struct main_entry *ment;
+ struct completer_entry *ent;
+{
+ while (ent != NULL)
+ {
+ compute_completer_bits (ment, ent->addl_entries);
+
+ if (ent->is_terminal)
+ {
+ ia64_insn mask = 0;
+ ia64_insn our_bits = ent->bits;
+ struct completer_entry *p = ent->parent;
+ ia64_insn p_bits;
+ int x;
+
+ while (p != NULL && ! p->is_terminal)
+ {
+ p = p->parent;
+ }
+
+ if (p != NULL)
+ {
+ p_bits = p->bits;
+ }
+ else
+ {
+ p_bits = ment->opcode->opcode;
+ }
+
+ for (x = 0; x < 64; x++)
+ {
+ ia64_insn m = ((ia64_insn) 1) << x;
+ if ((p_bits & m) != (our_bits & m))
+ {
+ mask |= m;
+ }
+ else
+ {
+ our_bits &= ~m;
+ }
+ }
+ ent->bits = our_bits;
+ ent->mask = mask;
+ }
+ else
+ {
+ ent->bits = 0;
+ ent->mask = 0;
+ }
+
+ ent = ent->alternative;
+ }
+}
+\f
+/* Find identical completer trees that are used in different
+ instructions and collapse their entries. */
+void
+collapse_redundant_completers ()
+{
+ struct main_entry *ptr;
+ int x;
+
+ for (ptr = maintable; ptr != NULL; ptr = ptr->next)
+ {
+ if (ptr->completers == NULL)
+ {
+ abort ();
+ }
+ compute_completer_bits (ptr, ptr->completers);
+ ptr->completers = insert_gclist (ptr->completers);
+ }
+
+ /* The table has been finalized, now number the indexes. */
+ for (x = 0; x < glistlen; x++)
+ {
+ glist[x]->num = x;
+ }
+}
+\f
+
+/* attach two lists of dependencies to each opcode.
+ 1) all resources which, when already marked in use, conflict with this
+ opcode (chks)
+ 2) all resources which must be marked in use when this opcode is used
+ (regs)
+*/
+int
+insert_opcode_dependencies (opc, cmp)
+ struct ia64_opcode *opc;
+ struct completer_entry *cmp;
+{
+ /* note all resources which point to this opcode. rfi has the most chks
+ (79) and cmpxchng has the most regs (54) so 100 here should be enough */
+ int i;
+ int nregs = 0;
+ unsigned short regs[256];
+ int nchks = 0;
+ unsigned short chks[256];
+ /* flag insns for which no class matched; there should be none */
+ int no_class_found = 1;
+
+ for (i=0;i < rdepslen;i++)
+ {
+ struct rdep *rs = rdeps[i];
+ int j;
+
+ if (strcmp (opc->name, "cmp.eq.and") == 0
+ && strncmp (rs->name, "PR%", 3) == 0
+ && rs->mode == 1)
+ no_class_found = 99;
+
+ for (j=0; j < rs->nregs;j++)
+ {
+ int ic_note = 0;
+
+ if (in_iclass (opc, ics[rs->regs[j]], NULL, NULL, &ic_note))
+ {
+ /* We can ignore ic_note 11 for non PR resources */
+ if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0)
+ ic_note = 0;
+
+ if (ic_note != 0 && rs->regnotes[j] != 0
+ && ic_note != rs->regnotes[j]
+ && !(ic_note == 11 && rs->regnotes[j] == 1))
+ fprintf (stderr, "Warning: IC note %d in opcode %s (IC:%s)"
+ " conflicts with resource %s note %d\n",
+ ic_note, opc->name, ics[rs->regs[j]]->name,
+ rs->name, rs->regnotes[j]);
+ /* Instruction class notes override resource notes.
+ So far, only note 11 applies to an IC instead of a resource,
+ and note 11 implies note 1.
+ */
+ if (ic_note)
+ regs[nregs++] = RDEP(ic_note, i);
+ else
+ regs[nregs++] = RDEP(rs->regnotes[j], i);
+ no_class_found = 0;
+ ++rs->total_regs;
+ }
+ }
+ for (j=0;j < rs->nchks;j++)
+ {
+ int ic_note = 0;
+
+ if (in_iclass (opc, ics[rs->chks[j]], NULL, NULL, &ic_note))
+ {
+ /* We can ignore ic_note 11 for non PR resources */
+ if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0)
+ ic_note = 0;
+
+ if (ic_note != 0 && rs->chknotes[j] != 0
+ && ic_note != rs->chknotes[j]
+ && !(ic_note == 11 && rs->chknotes[j] == 1))
+ fprintf (stderr, "Warning: IC note %d for opcode %s (IC:%s)"
+ " conflicts with resource %s note %d\n",
+ ic_note, opc->name, ics[rs->chks[j]]->name,
+ rs->name, rs->chknotes[j]);
+ if (ic_note)
+ chks[nchks++] = RDEP(ic_note, i);
+ else
+ chks[nchks++] = RDEP(rs->chknotes[j], i);
+ no_class_found = 0;
+ ++rs->total_chks;
+ }
+ }
+ }
+
+ if (no_class_found)
+ fprintf (stderr, "Warning: opcode %s has no class (ops %d %d %d)\n",
+ opc->name,
+ opc->operands[0], opc->operands[1], opc->operands[2]);
+
+ return insert_dependencies (nchks, chks, nregs, regs);
+}
+\f
+void
+insert_completer_entry (opc, tabent)
+ struct ia64_opcode *opc;
+ struct main_entry *tabent;
+{
+ struct completer_entry **ptr = &tabent->completers;
+ struct completer_entry *parent = NULL;
+ char pcopy[129], *prefix;
+ int at_end = 0;
+
+ if (strlen (opc->name) > 128)
+ {
+ abort ();
+ }
+ strcpy (pcopy, opc->name);
+ prefix = pcopy + get_prefix_len (pcopy);
+ if (prefix[0] != '\0')
+ {
+ prefix++;
+ }
+
+ while (! at_end)
+ {
+ int need_new_ent = 1;
+ int plen = get_prefix_len (prefix);
+ struct string_entry *sent;
+
+ at_end = (prefix[plen] == '\0');
+ prefix[plen] = '\0';
+ sent = insert_string (prefix);
+
+ while (*ptr != NULL)
+ {
+ int cmpres = sent->num - (*ptr)->name->num;
+
+ if (cmpres == 0)
+ {
+ need_new_ent = 0;
+ break;
+ }
+ else if (cmpres < 0)
+ {
+ break;
+ }
+ else
+ {
+ ptr = &((*ptr)->alternative);
+ }
+ }
+ if (need_new_ent)
+ {
+ struct completer_entry *nent = tmalloc (struct completer_entry);
+ nent->name = sent;
+ nent->parent = parent;
+ nent->addl_entries = NULL;
+ nent->alternative = *ptr;
+ *ptr = nent;
+ nent->is_terminal = 0;
+ nent->dependencies = -1;
+ }
+
+ if (! at_end)
+ {
+ parent = *ptr;
+ ptr = &((*ptr)->addl_entries);
+ prefix += plen + 1;
+ }
+ }
+
+ if ((*ptr)->is_terminal)
+ {
+ abort ();
+ }
+
+ (*ptr)->is_terminal = 1;
+ (*ptr)->mask = (ia64_insn)-1;
+ (*ptr)->bits = opc->opcode;
+
+ (*ptr)->dependencies = insert_opcode_dependencies (opc, *ptr);
+}
+\f
+void
+print_completer_entry (ent)
+ struct completer_entry *ent;
+{
+ int moffset = 0;
+ ia64_insn mask = ent->mask, bits = ent->bits;
+
+ if (mask != 0)
+ {
+ while (! (mask & 1))
+ {
+ moffset++;
+ mask = mask >> 1;
+ bits = bits >> 1;
+ }
+ if (bits & 0xffffffff00000000LL)
+ {
+ abort ();
+ }
+ }
+
+ printf (" { 0x%x, 0x%x, %d, %d, %d, %d, %d, %d },\n",
+ (int)bits,
+ (int)mask,
+ ent->name->num,
+ ent->alternative != NULL ? ent->alternative->num : -1,
+ ent->addl_entries != NULL ? ent->addl_entries->num : -1,
+ moffset,
+ ent->is_terminal ? 1 : 0,
+ ent->dependencies);
+}
+\f
+void
+print_completer_table ()
+{
+ int x;
+
+ printf ("static const struct ia64_completer_table\ncompleter_table[] = {\n");
+ for (x = 0; x < glistlen; x++)
+ {
+ print_completer_entry (glist[x]);
+ }
+ printf ("};\n\n");
+}
+\f
+int
+opcodes_eq (opc1, opc2)
+ struct ia64_opcode *opc1;
+ struct ia64_opcode *opc2;
+{
+ int x;
+ int plen1, plen2;
+
+ if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type)
+ || (opc1->num_outputs != opc2->num_outputs)
+ || (opc1->flags != opc2->flags))
+ {
+ return 0;
+ }
+ for (x = 0; x < 5; x++)
+ {
+ if (opc1->operands[x] != opc2->operands[x])
+ {
+ return 0;
+ }
+ }
+ plen1 = get_prefix_len (opc1->name);
+ plen2 = get_prefix_len (opc2->name);
+ if (plen1 == plen2 && (memcmp (opc1->name, opc2->name, plen1) == 0))
+ {
+ return 1;
+ }
+ return 0;
+}
+\f
+void
+add_opcode_entry (opc)
+ struct ia64_opcode *opc;
+{
+ struct main_entry **place;
+ struct string_entry *name;
+ char prefix[129];
+ int found_it = 0;
+
+ if (strlen (opc->name) > 128)
+ {
+ abort ();
+ }
+ place = &maintable;
+ strcpy (prefix, opc->name);
+ prefix[get_prefix_len (prefix)] = '\0';
+ name = insert_string (prefix);
+
+ /* Walk the list of opcode table entries. If it's a new
+ instruction, allocate and fill in a new entry. */
+
+ while (*place != NULL)
+ {
+ if ((*place)->name->num == name->num
+ && opcodes_eq ((*place)->opcode, opc))
+ {
+ found_it = 1;
+ break;
+ }
+ if ((*place)->name->num > name->num)
+ {
+ break;
+ }
+ place = &((*place)->next);
+ }
+ if (! found_it)
+ {
+ struct main_entry *nent = tmalloc (struct main_entry);
+
+ nent->name = name;
+ nent->opcode = opc;
+ nent->next = *place;
+ nent->completers = 0;
+ *place = nent;
+ }
+ insert_completer_entry (opc, *place);
+}
+\f
+void
+print_main_table ()
+{
+ struct main_entry *ptr = maintable;
+
+ printf ("static const struct ia64_main_table\nmain_table[] = {\n");
+ while (ptr != NULL)
+ {
+ printf (" { %d, %d, %d, 0x%llxull, 0x%llxull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n",
+ ptr->name->num,
+ ptr->opcode->type,
+ ptr->opcode->num_outputs,
+ ptr->opcode->opcode,
+ ptr->opcode->mask,
+ ptr->opcode->operands[0],
+ ptr->opcode->operands[1],
+ ptr->opcode->operands[2],
+ ptr->opcode->operands[3],
+ ptr->opcode->operands[4],
+ ptr->opcode->flags,
+ ptr->completers->num);
+
+ ptr = ptr->next;
+ }
+ printf ("};\n\n");
+}
+\f
+void
+shrink (table)
+ struct ia64_opcode *table;
+{
+ int curr_opcode;
+
+ for (curr_opcode = 0; table[curr_opcode].name != NULL; curr_opcode++)
+ {
+ add_opcode_entry (table + curr_opcode);
+ }
+}
+\f
+int
+main (int argc, char **argv)
+{
+ if (argc > 1)
+ {
+ debug = 1;
+ }
+
+ load_insn_classes();
+ load_dependencies();
+
+ shrink (ia64_opcodes_a);
+ shrink (ia64_opcodes_b);
+ shrink (ia64_opcodes_f);
+ shrink (ia64_opcodes_i);
+ shrink (ia64_opcodes_m);
+ shrink (ia64_opcodes_x);
+ shrink (ia64_opcodes_d);
+
+ collapse_redundant_completers ();
+
+ printf ("/* This file is automatically generated by ia64-gen. Do not edit! */\n");
+ print_string_table ();
+ print_dependency_table ();
+ print_completer_table ();
+ print_main_table ();
+
+ generate_disassembler ();
+
+ exit (0);
+}
--- /dev/null
+Class; Events/Instructions
+all; IC:predicatable-instructions, IC:unpredicatable-instructions
+branches; IC:indirect-brs, IC:ip-rel-brs
+cfm-readers; IC:fr-readers, IC:fr-writers, IC:gr-readers, IC:gr-writers, IC:mod-sched-brs, IC:predicatable-instructions, IC:pr-writers, alloc, br.call, brl.call, br.ret, cover, loadrs, rfi, IC:chk-a, invala.e
+chk-a; chk.a.clr, chk.a.nc
+cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8
+czx; czx1, czx2
+fcmp-s0; fcmp[Field(sf)==s0]
+fcmp-s1; fcmp[Field(sf)==s1]
+fcmp-s2; fcmp[Field(sf)==s2]
+fcmp-s3; fcmp[Field(sf)==s3]
+fetchadd; fetchadd4, fetchadd8
+fp-arith; fadd, famax, famin, fcvt.fx, fcvt.fxu, fcvt.xuf, fma, fmax, fmin, fmpy, fms, fnma, fnmpy, fnorm, fpamax, fpamin, fpcvt.fx, fpcvt.fxu, fpma, fpmax, fpmin, fpmpy, fpms, fpnma, fpnmpy, fprcpa, fprsqrta, frcpa, frsqrta, fsub
+fp-arith-s0; IC:fp-arith[Field(sf)==s0]
+fp-arith-s1; IC:fp-arith[Field(sf)==s1]
+fp-arith-s2; IC:fp-arith[Field(sf)==s2]
+fp-arith-s3; IC:fp-arith[Field(sf)==s3]
+fp-non-arith; fabs, fand, fandcm, fclass, fcvt.xf, fmerge, fmix, fneg, fnegabs, for, fpabs, fpmerge, fpack, fpneg, fpnegabs, fselect, fswap, fsxt, fxor, xma
+fpcmp-s0; fpcmp[Field(sf)==s0]
+fpcmp-s1; fpcmp[Field(sf)==s1]
+fpcmp-s2; fpcmp[Field(sf)==s2]
+fpcmp-s3; fpcmp[Field(sf)==s3]
+fr-readers; IC:fp-arith, IC:fp-non-arith, IC:pr-writers-fp, chk.s[Format in {M21}], getf
+fr-writers; IC:fp-arith, IC:fp-non-arith\fclass, IC:mem-readers-fp
+gr-readers; IC:gr-readers-writers, IC:mem-readers, IC:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC:mov-to-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-to-PR-allreg, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:probe-all, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, setf, tbit, tnat
+gr-readers-writers; IC:mov-from-IND, add, addl, addp4, adds, and, andcm, IC:czx, dep\dep[Format in {I13}], extr, IC:mem-readers-int, IC:ld-all-postinc, IC:lfetch-postinc, IC:mix, IC:mux, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-nofault, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, shl, shladd, shladdp4, shr, shrp, IC:st-postinc, sub, IC:sxt, tak, thash, tpa, ttag, IC:unpack, xor, IC:zxt
+gr-writers; alloc, dep, getf, IC:gr-readers-writers, IC:mem-readers-int, IC:mov-from-AR, IC:mov-from-BR, IC:mov-from-CR, IC:mov-from-PR, IC:mov-immediate, IC:mov-from-PSR, IC:mov-from-PSR-um, IC:mov-ip, movl
+indirect-brp; brp[Format in {B7}]
+indirect-brs; br.call[Format in {B5}], br.cond[Format in {B4}], br.ia, br.ret
+invala-all; invala[Format in {M24}], invala.e
+ip-rel-brs; IC:mod-sched-brs, br.call[Format in {B3}], brl.call, brl.cond, br.cond[Format in {B1}], br.cloop
+ld; ld1, ld2, ld4, ld8, ld8.fill
+ld-a; ld1.a, ld2.a, ld4.a, ld8.a
+ld-all-postinc; IC:ld[Format in {M2 M3}], IC:ldfp[Format in {M12}], IC:ldf[Format in {M7 M8}]
+ld-c; IC:ld-c-nc, IC:ld-c-clr
+ld-c-clr; ld1.c.clr, ld2.c.clr, ld4.c.clr, ld8.c.clr, IC:ld-c-clr-acq
+ld-c-clr-acq; ld1.c.clr.acq, ld2.c.clr.acq, ld4.c.clr.acq, ld8.c.clr.acq
+ld-c-nc; ld1.c.nc, ld2.c.nc, ld4.c.nc, ld8.c.nc
+ld-s; ld1.s, ld2.s, ld4.s, ld8.s
+ld-sa; ld1.sa, ld2.sa, ld4.sa, ld8.sa
+ldf; ldfs, ldfd, ldfe, ldf8, ldf.fill
+ldf-a; ldfs.a, ldfd.a, ldfe.a, ldf8.a
+ldf-c; IC:ldf-c-nc, IC:ldf-c-clr
+ldf-c-clr; ldfs.c.clr, ldfd.c.clr, ldfe.c.clr, ldf8.c.clr
+ldf-c-nc; ldfs.c.nc, ldfd.c.nc, ldfe.c.nc, ldf8.c.nc
+ldf-s; ldfs.s, ldfd.s, ldfe.s, ldf8.s
+ldf-sa; ldfs.sa, ldfd.sa, ldfe.sa, ldf8.sa
+ldfp; ldfps, ldfpd, ldfp8
+ldfp-a; ldfps.a, ldfpd.a, ldfp8.a
+ldfp-c; IC:ldfp-c-nc, IC:ldfp-c-clr
+ldfp-c-clr; ldfps.c.clr, ldfpd.c.clr, ldfp8.c.clr
+ldfp-c-nc; ldfps.c.nc, ldfpd.c.nc, ldfp8.c.nc
+ldfp-s; ldfps.s, ldfpd.s, ldfp8.s
+ldfp-sa; ldfps.sa, ldfpd.sa, ldfp8.sa
+lfetch-all; lfetch
+lfetch-fault; lfetch[Field(lftype)==fault]
+lfetch-nofault; lfetch[Field(lftype)==]
+lfetch-postinc; lfetch[Format in {M14 M15}]
+mem-readers; IC:mem-readers-fp, IC:mem-readers-int
+mem-readers-alat; IC:ld-a, IC:ldf-a, IC:ldfp-a, IC:ld-sa, IC:ldf-sa, IC:ldfp-sa, IC:ld-c, IC:ldf-c, IC:ldfp-c
+mem-readers-fp; IC:ldf, IC:ldfp
+mem-readers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:ld
+mem-readers-spec; IC:ld-s, IC:ld-sa, IC:ldf-s, IC:ldf-sa, IC:ldfp-s, IC:ldfp-sa
+mem-writers; IC:mem-writers-fp, IC:mem-writers-int
+mem-writers-fp; IC:stf
+mem-writers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:st
+mix; mix1, mix2, mix4
+mod-sched-brs; br.cexit, br.ctop, br.wexit, br.wtop
+mod-sched-brs-counted; br.cexit, br.cloop, br.ctop
+mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM
+mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP]
+mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE]
+mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV]
+mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) == EC]
+mov-from-AR-FPSR; IC:mov-from-AR-M[Field(ar3) == FPSR]
+mov-from-AR-I; mov_ar[Format in {I28}]
+mov-from-AR-ig; IC:mov-from-AR-IM[Field(ar3) in {48-63 112-127}]
+mov-from-AR-IM; mov_ar[Format in {I28 M31}]
+mov-from-AR-ITC; IC:mov-from-AR-M[Field(ar3) == ITC]
+mov-from-AR-K; IC:mov-from-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}]
+mov-from-AR-LC; IC:mov-from-AR-I[Field(ar3) == LC]
+mov-from-AR-M; mov_ar[Format in {M31}]
+mov-from-AR-PFS; IC:mov-from-AR-I[Field(ar3) == PFS]
+mov-from-AR-RNAT; IC:mov-from-AR-M[Field(ar3) == RNAT]
+mov-from-AR-RSC; IC:mov-from-AR-M[Field(ar3) == RSC]
+mov-from-AR-rv; IC:none
+mov-from-AR-UNAT; IC:mov-from-AR-M[Field(ar3) == UNAT]
+mov-from-BR; mov_br[Format in {I22}]
+mov-from-CR; mov_cr[Format in {M33}]
+mov-from-CR-CMCV; IC:mov-from-CR[Field(cr3) == CMCV]
+mov-from-CR-DCR; IC:mov-from-CR[Field(cr3) == DCR]
+mov-from-CR-EOI; IC:mov-from-CR[Field(cr3) == EOI]
+mov-from-CR-GPTA; IC:mov-from-CR[Field(cr3) == GPTA]
+mov-from-CR-IFA; IC:mov-from-CR[Field(cr3) == IFA]
+mov-from-CR-IFS; IC:mov-from-CR[Field(cr3) == IFS]
+mov-from-CR-IHA; IC:mov-from-CR[Field(cr3) == IHA]
+mov-from-CR-IIM; IC:mov-from-CR[Field(cr3) == IIM]
+mov-from-CR-IIP; IC:mov-from-CR[Field(cr3) == IIP]
+mov-from-CR-IIPA; IC:mov-from-CR[Field(cr3) == IIPA]
+mov-from-CR-IPSR; IC:mov-from-CR[Field(cr3) == IPSR]
+mov-from-CR-IRR; IC:mov-from-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}]
+mov-from-CR-ISR; IC:mov-from-CR[Field(cr3) == ISR]
+mov-from-CR-ITIR; IC:mov-from-CR[Field(cr3) == ITIR]
+mov-from-CR-ITM; IC:mov-from-CR[Field(cr3) == ITM]
+mov-from-CR-ITV; IC:mov-from-CR[Field(cr3) == ITV]
+mov-from-CR-IVA; IC:mov-from-CR[Field(cr3) == IVA]
+mov-from-CR-IVR; IC:mov-from-CR[Field(cr3) == IVR]
+mov-from-CR-LID; IC:mov-from-CR[Field(cr3) == LID]
+mov-from-CR-LRR; IC:mov-from-CR[Field(cr3) in {LRR0 LRR1}]
+mov-from-CR-PMV; IC:mov-from-CR[Field(cr3) == PMV]
+mov-from-CR-PTA; IC:mov-from-CR[Field(cr3) == PTA]
+mov-from-CR-rv; IC:none
+mov-from-CR-TPR; IC:mov-from-CR[Field(cr3) == TPR]
+mov-from-IND; mov_indirect[Format in {M43}]
+mov-from-IND-CPUID; IC:mov-from-IND[Field(ireg) == cpuid]
+mov-from-IND-DBR; IC:mov-from-IND[Field(ireg) == dbr]
+mov-from-IND-IBR; IC:mov-from-IND[Field(ireg) == ibr]
+mov-from-IND-MSR; IC:mov-from-IND[Field(ireg) == msr]
+mov-from-IND-PKR; IC:mov-from-IND[Field(ireg) == pkr]
+mov-from-IND-PMC; IC:mov-from-IND[Field(ireg) == pmc]
+mov-from-IND-PMD; IC:mov-from-IND[Field(ireg) == pmd]
+mov-from-IND-priv; IC:mov-from-IND[Field(ireg) in {dbr ibr msr pkr pmc rr}]
+mov-from-IND-RR; IC:mov-from-IND[Field(ireg) == rr]
+mov-from-PR; mov_pr[Format in {I25}]
+mov-from-PSR; mov_psr[Format in {M36}]
+mov-from-PSR-um; mov_um[Format in {M36}]
+mov-immediate; addl[Format in {A5}]
+mov-ip; mov_ip[Format in {I25}]
+mov-to-AR; IC:mov-to-AR-M, IC:mov-to-AR-I
+mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) == BSP]
+mov-to-AR-BSPSTORE; IC:mov-to-AR-M[Field(ar3) == BSPSTORE]
+mov-to-AR-CCV; IC:mov-to-AR-M[Field(ar3) == CCV]
+mov-to-AR-EC; IC:mov-to-AR-I[Field(ar3) == EC]
+mov-to-AR-FPSR; IC:mov-to-AR-M[Field(ar3) == FPSR]
+mov-to-AR-gr; IC:mov-to-AR-M[Format in {M29}], IC:mov-to-AR-I[Format in {I26}]
+mov-to-AR-I; mov_ar[Format in {I26 I27}]
+mov-to-AR-ig; IC:mov-to-AR-IM[Field(ar3) in {48-63 112-127}]
+mov-to-AR-IM; mov_ar[Format in {I26 I27 M29 M30}]
+mov-to-AR-ITC; IC:mov-to-AR-M[Field(ar3) == ITC]
+mov-to-AR-K; IC:mov-to-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}]
+mov-to-AR-LC; IC:mov-to-AR-I[Field(ar3) == LC]
+mov-to-AR-M; mov_ar[Format in {M29 M30}]
+mov-to-AR-PFS; IC:mov-to-AR-I[Field(ar3) == PFS]
+mov-to-AR-RNAT; IC:mov-to-AR-M[Field(ar3) == RNAT]
+mov-to-AR-RSC; IC:mov-to-AR-M[Field(ar3) == RSC]
+mov-to-AR-UNAT; IC:mov-to-AR-M[Field(ar3) == UNAT]
+mov-to-BR; mov_br[Format in {I21}]
+mov-to-CR; mov_cr[Format in {M32}]
+mov-to-CR-CMCV; IC:mov-to-CR[Field(cr3) == CMCV]
+mov-to-CR-DCR; IC:mov-to-CR[Field(cr3) == DCR]
+mov-to-CR-EOI; IC:mov-to-CR[Field(cr3) == EOI]
+mov-to-CR-GPTA; IC:mov-to-CR[Field(cr3) == GPTA]
+mov-to-CR-IFA; IC:mov-to-CR[Field(cr3) == IFA]
+mov-to-CR-IFS; IC:mov-to-CR[Field(cr3) == IFS]
+mov-to-CR-IHA; IC:mov-to-CR[Field(cr3) == IHA]
+mov-to-CR-IIM; IC:mov-to-CR[Field(cr3) == IIM]
+mov-to-CR-IIP; IC:mov-to-CR[Field(cr3) == IIP]
+mov-to-CR-IIPA; IC:mov-to-CR[Field(cr3) == IIPA]
+mov-to-CR-IPSR; IC:mov-to-CR[Field(cr3) == IPSR]
+mov-to-CR-IRR; IC:mov-to-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}]
+mov-to-CR-ISR; IC:mov-to-CR[Field(cr3) == ISR]
+mov-to-CR-ITIR; IC:mov-to-CR[Field(cr3) == ITIR]
+mov-to-CR-ITM; IC:mov-to-CR[Field(cr3) == ITM]
+mov-to-CR-ITV; IC:mov-to-CR[Field(cr3) == ITV]
+mov-to-CR-IVA; IC:mov-to-CR[Field(cr3) == IVA]
+mov-to-CR-IVR; IC:mov-to-CR[Field(cr3) == IVR]
+mov-to-CR-LID; IC:mov-to-CR[Field(cr3) == LID]
+mov-to-CR-LRR; IC:mov-to-CR[Field(cr3) in {LRR0 LRR1}]
+mov-to-CR-PMV; IC:mov-to-CR[Field(cr3) == PMV]
+mov-to-CR-PTA; IC:mov-to-CR[Field(cr3) == PTA]
+mov-to-CR-TPR; IC:mov-to-CR[Field(cr3) == TPR]
+mov-to-IND; mov_indirect[Format in {M42}]
+mov-to-IND-CPUID; IC:mov-to-IND[Field(ireg) == cpuid]
+mov-to-IND-DBR; IC:mov-to-IND[Field(ireg) == dbr]
+mov-to-IND-IBR; IC:mov-to-IND[Field(ireg) == ibr]
+mov-to-IND-MSR; IC:mov-to-IND[Field(ireg) == msr]
+mov-to-IND-PKR; IC:mov-to-IND[Field(ireg) == pkr]
+mov-to-IND-PMC; IC:mov-to-IND[Field(ireg) == pmc]
+mov-to-IND-PMD; IC:mov-to-IND[Field(ireg) == pmd]
+mov-to-IND-priv; IC:mov-to-IND
+mov-to-IND-RR; IC:mov-to-IND[Field(ireg) == rr]
+mov-to-PR; IC:mov-to-PR-allreg, IC:mov-to-PR-rotreg
+mov-to-PR-allreg; mov_pr[Format in {I23}]
+mov-to-PR-rotreg; mov_pr[Format in {I24}]
+mov-to-PSR-l; mov_psr[Format in {M35}]
+mov-to-PSR-um; mov_um[Format in {M35}]
+mux; mux1, mux2
+none; -
+pack; pack2, pack4
+padd; padd1, padd2, padd4
+pavg; pavg1, pavg2
+pavgsub; pavgsub1, pavgsub2
+pcmp; pcmp1, pcmp2, pcmp4
+pmax; pmax1, pmax2
+pmin; pmin1, pmin2
+pmpy; pmpy2
+pmpyshr; pmpyshr2
+pr-and-writers; IC:pr-gen-writers-int[Field(ctype) in {and andcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}]
+pr-gen-writers-fp; fclass, fcmp
+pr-gen-writers-int; cmp, cmp4, tbit, tnat
+pr-norm-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==]
+pr-norm-writers-int; IC:pr-gen-writers-int[Field(ctype)==]
+pr-or-writers; IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}]
+pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, break, nop.b, nop, IC:ReservedBQP
+pr-readers-nobr-nomovpr; add, addp4, and, andcm, break.f, break.i, break.m, break.x, break, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-immediate, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, nop, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak,
\ No newline at end of file
--- /dev/null
+/* ia64-opc-a.c -- IA-64 `A' opcode table.
+ Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 2, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+#include "ia64-opc.h"
+
+#define A IA64_TYPE_A, 1
+#define A2 IA64_TYPE_A, 2
+
+/* instruction bit fields: */
+#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12)
+#define bImm14(x) ((((ia64_insn) (((x) >> 0) & 0x7f)) << 13) | \
+ (((ia64_insn) (((x) >> 7) & 0x3f)) << 27) | \
+ (((ia64_insn) (((x) >> 13) & 0x01)) << 36))
+#define bR3a(x) (((ia64_insn) ((x) & 0x7f)) << 20)
+#define bR3b(x) (((ia64_insn) ((x) & 0x3)) << 20)
+#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33)
+#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36)
+#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 33)
+#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33)
+#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
+#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34)
+#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 27)
+#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 29)
+#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36)
+#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33)
+
+/* instruction bit masks: */
+#define mC bC (-1)
+#define mImm14 bImm14 (-1)
+#define mR3a bR3a (-1)
+#define mR3b bR3b (-1)
+#define mTa bTa (-1)
+#define mTb bTb (-1)
+#define mVe bVe (-1)
+#define mX bX (-1)
+#define mX2 bX2 (-1)
+#define mX2a bX2a (-1)
+#define mX2b bX2b (-1)
+#define mX4 bX4 (-1)
+#define mZa bZa (-1)
+#define mZb bZb (-1)
+
+#define OpR3b(a,b) (bOp (a) | bR3b (b)), (mOp | mR3b)
+#define OpX2aVe(a,b,c) (bOp (a) | bX2a (b) | bVe (c)), \
+ (mOp | mX2a | mVe)
+#define OpX2aVeR3a(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \
+ (mOp | mX2a | mVe | mR3a)
+#define OpX2aVeImm14(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \
+ (mOp | mX2a | mVe | mImm14)
+#define OpX2aVeX4(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \
+ (mOp | mX2a | mVe | mX4)
+#define OpX2aVeX4X2b(a,b,c,d,e) \
+ (bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \
+ (mOp | mX2a | mVe | mX4 | mX2b)
+#define OpX2TbTaC(a,b,c,d,e) \
+ (bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \
+ (mOp | mX2 | mTb | mTa | mC)
+#define OpX2TaC(a,b,c,d) (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \
+ (mOp | mX2 | mTa | mC)
+#define OpX2aZaZbX4(a,b,c,d,e) \
+ (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \
+ (mOp | mX2a | mZa | mZb | mX4)
+#define OpX2aZaZbX4X2b(a,b,c,d,e,f) \
+ (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \
+ (mOp | mX2a | mZa | mZb | mX4 | mX2b)
+
+struct ia64_opcode ia64_opcodes_a[] =
+ {
+ /* A-type instruction encodings (sorted according to major opcode) */
+
+ {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}},
+ {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}},
+ {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}},
+ {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}},
+ {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}},
+ {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}},
+ {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}},
+ {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}},
+ {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}},
+ {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}},
+ {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}},
+ {"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}},
+ {"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}},
+ {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}},
+ {"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}},
+ {"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}},
+ {"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}},
+ {"mov", A, OpX2aVeR3a (8, 2, 0, 0), {R1, IMM14}, PSEUDO},
+ {"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}},
+ {"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}},
+ {"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}},
+ {"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}},
+ {"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}},
+ {"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}},
+ {"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}},
+ {"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}},
+ {"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}},
+ {"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}},
+ {"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}},
+ {"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}},
+ {"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}},
+ {"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}},
+ {"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}},
+ {"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}},
+ {"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}},
+ {"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}},
+ {"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}},
+ {"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}},
+ {"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}},
+ {"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}},
+ {"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}},
+ {"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}},
+ {"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}},
+ {"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}},
+ {"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}},
+ {"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}},
+ {"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}},
+ {"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}},
+ {"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}},
+ {"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}},
+ {"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}},
+ {"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}},
+
+ {"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO},
+ {"addl", A, Op (9), {R1, IMM22, R3_2}},
+
+ {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}},
+ {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}},
+ {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}},
+ {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}},
+ {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}},
+ {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}},
+ {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}},
+ {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}},
+ {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}},
+ {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
+ {"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}},
+ {"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
+ {"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}},
+ {"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}},
+ {"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}},
+ {"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}},
+ {"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}},
+ {"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}},
+ {"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}},
+ {"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}},
+ {"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}},
+ {"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
+ {"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}},
+ {"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
+ {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}},
+ {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}},
+ {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}},
+ {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}},
+ {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}},
+ {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}},
+ {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}},
+ {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}},
+ {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}},
+ {"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}},
+ {"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}},
+ {"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}},
+ {"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}},
+ {"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}},
+ {"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}},
+ {"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}},
+ {"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}},
+ {"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
+ {"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}},
+ {"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
+ {"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}},
+ {"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}},
+ {"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}},
+ {"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}},
+ {"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}},
+ {"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}},
+ {"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}},
+ {"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}},
+ {"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}},
+ {"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
+ {"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}},
+ {"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
+ {"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}},
+ {"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}},
+ {"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}},
+ {"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}},
+ {"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}},
+ {"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}},
+ {"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}},
+ {"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}},
+ {"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}},
+ {"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
+ {"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}},
+ {"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
+ {"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}},
+ {"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}},
+ {"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}},
+ {"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}},
+ {"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}},
+ {"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}},
+ {"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}},
+ {"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}},
+ {"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}},
+ {"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
+ {"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}},
+ {"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
+ {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}},
+ {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}},
+ {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}},
+ {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}},
+ {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}},
+ {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}},
+ {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}},
+ {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}},
+ {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
+ {"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}},
+ {"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}},
+ {"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}},
+ {"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}},
+ {"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}},
+ {"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}},
+ {"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}},
+ {"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}},
+ {"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}},
+ {"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
+ {"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}},
+ {"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
+ {"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}},
+ {"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}},
+ {"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}},
+ {"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}},
+ {"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}},
+ {"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}},
+ {"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}},
+ {"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}},
+ {"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}},
+ {"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
+ {"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}},
+ {"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
+ {"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}},
+ {"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}},
+ {"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}},
+ {"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}},
+ {"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}},
+ {"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO},
+ {"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}},
+ {"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO},
+ {"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}},
+ {"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}},
+ {"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}},
+ {"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}},
+ {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}},
+ {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO},
+ {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}},
+ {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO},
+ {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}},
+ {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO},
+ {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}},
+ {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO},
+ {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}},
+ {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO},
+ {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}},
+ {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO},
+ {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}},
+ {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO},
+ {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}},
+ {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO},
+ {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}},
+ {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO},
+ {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}},
+ {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO},
+ {"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}},
+ {"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}},
+ {"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}},
+ {"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}},
+ {"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3}},
+ {"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO},
+ {"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3}},
+ {"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO},
+ {"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}},
+ {"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}},
+ {"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}},
+ {"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}},
+ {"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3}},
+ {"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO},
+ {"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3}},
+ {"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO},
+
+ {0}
+ };
+
+#undef A
+#undef A2
+#undef bC
+#undef bImm14
+#undef bR3a
+#undef bR3b
+#undef bTa
+#undef bTb
+#undef bVe
+#undef bX
+#undef bX2
+#undef bX2a
+#undef bX2b
+#undef bX4
+#undef bZa
+#undef bZb
+#undef mC
+#undef mImm14
+#undef mR3a
+#undef mR3b
+#undef mTa
+#undef mTb
+#undef mVe
+#undef mX
+#undef mX2
+#undef mX2a
+#undef mX2b
+#undef mX4
+#undef mZa
+#undef mZb
+#undef OpR3a
+#undef OpR3b
+#undef OpX2aVe
+#undef OpX2aVeImm14
+#undef OpX2aVeX4
+#undef OpX2aVeX4X2b
+#undef OpX2TbTaC
+#undef OpX2TaC
+#undef OpX2aZaZbX4
+#undef OpX2aZaZbX4X2b
--- /dev/null
+/* ia64-opc-b.c -- IA-64 `B' opcode table.
+ Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 2, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+#include "ia64-opc.h"
+
+#define B0 IA64_TYPE_B, 0
+#define B IA64_TYPE_B, 1
+
+/* instruction bit fields: */
+#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6)
+#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35)
+#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 35)
+#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12)
+#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0)
+#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33)
+#define bWhb(x) (((ia64_insn) ((x) & 0x3)) << 3)
+#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
+
+#define mBtype bBtype (-1)
+#define mD bD (-1)
+#define mIh bIh (-1)
+#define mPa bPa (-1)
+#define mPr bPr (-1)
+#define mWha bWha (-1)
+#define mWhb bWhb (-1)
+#define mX6 bX6 (-1)
+
+#define OpX6(a,b) (bOp (a) | bX6 (b)), (mOp | mX6)
+#define OpPaWhaD(a,b,c,d) \
+ (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD)
+#define OpBtypePaWhaD(a,b,c,d,e) \
+ (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \
+ (mOp | mBtype | mPa | mWha | mD)
+#define OpBtypePaWhaDPr(a,b,c,d,e,f) \
+ (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \
+ (mOp | mBtype | mPa | mWha | mD | mPr)
+#define OpX6BtypePaWhaD(a,b,c,d,e,f) \
+ (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f)), \
+ (mOp | mX6 | mBtype | mPa | mWha | mD)
+#define OpX6BtypePaWhaDPr(a,b,c,d,e,f,g) \
+ (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f) | bPr (g)), \
+ (mOp | mX6 | mBtype | mPa | mWha | mD | mPr)
+#define OpIhWhb(a,b,c) \
+ (bOp (a) | bIh (b) | bWhb (c)), \
+ (mOp | mIh | mWhb)
+#define OpX6IhWhb(a,b,c,d) \
+ (bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \
+ (mOp | mX6 | mIh | mWhb)
+
+struct ia64_opcode ia64_opcodes_b[] =
+ {
+ /* B-type instruction encodings (sorted according to major opcode) */
+
+#define BR(a,b) \
+ B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO
+ {"br.few", BR (0, 0)},
+ {"br", BR (0, 0)},
+ {"br.few.clr", BR (0, 1)},
+ {"br.clr", BR (0, 1)},
+ {"br.many", BR (1, 0)},
+ {"br.many.clr", BR (1, 1)},
+#undef BR
+
+#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}
+ {"br.cond.sptk.few", BR (0x20, 0, 0, 0, 0)},
+ {"br.cond.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO},
+ {"br.cond.sptk.few.clr", BR (0x20, 0, 0, 0, 1)},
+ {"br.cond.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO},
+ {"br.cond.spnt.few", BR (0x20, 0, 0, 1, 0)},
+ {"br.cond.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO},
+ {"br.cond.spnt.few.clr", BR (0x20, 0, 0, 1, 1)},
+ {"br.cond.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO},
+ {"br.cond.dptk.few", BR (0x20, 0, 0, 2, 0)},
+ {"br.cond.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO},
+ {"br.cond.dptk.few.clr", BR (0x20, 0, 0, 2, 1)},
+ {"br.cond.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO},
+ {"br.cond.dpnt.few", BR (0x20, 0, 0, 3, 0)},
+ {"br.cond.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO},
+ {"br.cond.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)},
+ {"br.cond.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO},
+ {"br.cond.sptk.many", BR (0x20, 0, 1, 0, 0)},
+ {"br.cond.sptk.many.clr", BR (0x20, 0, 1, 0, 1)},
+ {"br.cond.spnt.many", BR (0x20, 0, 1, 1, 0)},
+ {"br.cond.spnt.many.clr", BR (0x20, 0, 1, 1, 1)},
+ {"br.cond.dptk.many", BR (0x20, 0, 1, 2, 0)},
+ {"br.cond.dptk.many.clr", BR (0x20, 0, 1, 2, 1)},
+ {"br.cond.dpnt.many", BR (0x20, 0, 1, 3, 0)},
+ {"br.cond.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)},
+ {"br.sptk.few", BR (0x20, 0, 0, 0, 0)},
+ {"br.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO},
+ {"br.sptk.few.clr", BR (0x20, 0, 0, 0, 1)},
+ {"br.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO},
+ {"br.spnt.few", BR (0x20, 0, 0, 1, 0)},
+ {"br.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO},
+ {"br.spnt.few.clr", BR (0x20, 0, 0, 1, 1)},
+ {"br.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO},
+ {"br.dptk.few", BR (0x20, 0, 0, 2, 0)},
+ {"br.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO},
+ {"br.dptk.few.clr", BR (0x20, 0, 0, 2, 1)},
+ {"br.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO},
+ {"br.dpnt.few", BR (0x20, 0, 0, 3, 0)},
+ {"br.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO},
+ {"br.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)},
+ {"br.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO},
+ {"br.sptk.many", BR (0x20, 0, 1, 0, 0)},
+ {"br.sptk.many.clr", BR (0x20, 0, 1, 0, 1)},
+ {"br.spnt.many", BR (0x20, 0, 1, 1, 0)},
+ {"br.spnt.many.clr", BR (0x20, 0, 1, 1, 1)},
+ {"br.dptk.many", BR (0x20, 0, 1, 2, 0)},
+ {"br.dptk.many.clr", BR (0x20, 0, 1, 2, 1)},
+ {"br.dpnt.many", BR (0x20, 0, 1, 3, 0)},
+ {"br.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)},
+ {"br.ia.sptk.few", BR (0x20, 1, 0, 0, 0)},
+ {"br.ia.sptk", BR (0x20, 1, 0, 0, 0), PSEUDO},
+ {"br.ia.sptk.few.clr", BR (0x20, 1, 0, 0, 1)},
+ {"br.ia.sptk.clr", BR (0x20, 1, 0, 0, 1), PSEUDO},
+ {"br.ia.spnt.few", BR (0x20, 1, 0, 1, 0)},
+ {"br.ia.spnt", BR (0x20, 1, 0, 1, 0), PSEUDO},
+ {"br.ia.spnt.few.clr", BR (0x20, 1, 0, 1, 1)},
+ {"br.ia.spnt.clr", BR (0x20, 1, 0, 1, 1), PSEUDO},
+ {"br.ia.dptk.few", BR (0x20, 1, 0, 2, 0)},
+ {"br.ia.dptk", BR (0x20, 1, 0, 2, 0), PSEUDO},
+ {"br.ia.dptk.few.clr", BR (0x20, 1, 0, 2, 1)},
+ {"br.ia.dptk.clr", BR (0x20, 1, 0, 2, 1), PSEUDO},
+ {"br.ia.dpnt.few", BR (0x20, 1, 0, 3, 0)},
+ {"br.ia.dpnt", BR (0x20, 1, 0, 3, 0), PSEUDO},
+ {"br.ia.dpnt.few.clr", BR (0x20, 1, 0, 3, 1)},
+ {"br.ia.dpnt.clr", BR (0x20, 1, 0, 3, 1), PSEUDO},
+ {"br.ia.sptk.many", BR (0x20, 1, 1, 0, 0)},
+ {"br.ia.sptk.many.clr", BR (0x20, 1, 1, 0, 1)},
+ {"br.ia.spnt.many", BR (0x20, 1, 1, 1, 0)},
+ {"br.ia.spnt.many.clr", BR (0x20, 1, 1, 1, 1)},
+ {"br.ia.dptk.many", BR (0x20, 1, 1, 2, 0)},
+ {"br.ia.dptk.many.clr", BR (0x20, 1, 1, 2, 1)},
+ {"br.ia.dpnt.many", BR (0x20, 1, 1, 3, 0)},
+ {"br.ia.dpnt.many.clr", BR (0x20, 1, 1, 3, 1)},
+ {"br.ret.sptk.few", BR (0x21, 4, 0, 0, 0), MOD_RRBS},
+ {"br.ret.sptk", BR (0x21, 4, 0, 0, 0), PSEUDO | MOD_RRBS},
+ {"br.ret.sptk.few.clr", BR (0x21, 4, 0, 0, 1), MOD_RRBS},
+ {"br.ret.sptk.clr", BR (0x21, 4, 0, 0, 1), PSEUDO | MOD_RRBS},
+ {"br.ret.spnt.few", BR (0x21, 4, 0, 1, 0), MOD_RRBS},
+ {"br.ret.spnt", BR (0x21, 4, 0, 1, 0), PSEUDO | MOD_RRBS},
+ {"br.ret.spnt.few.clr", BR (0x21, 4, 0, 1, 1), MOD_RRBS},
+ {"br.ret.spnt.clr", BR (0x21, 4, 0, 1, 1), PSEUDO | MOD_RRBS},
+ {"br.ret.dptk.few", BR (0x21, 4, 0, 2, 0), MOD_RRBS},
+ {"br.ret.dptk", BR (0x21, 4, 0, 2, 0), PSEUDO | MOD_RRBS},
+ {"br.ret.dptk.few.clr", BR (0x21, 4, 0, 2, 1), MOD_RRBS},
+ {"br.ret.dptk.clr", BR (0x21, 4, 0, 2, 1), PSEUDO | MOD_RRBS},
+ {"br.ret.dpnt.few", BR (0x21, 4, 0, 3, 0), MOD_RRBS},
+ {"br.ret.dpnt", BR (0x21, 4, 0, 3, 0), PSEUDO | MOD_RRBS},
+ {"br.ret.dpnt.few.clr", BR (0x21, 4, 0, 3, 1), MOD_RRBS},
+ {"br.ret.dpnt.clr", BR (0x21, 4, 0, 3, 1), PSEUDO | MOD_RRBS},
+ {"br.ret.sptk.many", BR (0x21, 4, 1, 0, 0), MOD_RRBS},
+ {"br.ret.sptk.many.clr", BR (0x21, 4, 1, 0, 1), MOD_RRBS},
+ {"br.ret.spnt.many", BR (0x21, 4, 1, 1, 0), MOD_RRBS},
+ {"br.ret.spnt.many.clr", BR (0x21, 4, 1, 1, 1), MOD_RRBS},
+ {"br.ret.dptk.many", BR (0x21, 4, 1, 2, 0), MOD_RRBS},
+ {"br.ret.dptk.many.clr", BR (0x21, 4, 1, 2, 1), MOD_RRBS},
+ {"br.ret.dpnt.many", BR (0x21, 4, 1, 3, 0), MOD_RRBS},
+ {"br.ret.dpnt.many.clr", BR (0x21, 4, 1, 3, 1), MOD_RRBS},
+#undef BR
+
+ {"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS},
+ {"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS},
+ {"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS},
+ {"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS},
+ {"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV},
+ {"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV},
+ {"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED},
+
+ {"break.b", B0, OpX6 (0, 0x00), {IMMU21}},
+
+ {"br.call.sptk.few", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}},
+ {"br.call.sptk", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}, PSEUDO},
+ {"br.call.sptk.few.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}},
+ {"br.call.sptk.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}, PSEUDO},
+ {"br.call.spnt.few", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}},
+ {"br.call.spnt", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}, PSEUDO},
+ {"br.call.spnt.few.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}},
+ {"br.call.spnt.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}, PSEUDO},
+ {"br.call.dptk.few", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}},
+ {"br.call.dptk", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}, PSEUDO},
+ {"br.call.dptk.few.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}},
+ {"br.call.dptk.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}, PSEUDO},
+ {"br.call.dpnt.few", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}},
+ {"br.call.dpnt", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}, PSEUDO},
+ {"br.call.dpnt.few.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}},
+ {"br.call.dpnt.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}, PSEUDO},
+ {"br.call.sptk.many", B, OpPaWhaD (1, 1, 0, 0), {B1, B2}},
+ {"br.call.sptk.many.clr", B, OpPaWhaD (1, 1, 0, 1), {B1, B2}},
+ {"br.call.spnt.many", B, OpPaWhaD (1, 1, 1, 0), {B1, B2}},
+ {"br.call.spnt.many.clr", B, OpPaWhaD (1, 1, 1, 1), {B1, B2}},
+ {"br.call.dptk.many", B, OpPaWhaD (1, 1, 2, 0), {B1, B2}},
+ {"br.call.dptk.many.clr", B, OpPaWhaD (1, 1, 2, 1), {B1, B2}},
+ {"br.call.dpnt.many", B, OpPaWhaD (1, 1, 3, 0), {B1, B2}},
+ {"br.call.dpnt.many.clr", B, OpPaWhaD (1, 1, 3, 1), {B1, B2}},
+
+#define BRP(a,b,c) \
+ B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED
+ {"brp.sptk", BRP (0x10, 0, 0)},
+ {"brp.dptk", BRP (0x10, 0, 2)},
+ {"brp.sptk.imp", BRP (0x10, 1, 0)},
+ {"brp.dptk.imp", BRP (0x10, 1, 2)},
+ {"brp.ret.sptk", BRP (0x11, 0, 0)},
+ {"brp.ret.dptk", BRP (0x11, 0, 2)},
+ {"brp.ret.sptk.imp", BRP (0x11, 1, 0)},
+ {"brp.ret.dptk.imp", BRP (0x11, 1, 2)},
+#undef BRP
+
+ {"nop.b", B0, OpX6 (2, 0x00), {IMMU21}},
+
+#define BR(a,b) \
+ B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO
+ {"br.few", BR (0, 0)},
+ {"br", BR (0, 0)},
+ {"br.few.clr", BR (0, 1)},
+ {"br.clr", BR (0, 1)},
+ {"br.many", BR (1, 0)},
+ {"br.many.clr", BR (1, 1)},
+#undef BR
+
+ {"br.cond.sptk.few", B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}},
+ {"br.cond.sptk", B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}, PSEUDO},
+ {"br.cond.sptk.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}},
+ {"br.cond.sptk.clr", B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}, PSEUDO},
+ {"br.cond.spnt.few", B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}},
+ {"br.cond.spnt", B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}, PSEUDO},
+ {"br.cond.spnt.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}},
+ {"br.cond.spnt.clr", B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}, PSEUDO},
+ {"br.cond.dptk.few", B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}},
+ {"br.cond.dptk", B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}, PSEUDO},
+ {"br.cond.dptk.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}},
+ {"br.cond.dptk.clr", B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}, PSEUDO},
+ {"br.cond.dpnt.few", B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}},
+ {"br.cond.dpnt", B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}, PSEUDO},
+ {"br.cond.dpnt.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}},
+ {"br.cond.dpnt.clr", B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}, PSEUDO},
+ {"br.cond.sptk.many", B0, OpBtypePaWhaD (4, 0, 1, 0, 0), {TGT25c}},
+ {"br.cond.sptk.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 0, 1), {TGT25c}},
+ {"br.cond.spnt.many", B0, OpBtypePaWhaD (4, 0, 1, 1, 0), {TGT25c}},
+ {"br.cond.spnt.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 1, 1), {TGT25c}},
+ {"br.cond.dptk.many", B0, OpBtypePaWhaD (4, 0, 1, 2, 0), {TGT25c}},
+ {"br.cond.dptk.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 2, 1), {TGT25c}},
+ {"br.cond.dpnt.many", B0, OpBtypePaWhaD (4, 0, 1, 3, 0), {TGT25c}},
+ {"br.cond.dpnt.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 3, 1), {TGT25c}},
+ {"br.sptk.few", B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}},
+ {"br.sptk", B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}, PSEUDO},
+ {"br.sptk.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}},
+ {"br.sptk.clr", B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}, PSEUDO},
+ {"br.spnt.few", B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}},
+ {"br.spnt", B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}, PSEUDO},
+ {"br.spnt.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}},
+ {"br.spnt.clr", B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}, PSEUDO},
+ {"br.dptk.few", B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}},
+ {"br.dptk", B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}, PSEUDO},
+ {"br.dptk.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}},
+ {"br.dptk.clr", B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}, PSEUDO},
+ {"br.dpnt.few", B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}},
+ {"br.dpnt", B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}, PSEUDO},
+ {"br.dpnt.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}},
+ {"br.dpnt.clr", B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}, PSEUDO},
+ {"br.sptk.many", B0, OpBtypePaWhaD (4, 0, 1, 0, 0), {TGT25c}},
+ {"br.sptk.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 0, 1), {TGT25c}},
+ {"br.spnt.many", B0, OpBtypePaWhaD (4, 0, 1, 1, 0), {TGT25c}},
+ {"br.spnt.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 1, 1), {TGT25c}},
+ {"br.dptk.many", B0, OpBtypePaWhaD (4, 0, 1, 2, 0), {TGT25c}},
+ {"br.dptk.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 2, 1), {TGT25c}},
+ {"br.dpnt.many", B0, OpBtypePaWhaD (4, 0, 1, 3, 0), {TGT25c}},
+ {"br.dpnt.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 3, 1), {TGT25c}},
+
+#define BR(a,b,c,d) \
+ B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2
+ {"br.wexit.sptk.few", BR (2, 0, 0, 0) | MOD_RRBS},
+ {"br.wexit.sptk", BR (2, 0, 0, 0) | PSEUDO | MOD_RRBS},
+ {"br.wexit.sptk.few.clr", BR (2, 0, 0, 1) | MOD_RRBS},
+ {"br.wexit.sptk.clr", BR (2, 0, 0, 1) | PSEUDO | MOD_RRBS},
+ {"br.wexit.spnt.few", BR (2, 0, 1, 0) | MOD_RRBS},
+ {"br.wexit.spnt", BR (2, 0, 1, 0) | PSEUDO | MOD_RRBS},
+ {"br.wexit.spnt.few.clr", BR (2, 0, 1, 1) | MOD_RRBS},
+ {"br.wexit.spnt.clr", BR (2, 0, 1, 1) | PSEUDO | MOD_RRBS},
+ {"br.wexit.dptk.few", BR (2, 0, 2, 0) | MOD_RRBS},
+ {"br.wexit.dptk", BR (2, 0, 2, 0) | PSEUDO | MOD_RRBS},
+ {"br.wexit.dptk.few.clr", BR (2, 0, 2, 1) | MOD_RRBS},
+ {"br.wexit.dptk.clr", BR (2, 0, 2, 1) | PSEUDO | MOD_RRBS},
+ {"br.wexit.dpnt.few", BR (2, 0, 3, 0) | MOD_RRBS},
+ {"br.wexit.dpnt", BR (2, 0, 3, 0) | PSEUDO | MOD_RRBS},
+ {"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1) | MOD_RRBS},
+ {"br.wexit.dpnt.clr", BR (2, 0, 3, 1) | PSEUDO | MOD_RRBS},
+ {"br.wexit.sptk.many", BR (2, 1, 0, 0) | MOD_RRBS},
+ {"br.wexit.sptk.many.clr", BR (2, 1, 0, 1) | MOD_RRBS},
+ {"br.wexit.spnt.many", BR (2, 1, 1, 0) | MOD_RRBS},
+ {"br.wexit.spnt.many.clr", BR (2, 1, 1, 1) | MOD_RRBS},
+ {"br.wexit.dptk.many", BR (2, 1, 2, 0) | MOD_RRBS},
+ {"br.wexit.dptk.many.clr", BR (2, 1, 2, 1) | MOD_RRBS},
+ {"br.wexit.dpnt.many", BR (2, 1, 3, 0) | MOD_RRBS},
+ {"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1) | MOD_RRBS},
+ {"br.wtop.sptk.few", BR (3, 0, 0, 0) | MOD_RRBS},
+ {"br.wtop.sptk", BR (3, 0, 0, 0) | PSEUDO | MOD_RRBS},
+ {"br.wtop.sptk.few.clr", BR (3, 0, 0, 1) | MOD_RRBS},
+ {"br.wtop.sptk.clr", BR (3, 0, 0, 1) | PSEUDO | MOD_RRBS},
+ {"br.wtop.spnt.few", BR (3, 0, 1, 0) | MOD_RRBS},
+ {"br.wtop.spnt", BR (3, 0, 1, 0) | PSEUDO | MOD_RRBS},
+ {"br.wtop.spnt.few.clr", BR (3, 0, 1, 1) | MOD_RRBS},
+ {"br.wtop.spnt.clr", BR (3, 0, 1, 1) | PSEUDO | MOD_RRBS},
+ {"br.wtop.dptk.few", BR (3, 0, 2, 0) | MOD_RRBS},
+ {"br.wtop.dptk", BR (3, 0, 2, 0) | PSEUDO | MOD_RRBS},
+ {"br.wtop.dptk.few.clr", BR (3, 0, 2, 1) | MOD_RRBS},
+ {"br.wtop.dptk.clr", BR (3, 0, 2, 1) | PSEUDO | MOD_RRBS},
+ {"br.wtop.dpnt.few", BR (3, 0, 3, 0) | MOD_RRBS},
+ {"br.wtop.dpnt", BR (3, 0, 3, 0) | PSEUDO | MOD_RRBS},
+ {"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1) | MOD_RRBS},
+ {"br.wtop.dpnt.clr", BR (3, 0, 3, 1) | PSEUDO | MOD_RRBS},
+ {"br.wtop.sptk.many", BR (3, 1, 0, 0) | MOD_RRBS},
+ {"br.wtop.sptk.many.clr", BR (3, 1, 0, 1) | MOD_RRBS},
+ {"br.wtop.spnt.many", BR (3, 1, 1, 0) | MOD_RRBS},
+ {"br.wtop.spnt.many.clr", BR (3, 1, 1, 1) | MOD_RRBS},
+ {"br.wtop.dptk.many", BR (3, 1, 2, 0) | MOD_RRBS},
+ {"br.wtop.dptk.many.clr", BR (3, 1, 2, 1) | MOD_RRBS},
+ {"br.wtop.dpnt.many", BR (3, 1, 3, 0) | MOD_RRBS},
+ {"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1) | MOD_RRBS},
+
+#undef BR
+#define BR(a,b,c,d) \
+ B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED
+ {"br.cloop.sptk.few", BR (5, 0, 0, 0)},
+ {"br.cloop.sptk", BR (5, 0, 0, 0) | PSEUDO},
+ {"br.cloop.sptk.few.clr", BR (5, 0, 0, 1)},
+ {"br.cloop.sptk.clr", BR (5, 0, 0, 1) | PSEUDO},
+ {"br.cloop.spnt.few", BR (5, 0, 1, 0)},
+ {"br.cloop.spnt", BR (5, 0, 1, 0) | PSEUDO},
+ {"br.cloop.spnt.few.clr", BR (5, 0, 1, 1)},
+ {"br.cloop.spnt.clr", BR (5, 0, 1, 1) | PSEUDO},
+ {"br.cloop.dptk.few", BR (5, 0, 2, 0)},
+ {"br.cloop.dptk", BR (5, 0, 2, 0) | PSEUDO},
+ {"br.cloop.dptk.few.clr", BR (5, 0, 2, 1)},
+ {"br.cloop.dptk.clr", BR (5, 0, 2, 1) | PSEUDO},
+ {"br.cloop.dpnt.few", BR (5, 0, 3, 0)},
+ {"br.cloop.dpnt", BR (5, 0, 3, 0) | PSEUDO},
+ {"br.cloop.dpnt.few.clr", BR (5, 0, 3, 1)},
+ {"br.cloop.dpnt.clr", BR (5, 0, 3, 1) | PSEUDO},
+ {"br.cloop.sptk.many", BR (5, 1, 0, 0)},
+ {"br.cloop.sptk.many.clr", BR (5, 1, 0, 1)},
+ {"br.cloop.spnt.many", BR (5, 1, 1, 0)},
+ {"br.cloop.spnt.many.clr", BR (5, 1, 1, 1)},
+ {"br.cloop.dptk.many", BR (5, 1, 2, 0)},
+ {"br.cloop.dptk.many.clr", BR (5, 1, 2, 1)},
+ {"br.cloop.dpnt.many", BR (5, 1, 3, 0)},
+ {"br.cloop.dpnt.many.clr", BR (5, 1, 3, 1)},
+ {"br.cexit.sptk.few", BR (6, 0, 0, 0) | MOD_RRBS},
+ {"br.cexit.sptk", BR (6, 0, 0, 0) | PSEUDO | MOD_RRBS},
+ {"br.cexit.sptk.few.clr", BR (6, 0, 0, 1) | MOD_RRBS},
+ {"br.cexit.sptk.clr", BR (6, 0, 0, 1) | PSEUDO | MOD_RRBS},
+ {"br.cexit.spnt.few", BR (6, 0, 1, 0) | MOD_RRBS},
+ {"br.cexit.spnt", BR (6, 0, 1, 0) | PSEUDO | MOD_RRBS},
+ {"br.cexit.spnt.few.clr", BR (6, 0, 1, 1) | MOD_RRBS},
+ {"br.cexit.spnt.clr", BR (6, 0, 1, 1) | PSEUDO | MOD_RRBS},
+ {"br.cexit.dptk.few", BR (6, 0, 2, 0) | MOD_RRBS},
+ {"br.cexit.dptk", BR (6, 0, 2, 0) | PSEUDO | MOD_RRBS},
+ {"br.cexit.dptk.few.clr", BR (6, 0, 2, 1) | MOD_RRBS},
+ {"br.cexit.dptk.clr", BR (6, 0, 2, 1) | PSEUDO | MOD_RRBS},
+ {"br.cexit.dpnt.few", BR (6, 0, 3, 0) | MOD_RRBS},
+ {"br.cexit.dpnt", BR (6, 0, 3, 0) | PSEUDO | MOD_RRBS},
+ {"br.cexit.dpnt.few.clr", BR (6, 0, 3, 1) | MOD_RRBS},
+ {"br.cexit.dpnt.clr", BR (6, 0, 3, 1) | PSEUDO | MOD_RRBS},
+ {"br.cexit.sptk.many", BR (6, 1, 0, 0) | MOD_RRBS},
+ {"br.cexit.sptk.many.clr", BR (6, 1, 0, 1) | MOD_RRBS},
+ {"br.cexit.spnt.many", BR (6, 1, 1, 0) | MOD_RRBS},
+ {"br.cexit.spnt.many.clr", BR (6, 1, 1, 1) | MOD_RRBS},
+ {"br.cexit.dptk.many", BR (6, 1, 2, 0) | MOD_RRBS},
+ {"br.cexit.dptk.many.clr", BR (6, 1, 2, 1) | MOD_RRBS},
+ {"br.cexit.dpnt.many", BR (6, 1, 3, 0) | MOD_RRBS},
+ {"br.cexit.dpnt.many.clr", BR (6, 1, 3, 1) | MOD_RRBS},
+ {"br.ctop.sptk.few", BR (7, 0, 0, 0) | MOD_RRBS},
+ {"br.ctop.sptk", BR (7, 0, 0, 0) | PSEUDO | MOD_RRBS},
+ {"br.ctop.sptk.few.clr", BR (7, 0, 0, 1) | MOD_RRBS},
+ {"br.ctop.sptk.clr", BR (7, 0, 0, 1) | PSEUDO | MOD_RRBS},
+ {"br.ctop.spnt.few", BR (7, 0, 1, 0) | MOD_RRBS},
+ {"br.ctop.spnt", BR (7, 0, 1, 0) | PSEUDO | MOD_RRBS},
+ {"br.ctop.spnt.few.clr", BR (7, 0, 1, 1) | MOD_RRBS},
+ {"br.ctop.spnt.clr", BR (7, 0, 1, 1) | PSEUDO | MOD_RRBS},
+ {"br.ctop.dptk.few", BR (7, 0, 2, 0) | MOD_RRBS},
+ {"br.ctop.dptk", BR (7, 0, 2, 0) | PSEUDO | MOD_RRBS},
+ {"br.ctop.dptk.few.clr", BR (7, 0, 2, 1) | MOD_RRBS},
+ {"br.ctop.dptk.clr", BR (7, 0, 2, 1) | PSEUDO | MOD_RRBS},
+ {"br.ctop.dpnt.few", BR (7, 0, 3, 0) | MOD_RRBS},
+ {"br.ctop.dpnt", BR (7, 0, 3, 0) | PSEUDO | MOD_RRBS},
+ {"br.ctop.dpnt.few.clr", BR (7, 0, 3, 1) | MOD_RRBS},
+ {"br.ctop.dpnt.clr", BR (7, 0, 3, 1) | PSEUDO | MOD_RRBS},
+ {"br.ctop.sptk.many", BR (7, 1, 0, 0) | MOD_RRBS},
+ {"br.ctop.sptk.many.clr", BR (7, 1, 0, 1) | MOD_RRBS},
+ {"br.ctop.spnt.many", BR (7, 1, 1, 0) | MOD_RRBS},
+ {"br.ctop.spnt.many.clr", BR (7, 1, 1, 1) | MOD_RRBS},
+ {"br.ctop.dptk.many", BR (7, 1, 2, 0) | MOD_RRBS},
+ {"br.ctop.dptk.many.clr", BR (7, 1, 2, 1) | MOD_RRBS},
+ {"br.ctop.dpnt.many", BR (7, 1, 3, 0) | MOD_RRBS},
+ {"br.ctop.dpnt.many.clr", BR (7, 1, 3, 1) | MOD_RRBS},
+
+#undef BR
+#define BR(a,b,c,d) \
+ B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2
+ {"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}},
+ {"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO},
+ {"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}},
+ {"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO},
+ {"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}},
+ {"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO},
+ {"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}},
+ {"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO},
+ {"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}},
+ {"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO},
+ {"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}},
+ {"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO},
+ {"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}},
+ {"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO},
+ {"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}},
+ {"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO},
+ {"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}},
+ {"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}},
+ {"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}},
+ {"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}},
+ {"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}},
+ {"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}},
+ {"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}},
+ {"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}},
+#undef BR
+
+ /* branch predict */
+#define BRP(a,b) \
+ B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED
+ {"brp.sptk", BRP (0, 0)},
+ {"brp.loop", BRP (0, 1)},
+ {"brp.dptk", BRP (0, 2)},
+ {"brp.exit", BRP (0, 3)},
+ {"brp.sptk.imp", BRP (1, 0)},
+ {"brp.loop.imp", BRP (1, 1)},
+ {"brp.dptk.imp", BRP (1, 2)},
+ {"brp.exit.imp", BRP (1, 3)},
+#undef BRP
+
+ {0}
+ };
+
+#undef B0
+#undef B
+#undef bBtype
+#undef bD
+#undef bIh
+#undef bPa
+#undef bPr
+#undef bWha
+#undef bWhb
+#undef bX6
+#undef mBtype
+#undef mD
+#undef mIh
+#undef mPa
+#undef mPr
+#undef mWha
+#undef mWhb
+#undef mX6
+#undef OpX6
+#undef OpPaWhaD
+#undef OpBtypePaWhaD
+#undef OpBtypePaWhaDPr
+#undef OpX6BtypePaWhaD
+#undef OpX6BtypePaWhaDPr
+#undef OpIhWhb
+#undef OpX6IhWhb
--- /dev/null
+struct ia64_opcode ia64_opcodes_d[] =
+ {
+ {"add", IA64_TYPE_DYN, 1, 0, 0,
+ {IA64_OPND_R1, IA64_OPND_IMM22, IA64_OPND_R3}},
+ {"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}},
+ {"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}},
+ {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}},
+ {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}},
+ {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}},
+ {"nop", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}},
+ {0}
+ };
--- /dev/null
+/* ia64-opc-f.c -- IA-64 `F' opcode table.
+ Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 2, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+#include "ia64-opc.h"
+
+#define f0 IA64_TYPE_F, 0
+#define f IA64_TYPE_F, 1
+#define f2 IA64_TYPE_F, 2
+
+#define bF2(x) (((ia64_insn) ((x) & 0x7f)) << 13)
+#define bF4(x) (((ia64_insn) ((x) & 0x7f)) << 27)
+#define bQ(x) (((ia64_insn) ((x) & 0x1)) << 36)
+#define bRa(x) (((ia64_insn) ((x) & 0x1)) << 33)
+#define bRb(x) (((ia64_insn) ((x) & 0x1)) << 36)
+#define bSf(x) (((ia64_insn) ((x) & 0x3)) << 34)
+#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 12)
+#define bXa(x) (((ia64_insn) ((x) & 0x1)) << 36)
+#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33)
+#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
+#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
+
+#define mF2 bF2 (-1)
+#define mF4 bF4 (-1)
+#define mQ bQ (-1)
+#define mRa bRa (-1)
+#define mRb bRb (-1)
+#define mSf bSf (-1)
+#define mTa bTa (-1)
+#define mXa bXa (-1)
+#define mXb bXb (-1)
+#define mX2 bX2 (-1)
+#define mX6 bX6 (-1)
+
+#define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa)
+#define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf)
+#define OpXaSfF2(a,b,c,d) \
+ (bOp (a) | bXa (b) | bSf (c) | bF2 (d)), (mOp | mXa | mSf | mF2)
+#define OpXaSfF4(a,b,c,d) \
+ (bOp (a) | bXa (b) | bSf (c) | bF4 (d)), (mOp | mXa | mSf | mF4)
+#define OpXaSfF2F4(a,b,c,d,e) \
+ (bOp (a) | bXa (b) | bSf (c) | bF2 (d) | bF4 (e)), \
+ (mOp | mXa | mSf | mF2 | mF4)
+#define OpXaX2(a,b,c) (bOp (a) | bXa (b) | bX2 (c)), (mOp | mXa | mX2)
+#define OpXaX2F2(a,b,c,d) \
+ (bOp (a) | bXa (b) | bX2 (c) | bF2 (d)), (mOp | mXa | mX2 | mF2)
+#define OpRaRbTaSf(a,b,c,d,e) \
+ (bOp (a) | bRa (b) | bRb (c) | bTa (d) | bSf (e)), \
+ (mOp | mRa | mRb | mTa | mSf)
+#define OpTa(a,b) (bOp (a) | bTa (b)), (mOp | mTa)
+#define OpXbQSf(a,b,c,d) \
+ (bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf)
+#define OpXbX6(a,b,c) \
+ (bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6)
+#define OpXbX6F2(a,b,c,d) \
+ (bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2)
+#define OpXbX6Sf(a,b,c,d) \
+ (bOp (a) | bXb (b) | bX6 (c) | bSf (d)), (mOp | mXb | mX6 | mSf)
+
+struct ia64_opcode ia64_opcodes_f[] =
+ {
+ /* F-type instruction encodings (sorted according to major opcode) */
+
+ {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}},
+ {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO},
+ {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}},
+ {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}},
+ {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}},
+
+ {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}},
+ {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO},
+ {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}},
+ {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}},
+ {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}},
+
+ {"fmin.s0", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}},
+ {"fmin", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO},
+ {"fmin.s1", f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}},
+ {"fmin.s2", f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}},
+ {"fmin.s3", f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}},
+ {"fmax.s0", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}},
+ {"fmax", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO},
+ {"fmax.s1", f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}},
+ {"fmax.s2", f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}},
+ {"fmax.s3", f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}},
+ {"famin.s0", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}},
+ {"famin", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO},
+ {"famin.s1", f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}},
+ {"famin.s2", f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}},
+ {"famin.s3", f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}},
+ {"famax.s0", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}},
+ {"famax", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO},
+ {"famax.s1", f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}},
+ {"famax.s2", f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}},
+ {"famax.s3", f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}},
+
+ {"mov", f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3},
+ {"fabs", f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO},
+ {"fmerge.s", f, OpXbX6 (0, 0, 0x10), {F1, F2, F3}},
+ {"fneg", f, OpXbX6 (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3},
+ {"fnegabs", f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO},
+ {"fmerge.ns", f, OpXbX6 (0, 0, 0x11), {F1, F2, F3}},
+
+ {"fmerge.se", f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}},
+ {"fmix.lr", f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}},
+ {"fmix.r", f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}},
+ {"fmix.l", f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}},
+ {"fsxt.r", f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}},
+ {"fsxt.l", f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}},
+ {"fpack", f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}},
+ {"fswap", f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}},
+ {"fswap.nl", f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}},
+ {"fswap.nr", f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}},
+ {"fand", f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}},
+ {"fandcm", f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}},
+ {"for", f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}},
+ {"fxor", f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}},
+
+ {"fcvt.fx.s0", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}},
+ {"fcvt.fx", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO},
+ {"fcvt.fx.s1", f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}},
+ {"fcvt.fx.s2", f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}},
+ {"fcvt.fx.s3", f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}},
+ {"fcvt.fxu.s0", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}},
+ {"fcvt.fxu", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO},
+ {"fcvt.fxu.s1", f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}},
+ {"fcvt.fxu.s2", f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}},
+ {"fcvt.fxu.s3", f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}},
+ {"fcvt.fx.trunc.s0", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}},
+ {"fcvt.fx.trunc", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO},
+ {"fcvt.fx.trunc.s1", f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}},
+ {"fcvt.fx.trunc.s2", f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}},
+ {"fcvt.fx.trunc.s3", f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}},
+ {"fcvt.fxu.trunc.s0", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}},
+ {"fcvt.fxu.trunc", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO},
+ {"fcvt.fxu.trunc.s1", f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}},
+ {"fcvt.fxu.trunc.s2", f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}},
+ {"fcvt.fxu.trunc.s3", f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}},
+
+ {"fcvt.xf", f, OpXbX6 (0, 0, 0x1c), {F1, F2}},
+
+ {"fsetc.s0", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}},
+ {"fsetc", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO},
+ {"fsetc.s1", f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}},
+ {"fsetc.s2", f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}},
+ {"fsetc.s3", f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}},
+ {"fclrf.s0", f0, OpXbX6Sf (0, 0, 0x05, 0)},
+ {"fclrf", f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO},
+ {"fclrf.s1", f0, OpXbX6Sf (0, 0, 0x05, 1)},
+ {"fclrf.s2", f0, OpXbX6Sf (0, 0, 0x05, 2)},
+ {"fclrf.s3", f0, OpXbX6Sf (0, 0, 0x05, 3)},
+ {"fchkf.s0", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}},
+ {"fchkf", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO},
+ {"fchkf.s1", f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}},
+ {"fchkf.s2", f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}},
+ {"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}},
+
+ {"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}},
+ {"nop.f", f0, OpXbX6 (0, 0, 0x01), {IMMU21}},
+
+ {"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}},
+ {"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO},
+ {"fprcpa.s1", f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}},
+ {"fprcpa.s2", f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}},
+ {"fprcpa.s3", f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}},
+
+ {"fprsqrta.s0", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}},
+ {"fprsqrta", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO},
+ {"fprsqrta.s1", f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}},
+ {"fprsqrta.s2", f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}},
+ {"fprsqrta.s3", f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}},
+
+ {"fpmin.s0", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}},
+ {"fpmin", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO},
+ {"fpmin.s1", f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}},
+ {"fpmin.s2", f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}},
+ {"fpmin.s3", f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}},
+ {"fpmax.s0", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}},
+ {"fpmax", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO},
+ {"fpmax.s1", f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}},
+ {"fpmax.s2", f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}},
+ {"fpmax.s3", f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}},
+ {"fpamin.s0", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}},
+ {"fpamin", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO},
+ {"fpamin.s1", f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}},
+ {"fpamin.s2", f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}},
+ {"fpamin.s3", f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}},
+ {"fpamax.s0", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}},
+ {"fpamax", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO},
+ {"fpamax.s1", f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}},
+ {"fpamax.s2", f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}},
+ {"fpamax.s3", f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}},
+ {"fpcmp.eq.s0", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}},
+ {"fpcmp.eq", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO},
+ {"fpcmp.eq.s1", f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}},
+ {"fpcmp.eq.s2", f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}},
+ {"fpcmp.eq.s3", f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}},
+ {"fpcmp.lt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}},
+ {"fpcmp.lt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO},
+ {"fpcmp.lt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}},
+ {"fpcmp.lt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}},
+ {"fpcmp.lt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}},
+ {"fpcmp.le.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}},
+ {"fpcmp.le", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO},
+ {"fpcmp.le.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}},
+ {"fpcmp.le.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}},
+ {"fpcmp.le.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}},
+ {"fpcmp.unord.s0", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}},
+ {"fpcmp.unord", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO},
+ {"fpcmp.unord.s1", f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}},
+ {"fpcmp.unord.s2", f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}},
+ {"fpcmp.unord.s3", f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}},
+ {"fpcmp.neq.s0", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}},
+ {"fpcmp.neq", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO},
+ {"fpcmp.neq.s1", f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}},
+ {"fpcmp.neq.s2", f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}},
+ {"fpcmp.neq.s3", f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}},
+ {"fpcmp.nlt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}},
+ {"fpcmp.nlt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO},
+ {"fpcmp.nlt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}},
+ {"fpcmp.nlt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}},
+ {"fpcmp.nlt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}},
+ {"fpcmp.nle.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}},
+ {"fpcmp.nle", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO},
+ {"fpcmp.nle.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}},
+ {"fpcmp.nle.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}},
+ {"fpcmp.nle.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}},
+ {"fpcmp.ord.s0", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}},
+ {"fpcmp.ord", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO},
+ {"fpcmp.ord.s1", f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}},
+ {"fpcmp.ord.s2", f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}},
+ {"fpcmp.ord.s3", f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}},
+
+ {"fpabs", f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO},
+ {"fpmerge.s", f, OpXbX6 (1, 0, 0x10), {F1, F2, F3}},
+ {"fpneg", f, OpXbX6 (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3},
+ {"fpnegabs", f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO},
+ {"fpmerge.ns", f, OpXbX6 (1, 0, 0x11), {F1, F2, F3}},
+ {"fpmerge.se", f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}},
+
+ {"fpcvt.fx.s0", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}},
+ {"fpcvt.fx", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO},
+ {"fpcvt.fx.s1", f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}},
+ {"fpcvt.fx.s2", f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}},
+ {"fpcvt.fx.s3", f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}},
+ {"fpcvt.fxu.s0", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}},
+ {"fpcvt.fxu", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO},
+ {"fpcvt.fxu.s1", f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}},
+ {"fpcvt.fxu.s2", f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}},
+ {"fpcvt.fxu.s3", f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}},
+ {"fpcvt.fx.trunc.s0", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}},
+ {"fpcvt.fx.trunc", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO},
+ {"fpcvt.fx.trunc.s1", f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}},
+ {"fpcvt.fx.trunc.s2", f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}},
+ {"fpcvt.fx.trunc.s3", f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}},
+ {"fpcvt.fxu.trunc.s0", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}},
+ {"fpcvt.fxu.trunc", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO},
+ {"fpcvt.fxu.trunc.s1", f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}},
+ {"fpcvt.fxu.trunc.s2", f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}},
+ {"fpcvt.fxu.trunc.s3", f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}},
+
+ {"fcmp.eq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}},
+ {"fcmp.eq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO},
+ {"fcmp.eq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}},
+ {"fcmp.eq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}},
+ {"fcmp.eq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}},
+ {"fcmp.lt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}},
+ {"fcmp.lt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO},
+ {"fcmp.lt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}},
+ {"fcmp.lt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}},
+ {"fcmp.lt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}},
+ {"fcmp.le.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}},
+ {"fcmp.le", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO},
+ {"fcmp.le.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}},
+ {"fcmp.le.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}},
+ {"fcmp.le.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}},
+ {"fcmp.unord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}},
+ {"fcmp.unord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO},
+ {"fcmp.unord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}},
+ {"fcmp.unord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}},
+ {"fcmp.unord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}},
+ {"fcmp.eq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}},
+ {"fcmp.eq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO},
+ {"fcmp.eq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3}},
+ {"fcmp.eq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3}},
+ {"fcmp.eq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3}},
+ {"fcmp.lt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}},
+ {"fcmp.lt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO},
+ {"fcmp.lt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3}},
+ {"fcmp.lt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3}},
+ {"fcmp.lt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3}},
+ {"fcmp.le.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}},
+ {"fcmp.le.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO},
+ {"fcmp.le.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3}},
+ {"fcmp.le.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3}},
+ {"fcmp.le.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3}},
+ {"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}},
+ {"fcmp.unord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO},
+ {"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}},
+ {"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}},
+ {"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}},
+
+ /* pseudo-ops of the above */
+ {"fcmp.gt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}},
+ {"fcmp.gt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUDO},
+ {"fcmp.gt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}},
+ {"fcmp.gt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}},
+ {"fcmp.gt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}},
+ {"fcmp.ge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}},
+ {"fcmp.ge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUDO},
+ {"fcmp.ge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}},
+ {"fcmp.ge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}},
+ {"fcmp.ge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}},
+ {"fcmp.neq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}},
+ {"fcmp.neq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO},
+ {"fcmp.neq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}},
+ {"fcmp.neq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}},
+ {"fcmp.neq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}},
+ {"fcmp.nlt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}},
+ {"fcmp.nlt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO},
+ {"fcmp.nlt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}},
+ {"fcmp.nlt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}},
+ {"fcmp.nlt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}},
+ {"fcmp.nle.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}},
+ {"fcmp.nle", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO},
+ {"fcmp.nle.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}},
+ {"fcmp.nle.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}},
+ {"fcmp.nle.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}},
+ {"fcmp.ngt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}},
+ {"fcmp.ngt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUDO},
+ {"fcmp.ngt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}},
+ {"fcmp.ngt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}},
+ {"fcmp.ngt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}},
+ {"fcmp.nge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}},
+ {"fcmp.nge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUDO},
+ {"fcmp.nge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}},
+ {"fcmp.nge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}},
+ {"fcmp.nge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}},
+ {"fcmp.ord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}},
+ {"fcmp.ord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO},
+ {"fcmp.ord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}},
+ {"fcmp.ord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}},
+ {"fcmp.ord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}},
+ {"fcmp.gt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}},
+ {"fcmp.gt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PSEUDO},
+ {"fcmp.gt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2}},
+ {"fcmp.gt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2}},
+ {"fcmp.gt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2}},
+ {"fcmp.ge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}},
+ {"fcmp.ge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PSEUDO},
+ {"fcmp.ge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2}},
+ {"fcmp.ge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2}},
+ {"fcmp.ge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2}},
+ {"fcmp.neq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}},
+ {"fcmp.neq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO},
+ {"fcmp.neq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}},
+ {"fcmp.neq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}},
+ {"fcmp.neq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}},
+ {"fcmp.nlt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}},
+ {"fcmp.nlt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO},
+ {"fcmp.nlt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}},
+ {"fcmp.nlt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}},
+ {"fcmp.nlt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}},
+ {"fcmp.nle.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}},
+ {"fcmp.nle.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO},
+ {"fcmp.nle.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}},
+ {"fcmp.nle.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}},
+ {"fcmp.nle.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}},
+ {"fcmp.ngt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}},
+ {"fcmp.ngt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, PSEUDO},
+ {"fcmp.ngt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}},
+ {"fcmp.ngt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}},
+ {"fcmp.ngt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}},
+ {"fcmp.nge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}},
+ {"fcmp.nge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, PSEUDO},
+ {"fcmp.nge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}},
+ {"fcmp.nge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}},
+ {"fcmp.nge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}},
+ {"fcmp.ord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}},
+ {"fcmp.ord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO},
+ {"fcmp.ord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}},
+ {"fcmp.ord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}},
+ {"fcmp.ord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}},
+
+ {"fclass.m", f2, OpTa (5, 0), {P1, P2, F2, IMMU9}},
+ {"fclass.nm", f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO},
+ {"fclass.m.unc", f2, OpTa (5, 1), {P1, P2, F2, IMMU9}},
+ {"fclass.nm.unc", f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO},
+
+ /* note: fnorm and fcvt.xuf have identical encodings! */
+ {"fnorm.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO},
+ {"fadd.s0", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd.s1", f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd.s2", f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd.s3", f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd.s.s0", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd.s", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd.s.s1", f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd.s.s2", f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd.s.s3", f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO},
+ {"fmpy.s0", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy.s1", f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy.s2", f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy.s3", f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy.s.s0", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy.s", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy.s.s1", f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy.s.s2", f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy.s.s3", f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO},
+ {"fma.s0", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}},
+ {"fma", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"fma.s1", f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}},
+ {"fma.s2", f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}},
+ {"fma.s3", f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}},
+ {"fma.s.s0", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"fma.s", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}},
+ {"fma.s.s1", f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}},
+ {"fma.s.s2", f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}},
+ {"fma.s.s3", f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}},
+
+ {"fnorm.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO},
+ {"fnorm.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO},
+ {"fcvt.xuf.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO},
+ {"fadd.d.s0", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd.d", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd.d.s1", f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd.d.s2", f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO},
+ {"fadd.d.s3", f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO},
+ {"fmpy.d.s0", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy.d", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy.d.s1", f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy.d.s2", f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO},
+ {"fmpy.d.s3", f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO},
+ {"fma.d.s0", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}},
+ {"fma.d", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"fma.d.s1", f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}},
+ {"fma.d.s2", f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}},
+ {"fma.d.s3", f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}},
+
+ {"fpmpy.s0", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fpmpy", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fpmpy.s1", f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO},
+ {"fpmpy.s2", f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO},
+ {"fpmpy.s3", f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO},
+ {"fpma.s0", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}},
+ {"fpma", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"fpma.s1", f, OpXaSf (0x9, 1, 1), {F1, F3, F4, F2}},
+ {"fpma.s2", f, OpXaSf (0x9, 1, 2), {F1, F3, F4, F2}},
+ {"fpma.s3", f, OpXaSf (0x9, 1, 3), {F1, F3, F4, F2}},
+
+ {"fsub.s0", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub.s1", f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub.s2", f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub.s3", f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub.s.s0", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub.s", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub.s.s1", f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub.s.s2", f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub.s.s3", f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO},
+ {"fms.s0", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}},
+ {"fms", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"fms.s1", f, OpXaSf (0xa, 0, 1), {F1, F3, F4, F2}},
+ {"fms.s2", f, OpXaSf (0xa, 0, 2), {F1, F3, F4, F2}},
+ {"fms.s3", f, OpXaSf (0xa, 0, 3), {F1, F3, F4, F2}},
+ {"fms.s.s0", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}},
+ {"fms.s", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"fms.s.s1", f, OpXaSf (0xa, 1, 1), {F1, F3, F4, F2}},
+ {"fms.s.s2", f, OpXaSf (0xa, 1, 2), {F1, F3, F4, F2}},
+ {"fms.s.s3", f, OpXaSf (0xa, 1, 3), {F1, F3, F4, F2}},
+ {"fsub.d.s0", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub.d", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub.d.s1", f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub.d.s2", f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO},
+ {"fsub.d.s3", f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO},
+ {"fms.d.s0", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}},
+ {"fms.d", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"fms.d.s1", f, OpXaSf (0xb, 0, 1), {F1, F3, F4, F2}},
+ {"fms.d.s2", f, OpXaSf (0xb, 0, 2), {F1, F3, F4, F2}},
+ {"fms.d.s3", f, OpXaSf (0xb, 0, 3), {F1, F3, F4, F2}},
+
+ {"fpms.s0", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}},
+ {"fpms", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"fpms.s1", f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}},
+ {"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}},
+ {"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}},
+
+ {"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy.s2", f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy.s3", f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy.s.s0", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy.s", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy.s.s1", f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy.s.s2", f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy.s.s3", f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO},
+ {"fnma.s0", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}},
+ {"fnma", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"fnma.s1", f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}},
+ {"fnma.s2", f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}},
+ {"fnma.s3", f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}},
+ {"fnma.s.s0", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}},
+ {"fnma.s", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"fnma.s.s1", f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}},
+ {"fnma.s.s2", f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}},
+ {"fnma.s.s3", f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}},
+ {"fnmpy.d.s0", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy.d", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy.d.s1", f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy.d.s2", f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO},
+ {"fnmpy.d.s3", f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO},
+ {"fnma.d.s0", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}},
+ {"fnma.d", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"fnma.d.s1", f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}},
+ {"fnma.d.s2", f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}},
+ {"fnma.d.s3", f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}},
+
+ {"fpnmpy.s0", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fpnmpy", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"fpnmpy.s1", f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO},
+ {"fpnmpy.s2", f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO},
+ {"fpnmpy.s3", f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO},
+ {"fpnma.s0", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}},
+ {"fpnma", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"fpnma.s1", f, OpXaSf (0xd, 1, 1), {F1, F3, F4, F2}},
+ {"fpnma.s2", f, OpXaSf (0xd, 1, 2), {F1, F3, F4, F2}},
+ {"fpnma.s3", f, OpXaSf (0xd, 1, 3), {F1, F3, F4, F2}},
+
+ {"xmpy.l", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"xmpy.lu", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+ {"xmpy.h", f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO},
+ {"xmpy.hu", f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO},
+ {"xma.l", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}},
+ {"xma.lu", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+ {"xma.h", f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}},
+ {"xma.hu", f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}},
+
+ {"fselect", f, OpXa (0xe, 0), {F1, F3, F4, F2}},
+
+ {0}
+ };
+
+#undef f0
+#undef f
+#undef f2
+#undef bF2
+#undef bF4
+#undef bQ
+#undef bRa
+#undef bRb
+#undef bSf
+#undef bTa
+#undef bXa
+#undef bXb
+#undef bX2
+#undef bX6
+#undef mF2
+#undef mF4
+#undef mQ
+#undef mRa
+#undef mRb
+#undef mSf
+#undef mTa
+#undef mXa
+#undef mXb
+#undef mX2
+#undef mX6
+#undef OpXa
+#undef OpXaSf
+#undef OpXaSfF2
+#undef OpXaSfF4
+#undef OpXaSfF2F4
+#undef OpXaX2
+#undef OpRaRbTaSf
+#undef OpTa
+#undef OpXbQSf
+#undef OpXbX6
+#undef OpXbX6F2
+#undef OpXbX6Sf
--- /dev/null
+/* ia64-opc-i.c -- IA-64 `I' opcode table.
+ Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 2, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+#include "ia64-opc.h"
+
+#define I0 IA64_TYPE_I, 0
+#define I IA64_TYPE_I, 1
+#define I2 IA64_TYPE_I, 2
+
+/* instruction bit fields: */
+#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12)
+#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 23)
+#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33)
+#define bTag13(x) (((ia64_insn) ((x) & 0x1)) << 33)
+#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36)
+#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20)
+#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 32)
+#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20)
+#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33)
+#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22)
+#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
+#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34)
+#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28)
+#define bX2c(x) (((ia64_insn) ((x) & 0x3)) << 30)
+#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33)
+#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
+#define bYa(x) (((ia64_insn) ((x) & 0x1)) << 13)
+#define bYb(x) (((ia64_insn) ((x) & 0x1)) << 26)
+#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36)
+#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33)
+
+/* instruction bit masks: */
+#define mC bC (-1)
+#define mIh bIh (-1)
+#define mTa bTa (-1)
+#define mTag13 bTag13 (-1)
+#define mTb bTb (-1)
+#define mVc bVc (-1)
+#define mVe bVe (-1)
+#define mWh bWh (-1)
+#define mX bX (-1)
+#define mXb bXb (-1)
+#define mX2 bX2 (-1)
+#define mX2a bX2a (-1)
+#define mX2b bX2b (-1)
+#define mX2c bX2c (-1)
+#define mX3 bX3 (-1)
+#define mX6 bX6 (-1)
+#define mYa bYa (-1)
+#define mYb bYb (-1)
+#define mZa bZa (-1)
+#define mZb bZb (-1)
+
+#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \
+ (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \
+ (mOp | mZa | mZb | mVe | mX2a | mX2b)
+#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \
+ (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \
+ (mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c)
+#define OpX2X(a,b,c) (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX)
+#define OpX2XYa(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \
+ (mOp | mX2 | mX | mYa)
+#define OpX2XYb(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \
+ (mOp | mX2 | mX | mYb)
+#define OpX2TaTbYaC(a,b,c,d,e,f) \
+ (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \
+ (mOp | mX2 | mTa | mTb | mYa | mC)
+#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3)
+#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \
+ (mOp | mX3 | mX6)
+#define OpX3XbIhWh(a,b,c,d,e) \
+ (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \
+ (mOp | mX3 | mXb | mIh | mWh)
+#define OpX3XbIhWhTag13(a,b,c,d,e,f) \
+ (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \
+ (mOp | mX3 | mXb | mIh | mWh | mTag13)
+
+struct ia64_opcode ia64_opcodes_i[] =
+ {
+ /* I-type instruction encodings (sorted according to major opcode) */
+
+ {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX},
+ {"nop.i", I0, OpX3X6 (0, 0, 0x01), {IMMU21}, X_IN_MLX},
+ {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}},
+
+ {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO},
+#define MOV(a,b,c,d) \
+ I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}
+ {"mov.sptk", MOV (7, 0, 0, 0)},
+ {"mov.sptk.imp", MOV (7, 0, 1, 0)},
+ {"mov", MOV (7, 0, 0, 1)},
+ {"mov.imp", MOV (7, 0, 1, 1)},
+ {"mov.dptk", MOV (7, 0, 0, 2)},
+ {"mov.dptk.imp", MOV (7, 0, 1, 2)},
+ {"mov.ret.sptk", MOV (7, 1, 0, 0)},
+ {"mov.ret.sptk.imp", MOV (7, 1, 1, 0)},
+ {"mov.ret", MOV (7, 1, 0, 1)},
+ {"mov.ret.imp", MOV (7, 1, 1, 1)},
+ {"mov.ret.dptk", MOV (7, 1, 0, 2)},
+ {"mov.ret.dptk.imp", MOV (7, 1, 1, 2)},
+#undef MOV
+ {"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}},
+ {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}},
+ {"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}},
+ {"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}},
+ {"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}},
+ {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}},
+ {"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}},
+ {"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}},
+ {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}},
+ {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}},
+ {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}},
+ {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}},
+ {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}},
+ {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}},
+ {"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}},
+ {"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}},
+ {"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}},
+ {"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}},
+
+ {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}},
+
+ {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}},
+
+ {"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6},
+ PSEUDO | LEN_EQ_64MCNT},
+ {"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}},
+
+ {"shr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6},
+ PSEUDO | LEN_EQ_64MCNT},
+ {"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}},
+
+ {"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
+ PSEUDO | LEN_EQ_64MCNT},
+ {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}},
+ {"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}},
+ {"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}},
+#define TBIT(a,b,c,d) \
+ I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}
+#define TBITCM(a,b,c,d) \
+ I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO
+ {"tbit.z", TBIT (0, 0, 0, 0)},
+ {"tbit.nz", TBITCM (0, 0, 0, 0)},
+ {"tbit.z.unc", TBIT (0, 0, 0, 1)},
+ {"tbit.nz.unc", TBITCM (0, 0, 0, 1)},
+ {"tbit.z.and", TBIT (0, 1, 0, 0)},
+ {"tbit.nz.andcm", TBITCM (0, 1, 0, 0)},
+ {"tbit.nz.and", TBIT (0, 1, 0, 1)},
+ {"tbit.z.andcm", TBITCM (0, 1, 0, 1)},
+ {"tbit.z.or", TBIT (1, 0, 0, 0)},
+ {"tbit.nz.orcm", TBITCM (1, 0, 0, 0)},
+ {"tbit.nz.or", TBIT (1, 0, 0, 1)},
+ {"tbit.z.orcm", TBITCM (1, 0, 0, 1)},
+ {"tbit.z.or.andcm", TBIT (1, 1, 0, 0)},
+ {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)},
+ {"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)},
+ {"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)},
+#undef TBIT
+#define TNAT(a,b,c,d) \
+ I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}
+#define TNATCM(a,b,c,d) \
+ I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO
+ {"tnat.z", TNAT (0, 0, 1, 0)},
+ {"tnat.nz", TNATCM (0, 0, 1, 0)},
+ {"tnat.z.unc", TNAT (0, 0, 1, 1)},
+ {"tnat.nz.unc", TNATCM (0, 0, 1, 1)},
+ {"tnat.z.and", TNAT (0, 1, 1, 0)},
+ {"tnat.nz.andcm", TNATCM (0, 1, 1, 0)},
+ {"tnat.nz.and", TNAT (0, 1, 1, 1)},
+ {"tnat.z.andcm", TNATCM (0, 1, 1, 1)},
+ {"tnat.z.or", TNAT (1, 0, 1, 0)},
+ {"tnat.nz.orcm", TNATCM (1, 0, 1, 0)},
+ {"tnat.nz.or", TNAT (1, 0, 1, 1)},
+ {"tnat.z.orcm", TNATCM (1, 0, 1, 1)},
+ {"tnat.z.or.andcm", TNAT (1, 1, 1, 0)},
+ {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)},
+ {"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)},
+ {"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)},
+#undef TNAT
+
+ {"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}},
+ {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}},
+ {"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}},
+ {"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}},
+ {"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}},
+ {"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}},
+ {"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}},
+ {"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}},
+ {"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}},
+ {"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}},
+ {"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}},
+ {"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}},
+ {"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}},
+ {"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}},
+ {"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}},
+ {"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}},
+ {"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}},
+ {"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}},
+ {"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}},
+ {"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}},
+ {"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}},
+ {"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}},
+ {"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}},
+ {"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}},
+ {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}},
+ {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}},
+ {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}},
+ {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}},
+ {"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}},
+ {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}},
+ {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}},
+ {"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}},
+ {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}},
+ {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}},
+ {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}},
+ {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}},
+ {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}},
+ {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}},
+ {"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}},
+ {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}},
+ {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}},
+ {"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}},
+
+ {0}
+ };
+
+#undef I0
+#undef I
+#undef I2
+#undef L
+#undef bC
+#undef bIh
+#undef bTa
+#undef bTag13
+#undef bTb
+#undef bVc
+#undef bVe
+#undef bWh
+#undef bX
+#undef bXb
+#undef bX2
+#undef bX2a
+#undef bX2b
+#undef bX2c
+#undef bX3
+#undef bX6
+#undef bY
+#undef bZa
+#undef bZb
+#undef mC
+#undef mIh
+#undef mTa
+#undef mTag13
+#undef mTb
+#undef mVc
+#undef mVe
+#undef mWh
+#undef mX
+#undef mXb
+#undef mX2
+#undef mX2a
+#undef mX2b
+#undef mX2c
+#undef mX3
+#undef mX6
+#undef mY
+#undef mZa
+#undef mZb
+#undef OpZaZbVeX2aX2b
+#undef OpZaZbVeX2aX2bX2c
+#undef OpX2X
+#undef OpX2XYa
+#undef OpX2XYb
+#undef OpX2TaTbYaC
+#undef OpX3
+#undef OpX3X6
+#undef OpX3XbIhWh
+#undef OpX3XbIhWhTag13
--- /dev/null
+/* ia64-opc-m.c -- IA-64 `M' opcode table.
+ Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 2, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+#include "ia64-opc.h"
+
+#define M0 IA64_TYPE_M, 0
+#define M IA64_TYPE_M, 1
+#define M2 IA64_TYPE_M, 2
+
+/* instruction bit fields: */
+#define bM(x) (((ia64_insn) ((x) & 0x1)) << 36)
+#define bX(x) (((ia64_insn) ((x) & 0x1)) << 27)
+#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 31)
+#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33)
+#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 27)
+#define bX6a(x) (((ia64_insn) ((x) & 0x3f)) << 30)
+#define bX6b(x) (((ia64_insn) ((x) & 0x3f)) << 27)
+#define bHint(x) (((ia64_insn) ((x) & 0x3)) << 28)
+
+#define mM bM (-1)
+#define mX bX (-1)
+#define mX2 bX2 (-1)
+#define mX3 bX3 (-1)
+#define mX4 bX4 (-1)
+#define mX6a bX6a (-1)
+#define mX6b bX6b (-1)
+#define mHint bHint (-1)
+
+#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3)
+#define OpX3X6b(a,b,c) (bOp (a) | bX3 (b) | bX6b (c)), \
+ (mOp | mX3 | mX6b)
+#define OpX3X4(a,b,c) (bOp (a) | bX3 (b) | bX4 (c)), \
+ (mOp | mX3 | mX4)
+#define OpX3X4X2(a,b,c,d) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d)), \
+ (mOp | mX3 | mX4 | mX2)
+#define OpX6aHint(a,b,c) (bOp (a) | bX6a (b) | bHint (c)), \
+ (mOp | mX6a | mHint)
+#define OpXX6aHint(a,b,c,d) (bOp (a) | bX (b) | bX6a (c) | bHint (d)), \
+ (mOp | mX | mX6a | mHint)
+#define OpMXX6a(a,b,c,d) \
+ (bOp (a) | bM (b) | bX (c) | bX6a (d)), (mOp | mM | mX | mX6a)
+#define OpMXX6aHint(a,b,c,d,e) \
+ (bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e)), \
+ (mOp | mM | mX | mX6a | mHint)
+
+struct ia64_opcode ia64_opcodes_m[] =
+ {
+ /* M-type instruction encodings (sorted according to major opcode) */
+
+ {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}},
+ {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}},
+ {"chk.a.nc", M0, OpX3 (0, 6), {F1, TGT25c}},
+ {"chk.a.clr", M0, OpX3 (0, 7), {F1, TGT25c}},
+
+ {"invala", M0, OpX3X4X2 (0, 0, 0, 1)},
+ {"fwb", M0, OpX3X4X2 (0, 0, 0, 2)},
+ {"mf", M0, OpX3X4X2 (0, 0, 2, 2)},
+ {"mf.a", M0, OpX3X4X2 (0, 0, 3, 2)},
+ {"srlz.d", M0, OpX3X4X2 (0, 0, 0, 3)},
+ {"srlz.i", M0, OpX3X4X2 (0, 0, 1, 3)},
+ {"sync.i", M0, OpX3X4X2 (0, 0, 3, 3)},
+ {"flushrs", M0, OpX3X4X2 (0, 0, 0xc, 0), {0, }, FIRST | NO_PRED},
+ {"loadrs", M0, OpX3X4X2 (0, 0, 0xa, 0), {0, }, FIRST | NO_PRED},
+ {"invala.e", M0, OpX3X4X2 (0, 0, 2, 1), {R1}},
+ {"invala.e", M0, OpX3X4X2 (0, 0, 3, 1), {F1}},
+ {"mov.m", M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}},
+
+ {"break.m", M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}},
+ {"nop.m", M0, OpX3X4X2 (0, 0, 1, 0), {IMMU21}},
+
+ {"sum", M0, OpX3X4 (0, 0, 4), {IMMU24}},
+ {"rum", M0, OpX3X4 (0, 0, 5), {IMMU24}},
+ {"ssm", M0, OpX3X4 (0, 0, 6), {IMMU24}, PRIV},
+ {"rsm", M0, OpX3X4 (0, 0, 7), {IMMU24}, PRIV},
+
+ {"mov.m", M, OpX3X6b (1, 0, 0x2a), {AR3, R2}},
+ {"mov.m", M, OpX3X6b (1, 0, 0x22), {R1, AR3}},
+ {"mov", M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV},
+
+ {"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS},
+
+ {"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}},
+ {"mov", M, OpX3X6b (1, 0, 0x25), {R1, PSR}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x21), {R1, PSR_UM}},
+ {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}},
+ {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}},
+ {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}},
+ {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}},
+ {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}},
+ {"probe.r.fault", M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}},
+ {"probe.w.fault", M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}},
+ {"itc.d", M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV},
+ {"itc.i", M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV},
+
+ {"mov", M, OpX3X6b (1, 0, 0x00), {RR_R3, R2}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x01), {DBR_R3, R2}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x02), {IBR_R3, R2}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x03), {PKR_R3, R2}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x04), {PMC_R3, R2}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x05), {PMD_R3, R2}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x06), {MSR_R3, R2}, PRIV},
+ {"itr.d", M, OpX3X6b (1, 0, 0x0e), {DTR_R3, R2}, PRIV},
+ {"itr.i", M, OpX3X6b (1, 0, 0x0f), {ITR_R3, R2}, PRIV},
+
+ {"mov", M, OpX3X6b (1, 0, 0x10), {R1, RR_R3}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x11), {R1, DBR_R3}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x12), {R1, IBR_R3}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x13), {R1, PKR_R3}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x14), {R1, PMC_R3}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x15), {R1, PMD_R3}},
+ {"mov", M, OpX3X6b (1, 0, 0x16), {R1, MSR_R3}, PRIV},
+ {"mov", M, OpX3X6b (1, 0, 0x17), {R1, CPUID_R3}},
+
+ {"ptc.l", M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV},
+ {"ptc.g", M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV},
+ {"ptc.ga", M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV},
+ {"ptr.d", M0, OpX3X6b (1, 0, 0x0c), {R3, R2}, PRIV},
+ {"ptr.i", M0, OpX3X6b (1, 0, 0x0d), {R3, R2}, PRIV},
+
+ {"thash", M, OpX3X6b (1, 0, 0x1a), {R1, R3}},
+ {"ttag", M, OpX3X6b (1, 0, 0x1b), {R1, R3}},
+ {"tpa", M, OpX3X6b (1, 0, 0x1e), {R1, R3}, PRIV},
+ {"tak", M, OpX3X6b (1, 0, 0x1f), {R1, R3}, PRIV},
+
+ {"chk.s.m", M0, OpX3 (1, 1), {R2, TGT25b}},
+ {"chk.s", M0, OpX3 (1, 3), {F2, TGT25b}},
+
+ {"fc", M0, OpX3X6b (1, 0, 0x30), {R3}},
+ {"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV},
+
+ /* integer load */
+ {"ld1", M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}},
+ {"ld1.nt1", M, OpMXX6aHint (4, 0, 0, 0x00, 1), {R1, MR3}},
+ {"ld1.nta", M, OpMXX6aHint (4, 0, 0, 0x00, 3), {R1, MR3}},
+ {"ld2", M, OpMXX6aHint (4, 0, 0, 0x01, 0), {R1, MR3}},
+ {"ld2.nt1", M, OpMXX6aHint (4, 0, 0, 0x01, 1), {R1, MR3}},
+ {"ld2.nta", M, OpMXX6aHint (4, 0, 0, 0x01, 3), {R1, MR3}},
+ {"ld4", M, OpMXX6aHint (4, 0, 0, 0x02, 0), {R1, MR3}},
+ {"ld4.nt1", M, OpMXX6aHint (4, 0, 0, 0x02, 1), {R1, MR3}},
+ {"ld4.nta", M, OpMXX6aHint (4, 0, 0, 0x02, 3), {R1, MR3}},
+ {"ld8", M, OpMXX6aHint (4, 0, 0, 0x03, 0), {R1, MR3}},
+ {"ld8.nt1", M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}},
+ {"ld8.nta", M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}},
+ {"ld1.s", M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}},
+ {"ld1.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}},
+ {"ld1.s.nta", M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}},
+ {"ld2.s", M, OpMXX6aHint (4, 0, 0, 0x05, 0), {R1, MR3}},
+ {"ld2.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x05, 1), {R1, MR3}},
+ {"ld2.s.nta", M, OpMXX6aHint (4, 0, 0, 0x05, 3), {R1, MR3}},
+ {"ld4.s", M, OpMXX6aHint (4, 0, 0, 0x06, 0), {R1, MR3}},
+ {"ld4.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x06, 1), {R1, MR3}},
+ {"ld4.s.nta", M, OpMXX6aHint (4, 0, 0, 0x06, 3), {R1, MR3}},
+ {"ld8.s", M, OpMXX6aHint (4, 0, 0, 0x07, 0), {R1, MR3}},
+ {"ld8.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x07, 1), {R1, MR3}},
+ {"ld8.s.nta", M, OpMXX6aHint (4, 0, 0, 0x07, 3), {R1, MR3}},
+ {"ld1.a", M, OpMXX6aHint (4, 0, 0, 0x08, 0), {R1, MR3}},
+ {"ld1.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x08, 1), {R1, MR3}},
+ {"ld1.a.nta", M, OpMXX6aHint (4, 0, 0, 0x08, 3), {R1, MR3}},
+ {"ld2.a", M, OpMXX6aHint (4, 0, 0, 0x09, 0), {R1, MR3}},
+ {"ld2.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x09, 1), {R1, MR3}},
+ {"ld2.a.nta", M, OpMXX6aHint (4, 0, 0, 0x09, 3), {R1, MR3}},
+ {"ld4.a", M, OpMXX6aHint (4, 0, 0, 0x0a, 0), {R1, MR3}},
+ {"ld4.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0a, 1), {R1, MR3}},
+ {"ld4.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0a, 3), {R1, MR3}},
+ {"ld8.a", M, OpMXX6aHint (4, 0, 0, 0x0b, 0), {R1, MR3}},
+ {"ld8.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0b, 1), {R1, MR3}},
+ {"ld8.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0b, 3), {R1, MR3}},
+ {"ld1.sa", M, OpMXX6aHint (4, 0, 0, 0x0c, 0), {R1, MR3}},
+ {"ld1.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0c, 1), {R1, MR3}},
+ {"ld1.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0c, 3), {R1, MR3}},
+ {"ld2.sa", M, OpMXX6aHint (4, 0, 0, 0x0d, 0), {R1, MR3}},
+ {"ld2.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0d, 1), {R1, MR3}},
+ {"ld2.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0d, 3), {R1, MR3}},
+ {"ld4.sa", M, OpMXX6aHint (4, 0, 0, 0x0e, 0), {R1, MR3}},
+ {"ld4.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0e, 1), {R1, MR3}},
+ {"ld4.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0e, 3), {R1, MR3}},
+ {"ld8.sa", M, OpMXX6aHint (4, 0, 0, 0x0f, 0), {R1, MR3}},
+ {"ld8.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0f, 1), {R1, MR3}},
+ {"ld8.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0f, 3), {R1, MR3}},
+ {"ld1.bias", M, OpMXX6aHint (4, 0, 0, 0x10, 0), {R1, MR3}},
+ {"ld1.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x10, 1), {R1, MR3}},
+ {"ld1.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x10, 3), {R1, MR3}},
+ {"ld2.bias", M, OpMXX6aHint (4, 0, 0, 0x11, 0), {R1, MR3}},
+ {"ld2.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x11, 1), {R1, MR3}},
+ {"ld2.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x11, 3), {R1, MR3}},
+ {"ld4.bias", M, OpMXX6aHint (4, 0, 0, 0x12, 0), {R1, MR3}},
+ {"ld4.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x12, 1), {R1, MR3}},
+ {"ld4.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x12, 3), {R1, MR3}},
+ {"ld8.bias", M, OpMXX6aHint (4, 0, 0, 0x13, 0), {R1, MR3}},
+ {"ld8.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x13, 1), {R1, MR3}},
+ {"ld8.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x13, 3), {R1, MR3}},
+ {"ld1.acq", M, OpMXX6aHint (4, 0, 0, 0x14, 0), {R1, MR3}},
+ {"ld1.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x14, 1), {R1, MR3}},
+ {"ld1.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x14, 3), {R1, MR3}},
+ {"ld2.acq", M, OpMXX6aHint (4, 0, 0, 0x15, 0), {R1, MR3}},
+ {"ld2.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x15, 1), {R1, MR3}},
+ {"ld2.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x15, 3), {R1, MR3}},
+ {"ld4.acq", M, OpMXX6aHint (4, 0, 0, 0x16, 0), {R1, MR3}},
+ {"ld4.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x16, 1), {R1, MR3}},
+ {"ld4.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x16, 3), {R1, MR3}},
+ {"ld8.acq", M, OpMXX6aHint (4, 0, 0, 0x17, 0), {R1, MR3}},
+ {"ld8.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}},
+ {"ld8.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}},
+ {"ld8.fill", M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}},
+ {"ld8.fill.nt1", M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}},
+ {"ld8.fill.nta", M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}},
+ {"ld1.c.clr", M, OpMXX6aHint (4, 0, 0, 0x20, 0), {R1, MR3}},
+ {"ld1.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x20, 1), {R1, MR3}},
+ {"ld1.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x20, 3), {R1, MR3}},
+ {"ld2.c.clr", M, OpMXX6aHint (4, 0, 0, 0x21, 0), {R1, MR3}},
+ {"ld2.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x21, 1), {R1, MR3}},
+ {"ld2.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x21, 3), {R1, MR3}},
+ {"ld4.c.clr", M, OpMXX6aHint (4, 0, 0, 0x22, 0), {R1, MR3}},
+ {"ld4.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x22, 1), {R1, MR3}},
+ {"ld4.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x22, 3), {R1, MR3}},
+ {"ld8.c.clr", M, OpMXX6aHint (4, 0, 0, 0x23, 0), {R1, MR3}},
+ {"ld8.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x23, 1), {R1, MR3}},
+ {"ld8.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x23, 3), {R1, MR3}},
+ {"ld1.c.nc", M, OpMXX6aHint (4, 0, 0, 0x24, 0), {R1, MR3}},
+ {"ld1.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x24, 1), {R1, MR3}},
+ {"ld1.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x24, 3), {R1, MR3}},
+ {"ld2.c.nc", M, OpMXX6aHint (4, 0, 0, 0x25, 0), {R1, MR3}},
+ {"ld2.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x25, 1), {R1, MR3}},
+ {"ld2.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x25, 3), {R1, MR3}},
+ {"ld4.c.nc", M, OpMXX6aHint (4, 0, 0, 0x26, 0), {R1, MR3}},
+ {"ld4.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x26, 1), {R1, MR3}},
+ {"ld4.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x26, 3), {R1, MR3}},
+ {"ld8.c.nc", M, OpMXX6aHint (4, 0, 0, 0x27, 0), {R1, MR3}},
+ {"ld8.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x27, 1), {R1, MR3}},
+ {"ld8.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x27, 3), {R1, MR3}},
+ {"ld1.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x28, 0), {R1, MR3}},
+ {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x28, 1), {R1, MR3}},
+ {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x28, 3), {R1, MR3}},
+ {"ld2.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x29, 0), {R1, MR3}},
+ {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x29, 1), {R1, MR3}},
+ {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x29, 3), {R1, MR3}},
+ {"ld4.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2a, 0), {R1, MR3}},
+ {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2a, 1), {R1, MR3}},
+ {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2a, 3), {R1, MR3}},
+ {"ld8.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2b, 0), {R1, MR3}},
+ {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2b, 1), {R1, MR3}},
+ {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}},
+
+ /* integer load w/increment by register */
+ {"ld1", M, OpMXX6aHint (4, 1, 0, 0x00, 0), {R1, MR3, R2}},
+ {"ld1.nt1", M, OpMXX6aHint (4, 1, 0, 0x00, 1), {R1, MR3, R2}},
+ {"ld1.nta", M, OpMXX6aHint (4, 1, 0, 0x00, 3), {R1, MR3, R2}},
+ {"ld2", M, OpMXX6aHint (4, 1, 0, 0x01, 0), {R1, MR3, R2}},
+ {"ld2.nt1", M, OpMXX6aHint (4, 1, 0, 0x01, 1), {R1, MR3, R2}},
+ {"ld2.nta", M, OpMXX6aHint (4, 1, 0, 0x01, 3), {R1, MR3, R2}},
+ {"ld4", M, OpMXX6aHint (4, 1, 0, 0x02, 0), {R1, MR3, R2}},
+ {"ld4.nt1", M, OpMXX6aHint (4, 1, 0, 0x02, 1), {R1, MR3, R2}},
+ {"ld4.nta", M, OpMXX6aHint (4, 1, 0, 0x02, 3), {R1, MR3, R2}},
+ {"ld8", M, OpMXX6aHint (4, 1, 0, 0x03, 0), {R1, MR3, R2}},
+ {"ld8.nt1", M, OpMXX6aHint (4, 1, 0, 0x03, 1), {R1, MR3, R2}},
+ {"ld8.nta", M, OpMXX6aHint (4, 1, 0, 0x03, 3), {R1, MR3, R2}},
+ {"ld1.s", M, OpMXX6aHint (4, 1, 0, 0x04, 0), {R1, MR3, R2}},
+ {"ld1.s.nt1", M, OpMXX6aHint (4, 1, 0, 0x04, 1), {R1, MR3, R2}},
+ {"ld1.s.nta", M, OpMXX6aHint (4, 1, 0, 0x04, 3), {R1, MR3, R2}},
+ {"ld2.s", M, OpMXX6aHint (4, 1, 0, 0x05, 0), {R1, MR3, R2}},
+ {"ld2.s.nt1", M, OpMXX6aHint (4, 1, 0, 0x05, 1), {R1, MR3, R2}},
+ {"ld2.s.nta", M, OpMXX6aHint (4, 1, 0, 0x05, 3), {R1, MR3, R2}},
+ {"ld4.s", M, OpMXX6aHint (4, 1, 0, 0x06, 0), {R1, MR3, R2}},
+ {"ld4.s.nt1", M, OpMXX6aHint (4, 1, 0, 0x06, 1), {R1, MR3, R2}},
+ {"ld4.s.nta", M, OpMXX6aHint (4, 1, 0, 0x06, 3), {R1, MR3, R2}},
+ {"ld8.s", M, OpMXX6aHint (4, 1, 0, 0x07, 0), {R1, MR3, R2}},
+ {"ld8.s.nt1", M, OpMXX6aHint (4, 1, 0, 0x07, 1), {R1, MR3, R2}},
+ {"ld8.s.nta", M, OpMXX6aHint (4, 1, 0, 0x07, 3), {R1, MR3, R2}},
+ {"ld1.a", M, OpMXX6aHint (4, 1, 0, 0x08, 0), {R1, MR3, R2}},
+ {"ld1.a.nt1", M, OpMXX6aHint (4, 1, 0, 0x08, 1), {R1, MR3, R2}},
+ {"ld1.a.nta", M, OpMXX6aHint (4, 1, 0, 0x08, 3), {R1, MR3, R2}},
+ {"ld2.a", M, OpMXX6aHint (4, 1, 0, 0x09, 0), {R1, MR3, R2}},
+ {"ld2.a.nt1", M, OpMXX6aHint (4, 1, 0, 0x09, 1), {R1, MR3, R2}},
+ {"ld2.a.nta", M, OpMXX6aHint (4, 1, 0, 0x09, 3), {R1, MR3, R2}},
+ {"ld4.a", M, OpMXX6aHint (4, 1, 0, 0x0a, 0), {R1, MR3, R2}},
+ {"ld4.a.nt1", M, OpMXX6aHint (4, 1, 0, 0x0a, 1), {R1, MR3, R2}},
+ {"ld4.a.nta", M, OpMXX6aHint (4, 1, 0, 0x0a, 3), {R1, MR3, R2}},
+ {"ld8.a", M, OpMXX6aHint (4, 1, 0, 0x0b, 0), {R1, MR3, R2}},
+ {"ld8.a.nt1", M, OpMXX6aHint (4, 1, 0, 0x0b, 1), {R1, MR3, R2}},
+ {"ld8.a.nta", M, OpMXX6aHint (4, 1, 0, 0x0b, 3), {R1, MR3, R2}},
+ {"ld1.sa", M, OpMXX6aHint (4, 1, 0, 0x0c, 0), {R1, MR3, R2}},
+ {"ld1.sa.nt1", M, OpMXX6aHint (4, 1, 0, 0x0c, 1), {R1, MR3, R2}},
+ {"ld1.sa.nta", M, OpMXX6aHint (4, 1, 0, 0x0c, 3), {R1, MR3, R2}},
+ {"ld2.sa", M, OpMXX6aHint (4, 1, 0, 0x0d, 0), {R1, MR3, R2}},
+ {"ld2.sa.nt1", M, OpMXX6aHint (4, 1, 0, 0x0d, 1), {R1, MR3, R2}},
+ {"ld2.sa.nta", M, OpMXX6aHint (4, 1, 0, 0x0d, 3), {R1, MR3, R2}},
+ {"ld4.sa", M, OpMXX6aHint (4, 1, 0, 0x0e, 0), {R1, MR3, R2}},
+ {"ld4.sa.nt1", M, OpMXX6aHint (4, 1, 0, 0x0e, 1), {R1, MR3, R2}},
+ {"ld4.sa.nta", M, OpMXX6aHint (4, 1, 0, 0x0e, 3), {R1, MR3, R2}},
+ {"ld8.sa", M, OpMXX6aHint (4, 1, 0, 0x0f, 0), {R1, MR3, R2}},
+ {"ld8.sa.nt1", M, OpMXX6aHint (4, 1, 0, 0x0f, 1), {R1, MR3, R2}},
+ {"ld8.sa.nta", M, OpMXX6aHint (4, 1, 0, 0x0f, 3), {R1, MR3, R2}},
+ {"ld1.bias", M, OpMXX6aHint (4, 1, 0, 0x10, 0), {R1, MR3, R2}},
+ {"ld1.bias.nt1", M, OpMXX6aHint (4, 1, 0, 0x10, 1), {R1, MR3, R2}},
+ {"ld1.bias.nta", M, OpMXX6aHint (4, 1, 0, 0x10, 3), {R1, MR3, R2}},
+ {"ld2.bias", M, OpMXX6aHint (4, 1, 0, 0x11, 0), {R1, MR3, R2}},
+ {"ld2.bias.nt1", M, OpMXX6aHint (4, 1, 0, 0x11, 1), {R1, MR3, R2}},
+ {"ld2.bias.nta", M, OpMXX6aHint (4, 1, 0, 0x11, 3), {R1, MR3, R2}},
+ {"ld4.bias", M, OpMXX6aHint (4, 1, 0, 0x12, 0), {R1, MR3, R2}},
+ {"ld4.bias.nt1", M, OpMXX6aHint (4, 1, 0, 0x12, 1), {R1, MR3, R2}},
+ {"ld4.bias.nta", M, OpMXX6aHint (4, 1, 0, 0x12, 3), {R1, MR3, R2}},
+ {"ld8.bias", M, OpMXX6aHint (4, 1, 0, 0x13, 0), {R1, MR3, R2}},
+ {"ld8.bias.nt1", M, OpMXX6aHint (4, 1, 0, 0x13, 1), {R1, MR3, R2}},
+ {"ld8.bias.nta", M, OpMXX6aHint (4, 1, 0, 0x13, 3), {R1, MR3, R2}},
+ {"ld1.acq", M, OpMXX6aHint (4, 1, 0, 0x14, 0), {R1, MR3, R2}},
+ {"ld1.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x14, 1), {R1, MR3, R2}},
+ {"ld1.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x14, 3), {R1, MR3, R2}},
+ {"ld2.acq", M, OpMXX6aHint (4, 1, 0, 0x15, 0), {R1, MR3, R2}},
+ {"ld2.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x15, 1), {R1, MR3, R2}},
+ {"ld2.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x15, 3), {R1, MR3, R2}},
+ {"ld4.acq", M, OpMXX6aHint (4, 1, 0, 0x16, 0), {R1, MR3, R2}},
+ {"ld4.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x16, 1), {R1, MR3, R2}},
+ {"ld4.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x16, 3), {R1, MR3, R2}},
+ {"ld8.acq", M, OpMXX6aHint (4, 1, 0, 0x17, 0), {R1, MR3, R2}},
+ {"ld8.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x17, 1), {R1, MR3, R2}},
+ {"ld8.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x17, 3), {R1, MR3, R2}},
+ {"ld8.fill", M, OpMXX6aHint (4, 1, 0, 0x1b, 0), {R1, MR3, R2}},
+ {"ld8.fill.nt1", M, OpMXX6aHint (4, 1, 0, 0x1b, 1), {R1, MR3, R2}},
+ {"ld8.fill.nta", M, OpMXX6aHint (4, 1, 0, 0x1b, 3), {R1, MR3, R2}},
+ {"ld1.c.clr", M, OpMXX6aHint (4, 1, 0, 0x20, 0), {R1, MR3, R2}},
+ {"ld1.c.clr.nt1", M, OpMXX6aHint (4, 1, 0, 0x20, 1), {R1, MR3, R2}},
+ {"ld1.c.clr.nta", M, OpMXX6aHint (4, 1, 0, 0x20, 3), {R1, MR3, R2}},
+ {"ld2.c.clr", M, OpMXX6aHint (4, 1, 0, 0x21, 0), {R1, MR3, R2}},
+ {"ld2.c.clr.nt1", M, OpMXX6aHint (4, 1, 0, 0x21, 1), {R1, MR3, R2}},
+ {"ld2.c.clr.nta", M, OpMXX6aHint (4, 1, 0, 0x21, 3), {R1, MR3, R2}},
+ {"ld4.c.clr", M, OpMXX6aHint (4, 1, 0, 0x22, 0), {R1, MR3, R2}},
+ {"ld4.c.clr.nt1", M, OpMXX6aHint (4, 1, 0, 0x22, 1), {R1, MR3, R2}},
+ {"ld4.c.clr.nta", M, OpMXX6aHint (4, 1, 0, 0x22, 3), {R1, MR3, R2}},
+ {"ld8.c.clr", M, OpMXX6aHint (4, 1, 0, 0x23, 0), {R1, MR3, R2}},
+ {"ld8.c.clr.nt1", M, OpMXX6aHint (4, 1, 0, 0x23, 1), {R1, MR3, R2}},
+ {"ld8.c.clr.nta", M, OpMXX6aHint (4, 1, 0, 0x23, 3), {R1, MR3, R2}},
+ {"ld1.c.nc", M, OpMXX6aHint (4, 1, 0, 0x24, 0), {R1, MR3, R2}},
+ {"ld1.c.nc.nt1", M, OpMXX6aHint (4, 1, 0, 0x24, 1), {R1, MR3, R2}},
+ {"ld1.c.nc.nta", M, OpMXX6aHint (4, 1, 0, 0x24, 3), {R1, MR3, R2}},
+ {"ld2.c.nc", M, OpMXX6aHint (4, 1, 0, 0x25, 0), {R1, MR3, R2}},
+ {"ld2.c.nc.nt1", M, OpMXX6aHint (4, 1, 0, 0x25, 1), {R1, MR3, R2}},
+ {"ld2.c.nc.nta", M, OpMXX6aHint (4, 1, 0, 0x25, 3), {R1, MR3, R2}},
+ {"ld4.c.nc", M, OpMXX6aHint (4, 1, 0, 0x26, 0), {R1, MR3, R2}},
+ {"ld4.c.nc.nt1", M, OpMXX6aHint (4, 1, 0, 0x26, 1), {R1, MR3, R2}},
+ {"ld4.c.nc.nta", M, OpMXX6aHint (4, 1, 0, 0x26, 3), {R1, MR3, R2}},
+ {"ld8.c.nc", M, OpMXX6aHint (4, 1, 0, 0x27, 0), {R1, MR3, R2}},
+ {"ld8.c.nc.nt1", M, OpMXX6aHint (4, 1, 0, 0x27, 1), {R1, MR3, R2}},
+ {"ld8.c.nc.nta", M, OpMXX6aHint (4, 1, 0, 0x27, 3), {R1, MR3, R2}},
+ {"ld1.c.clr.acq", M, OpMXX6aHint (4, 1, 0, 0x28, 0), {R1, MR3, R2}},
+ {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x28, 1), {R1, MR3, R2}},
+ {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x28, 3), {R1, MR3, R2}},
+ {"ld2.c.clr.acq", M, OpMXX6aHint (4, 1, 0, 0x29, 0), {R1, MR3, R2}},
+ {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x29, 1), {R1, MR3, R2}},
+ {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x29, 3), {R1, MR3, R2}},
+ {"ld4.c.clr.acq", M, OpMXX6aHint (4, 1, 0, 0x2a, 0), {R1, MR3, R2}},
+ {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x2a, 1), {R1, MR3, R2}},
+ {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x2a, 3), {R1, MR3, R2}},
+ {"ld8.c.clr.acq", M, OpMXX6aHint (4, 1, 0, 0x2b, 0), {R1, MR3, R2}},
+ {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x2b, 1), {R1, MR3, R2}},
+ {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x2b, 3), {R1, MR3, R2}},
+
+ {"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}},
+ {"st1.nta", M, OpMXX6aHint (4, 0, 0, 0x30, 3), {MR3, R2}},
+ {"st2", M, OpMXX6aHint (4, 0, 0, 0x31, 0), {MR3, R2}},
+ {"st2.nta", M, OpMXX6aHint (4, 0, 0, 0x31, 3), {MR3, R2}},
+ {"st4", M, OpMXX6aHint (4, 0, 0, 0x32, 0), {MR3, R2}},
+ {"st4.nta", M, OpMXX6aHint (4, 0, 0, 0x32, 3), {MR3, R2}},
+ {"st8", M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}},
+ {"st8.nta", M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}},
+ {"st1.rel", M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}},
+ {"st1.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}},
+ {"st2.rel", M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}},
+ {"st2.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x35, 3), {MR3, R2}},
+ {"st4.rel", M, OpMXX6aHint (4, 0, 0, 0x36, 0), {MR3, R2}},
+ {"st4.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x36, 3), {MR3, R2}},
+ {"st8.rel", M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}},
+ {"st8.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}},
+ {"st8.spill", M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}},
+ {"st8.spill.nta", M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}},
+
+#define CMPXCHG(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV}
+ {"cmpxchg1.acq", CMPXCHG (0x00, 0)},
+ {"cmpxchg1.acq.nt1", CMPXCHG (0x00, 1)},
+ {"cmpxchg1.acq.nta", CMPXCHG (0x00, 3)},
+ {"cmpxchg2.acq", CMPXCHG (0x01, 0)},
+ {"cmpxchg2.acq.nt1", CMPXCHG (0x01, 1)},
+ {"cmpxchg2.acq.nta", CMPXCHG (0x01, 3)},
+ {"cmpxchg4.acq", CMPXCHG (0x02, 0)},
+ {"cmpxchg4.acq.nt1", CMPXCHG (0x02, 1)},
+ {"cmpxchg4.acq.nta", CMPXCHG (0x02, 3)},
+ {"cmpxchg8.acq", CMPXCHG (0x03, 0)},
+ {"cmpxchg8.acq.nt1", CMPXCHG (0x03, 1)},
+ {"cmpxchg8.acq.nta", CMPXCHG (0x03, 3)},
+ {"cmpxchg1.rel", CMPXCHG (0x04, 0)},
+ {"cmpxchg1.rel.nt1", CMPXCHG (0x04, 1)},
+ {"cmpxchg1.rel.nta", CMPXCHG (0x04, 3)},
+ {"cmpxchg2.rel", CMPXCHG (0x05, 0)},
+ {"cmpxchg2.rel.nt1", CMPXCHG (0x05, 1)},
+ {"cmpxchg2.rel.nta", CMPXCHG (0x05, 3)},
+ {"cmpxchg4.rel", CMPXCHG (0x06, 0)},
+ {"cmpxchg4.rel.nt1", CMPXCHG (0x06, 1)},
+ {"cmpxchg4.rel.nta", CMPXCHG (0x06, 3)},
+ {"cmpxchg8.rel", CMPXCHG (0x07, 0)},
+ {"cmpxchg8.rel.nt1", CMPXCHG (0x07, 1)},
+ {"cmpxchg8.rel.nta", CMPXCHG (0x07, 3)},
+#undef CMPXCHG
+ {"xchg1", M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}},
+ {"xchg1.nt1", M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}},
+ {"xchg1.nta", M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}},
+ {"xchg2", M, OpMXX6aHint (4, 0, 1, 0x09, 0), {R1, MR3, R2}},
+ {"xchg2.nt1", M, OpMXX6aHint (4, 0, 1, 0x09, 1), {R1, MR3, R2}},
+ {"xchg2.nta", M, OpMXX6aHint (4, 0, 1, 0x09, 3), {R1, MR3, R2}},
+ {"xchg4", M, OpMXX6aHint (4, 0, 1, 0x0a, 0), {R1, MR3, R2}},
+ {"xchg4.nt1", M, OpMXX6aHint (4, 0, 1, 0x0a, 1), {R1, MR3, R2}},
+ {"xchg4.nta", M, OpMXX6aHint (4, 0, 1, 0x0a, 3), {R1, MR3, R2}},
+ {"xchg8", M, OpMXX6aHint (4, 0, 1, 0x0b, 0), {R1, MR3, R2}},
+ {"xchg8.nt1", M, OpMXX6aHint (4, 0, 1, 0x0b, 1), {R1, MR3, R2}},
+ {"xchg8.nta", M, OpMXX6aHint (4, 0, 1, 0x0b, 3), {R1, MR3, R2}},
+
+ {"fetchadd4.acq", M, OpMXX6aHint (4, 0, 1, 0x12, 0), {R1, MR3, INC3}},
+ {"fetchadd4.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x12, 1), {R1, MR3, INC3}},
+ {"fetchadd4.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x12, 3), {R1, MR3, INC3}},
+ {"fetchadd8.acq", M, OpMXX6aHint (4, 0, 1, 0x13, 0), {R1, MR3, INC3}},
+ {"fetchadd8.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x13, 1), {R1, MR3, INC3}},
+ {"fetchadd8.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x13, 3), {R1, MR3, INC3}},
+ {"fetchadd4.rel", M, OpMXX6aHint (4, 0, 1, 0x16, 0), {R1, MR3, INC3}},
+ {"fetchadd4.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x16, 1), {R1, MR3, INC3}},
+ {"fetchadd4.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x16, 3), {R1, MR3, INC3}},
+ {"fetchadd8.rel", M, OpMXX6aHint (4, 0, 1, 0x17, 0), {R1, MR3, INC3}},
+ {"fetchadd8.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x17, 1), {R1, MR3, INC3}},
+ {"fetchadd8.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x17, 3), {R1, MR3, INC3}},
+
+ {"getf.sig", M, OpMXX6a (4, 0, 1, 0x1c), {R1, F2}},
+ {"getf.exp", M, OpMXX6a (4, 0, 1, 0x1d), {R1, F2}},
+ {"getf.s", M, OpMXX6a (4, 0, 1, 0x1e), {R1, F2}},
+ {"getf.d", M, OpMXX6a (4, 0, 1, 0x1f), {R1, F2}},
+
+ /* integer load w/increment by immediate */
+ {"ld1", M, OpX6aHint (5, 0x00, 0), {R1, MR3, IMM9b}},
+ {"ld1.nt1", M, OpX6aHint (5, 0x00, 1), {R1, MR3, IMM9b}},
+ {"ld1.nta", M, OpX6aHint (5, 0x00, 3), {R1, MR3, IMM9b}},
+ {"ld2", M, OpX6aHint (5, 0x01, 0), {R1, MR3, IMM9b}},
+ {"ld2.nt1", M, OpX6aHint (5, 0x01, 1), {R1, MR3, IMM9b}},
+ {"ld2.nta", M, OpX6aHint (5, 0x01, 3), {R1, MR3, IMM9b}},
+ {"ld4", M, OpX6aHint (5, 0x02, 0), {R1, MR3, IMM9b}},
+ {"ld4.nt1", M, OpX6aHint (5, 0x02, 1), {R1, MR3, IMM9b}},
+ {"ld4.nta", M, OpX6aHint (5, 0x02, 3), {R1, MR3, IMM9b}},
+ {"ld8", M, OpX6aHint (5, 0x03, 0), {R1, MR3, IMM9b}},
+ {"ld8.nt1", M, OpX6aHint (5, 0x03, 1), {R1, MR3, IMM9b}},
+ {"ld8.nta", M, OpX6aHint (5, 0x03, 3), {R1, MR3, IMM9b}},
+ {"ld1.s", M, OpX6aHint (5, 0x04, 0), {R1, MR3, IMM9b}},
+ {"ld1.s.nt1", M, OpX6aHint (5, 0x04, 1), {R1, MR3, IMM9b}},
+ {"ld1.s.nta", M, OpX6aHint (5, 0x04, 3), {R1, MR3, IMM9b}},
+ {"ld2.s", M, OpX6aHint (5, 0x05, 0), {R1, MR3, IMM9b}},
+ {"ld2.s.nt1", M, OpX6aHint (5, 0x05, 1), {R1, MR3, IMM9b}},
+ {"ld2.s.nta", M, OpX6aHint (5, 0x05, 3), {R1, MR3, IMM9b}},
+ {"ld4.s", M, OpX6aHint (5, 0x06, 0), {R1, MR3, IMM9b}},
+ {"ld4.s.nt1", M, OpX6aHint (5, 0x06, 1), {R1, MR3, IMM9b}},
+ {"ld4.s.nta", M, OpX6aHint (5, 0x06, 3), {R1, MR3, IMM9b}},
+ {"ld8.s", M, OpX6aHint (5, 0x07, 0), {R1, MR3, IMM9b}},
+ {"ld8.s.nt1", M, OpX6aHint (5, 0x07, 1), {R1, MR3, IMM9b}},
+ {"ld8.s.nta", M, OpX6aHint (5, 0x07, 3), {R1, MR3, IMM9b}},
+ {"ld1.a", M, OpX6aHint (5, 0x08, 0), {R1, MR3, IMM9b}},
+ {"ld1.a.nt1", M, OpX6aHint (5, 0x08, 1), {R1, MR3, IMM9b}},
+ {"ld1.a.nta", M, OpX6aHint (5, 0x08, 3), {R1, MR3, IMM9b}},
+ {"ld2.a", M, OpX6aHint (5, 0x09, 0), {R1, MR3, IMM9b}},
+ {"ld2.a.nt1", M, OpX6aHint (5, 0x09, 1), {R1, MR3, IMM9b}},
+ {"ld2.a.nta", M, OpX6aHint (5, 0x09, 3), {R1, MR3, IMM9b}},
+ {"ld4.a", M, OpX6aHint (5, 0x0a, 0), {R1, MR3, IMM9b}},
+ {"ld4.a.nt1", M, OpX6aHint (5, 0x0a, 1), {R1, MR3, IMM9b}},
+ {"ld4.a.nta", M, OpX6aHint (5, 0x0a, 3), {R1, MR3, IMM9b}},
+ {"ld8.a", M, OpX6aHint (5, 0x0b, 0), {R1, MR3, IMM9b}},
+ {"ld8.a.nt1", M, OpX6aHint (5, 0x0b, 1), {R1, MR3, IMM9b}},
+ {"ld8.a.nta", M, OpX6aHint (5, 0x0b, 3), {R1, MR3, IMM9b}},
+ {"ld1.sa", M, OpX6aHint (5, 0x0c, 0), {R1, MR3, IMM9b}},
+ {"ld1.sa.nt1", M, OpX6aHint (5, 0x0c, 1), {R1, MR3, IMM9b}},
+ {"ld1.sa.nta", M, OpX6aHint (5, 0x0c, 3), {R1, MR3, IMM9b}},
+ {"ld2.sa", M, OpX6aHint (5, 0x0d, 0), {R1, MR3, IMM9b}},
+ {"ld2.sa.nt1", M, OpX6aHint (5, 0x0d, 1), {R1, MR3, IMM9b}},
+ {"ld2.sa.nta", M, OpX6aHint (5, 0x0d, 3), {R1, MR3, IMM9b}},
+ {"ld4.sa", M, OpX6aHint (5, 0x0e, 0), {R1, MR3, IMM9b}},
+ {"ld4.sa.nt1", M, OpX6aHint (5, 0x0e, 1), {R1, MR3, IMM9b}},
+ {"ld4.sa.nta", M, OpX6aHint (5, 0x0e, 3), {R1, MR3, IMM9b}},
+ {"ld8.sa", M, OpX6aHint (5, 0x0f, 0), {R1, MR3, IMM9b}},
+ {"ld8.sa.nt1", M, OpX6aHint (5, 0x0f, 1), {R1, MR3, IMM9b}},
+ {"ld8.sa.nta", M, OpX6aHint (5, 0x0f, 3), {R1, MR3, IMM9b}},
+ {"ld1.bias", M, OpX6aHint (5, 0x10, 0), {R1, MR3, IMM9b}},
+ {"ld1.bias.nt1", M, OpX6aHint (5, 0x10, 1), {R1, MR3, IMM9b}},
+ {"ld1.bias.nta", M, OpX6aHint (5, 0x10, 3), {R1, MR3, IMM9b}},
+ {"ld2.bias", M, OpX6aHint (5, 0x11, 0), {R1, MR3, IMM9b}},
+ {"ld2.bias.nt1", M, OpX6aHint (5, 0x11, 1), {R1, MR3, IMM9b}},
+ {"ld2.bias.nta", M, OpX6aHint (5, 0x11, 3), {R1, MR3, IMM9b}},
+ {"ld4.bias", M, OpX6aHint (5, 0x12, 0), {R1, MR3, IMM9b}},
+ {"ld4.bias.nt1", M, OpX6aHint (5, 0x12, 1), {R1, MR3, IMM9b}},
+ {"ld4.bias.nta", M, OpX6aHint (5, 0x12, 3), {R1, MR3, IMM9b}},
+ {"ld8.bias", M, OpX6aHint (5, 0x13, 0), {R1, MR3, IMM9b}},
+ {"ld8.bias.nt1", M, OpX6aHint (5, 0x13, 1), {R1, MR3, IMM9b}},
+ {"ld8.bias.nta", M, OpX6aHint (5, 0x13, 3), {R1, MR3, IMM9b}},
+ {"ld1.acq", M, OpX6aHint (5, 0x14, 0), {R1, MR3, IMM9b}},
+ {"ld1.acq.nt1", M, OpX6aHint (5, 0x14, 1), {R1, MR3, IMM9b}},
+ {"ld1.acq.nta", M, OpX6aHint (5, 0x14, 3), {R1, MR3, IMM9b}},
+ {"ld2.acq", M, OpX6aHint (5, 0x15, 0), {R1, MR3, IMM9b}},
+ {"ld2.acq.nt1", M, OpX6aHint (5, 0x15, 1), {R1, MR3, IMM9b}},
+ {"ld2.acq.nta", M, OpX6aHint (5, 0x15, 3), {R1, MR3, IMM9b}},
+ {"ld4.acq", M, OpX6aHint (5, 0x16, 0), {R1, MR3, IMM9b}},
+ {"ld4.acq.nt1", M, OpX6aHint (5, 0x16, 1), {R1, MR3, IMM9b}},
+ {"ld4.acq.nta", M, OpX6aHint (5, 0x16, 3), {R1, MR3, IMM9b}},
+ {"ld8.acq", M, OpX6aHint (5, 0x17, 0), {R1, MR3, IMM9b}},
+ {"ld8.acq.nt1", M, OpX6aHint (5, 0x17, 1), {R1, MR3, IMM9b}},
+ {"ld8.acq.nta", M, OpX6aHint (5, 0x17, 3), {R1, MR3, IMM9b}},
+ {"ld8.fill", M, OpX6aHint (5, 0x1b, 0), {R1, MR3, IMM9b}},
+ {"ld8.fill.nt1", M, OpX6aHint (5, 0x1b, 1), {R1, MR3, IMM9b}},
+ {"ld8.fill.nta", M, OpX6aHint (5, 0x1b, 3), {R1, MR3, IMM9b}},
+ {"ld1.c.clr", M, OpX6aHint (5, 0x20, 0), {R1, MR3, IMM9b}},
+ {"ld1.c.clr.nt1", M, OpX6aHint (5, 0x20, 1), {R1, MR3, IMM9b}},
+ {"ld1.c.clr.nta", M, OpX6aHint (5, 0x20, 3), {R1, MR3, IMM9b}},
+ {"ld2.c.clr", M, OpX6aHint (5, 0x21, 0), {R1, MR3, IMM9b}},
+ {"ld2.c.clr.nt1", M, OpX6aHint (5, 0x21, 1), {R1, MR3, IMM9b}},
+ {"ld2.c.clr.nta", M, OpX6aHint (5, 0x21, 3), {R1, MR3, IMM9b}},
+ {"ld4.c.clr", M, OpX6aHint (5, 0x22, 0), {R1, MR3, IMM9b}},
+ {"ld4.c.clr.nt1", M, OpX6aHint (5, 0x22, 1), {R1, MR3, IMM9b}},
+ {"ld4.c.clr.nta", M, OpX6aHint (5, 0x22, 3), {R1, MR3, IMM9b}},
+ {"ld8.c.clr", M, OpX6aHint (5, 0x23, 0), {R1, MR3, IMM9b}},
+ {"ld8.c.clr.nt1", M, OpX6aHint (5, 0x23, 1), {R1, MR3, IMM9b}},
+ {"ld8.c.clr.nta", M, OpX6aHint (5, 0x23, 3), {R1, MR3, IMM9b}},
+ {"ld1.c.nc", M, OpX6aHint (5, 0x24, 0), {R1, MR3, IMM9b}},
+ {"ld1.c.nc.nt1", M, OpX6aHint (5, 0x24, 1), {R1, MR3, IMM9b}},
+ {"ld1.c.nc.nta", M, OpX6aHint (5, 0x24, 3), {R1, MR3, IMM9b}},
+ {"ld2.c.nc", M, OpX6aHint (5, 0x25, 0), {R1, MR3, IMM9b}},
+ {"ld2.c.nc.nt1", M, OpX6aHint (5, 0x25, 1), {R1, MR3, IMM9b}},
+ {"ld2.c.nc.nta", M, OpX6aHint (5, 0x25, 3), {R1, MR3, IMM9b}},
+ {"ld4.c.nc", M, OpX6aHint (5, 0x26, 0), {R1, MR3, IMM9b}},
+ {"ld4.c.nc.nt1", M, OpX6aHint (5, 0x26, 1), {R1, MR3, IMM9b}},
+ {"ld4.c.nc.nta", M, OpX6aHint (5, 0x26, 3), {R1, MR3, IMM9b}},
+ {"ld8.c.nc", M, OpX6aHint (5, 0x27, 0), {R1, MR3, IMM9b}},
+ {"ld8.c.nc.nt1", M, OpX6aHint (5, 0x27, 1), {R1, MR3, IMM9b}},
+ {"ld8.c.nc.nta", M, OpX6aHint (5, 0x27, 3), {R1, MR3, IMM9b}},
+ {"ld1.c.clr.acq", M, OpX6aHint (5, 0x28, 0), {R1, MR3, IMM9b}},
+ {"ld1.c.clr.acq.nt1", M, OpX6aHint (5, 0x28, 1), {R1, MR3, IMM9b}},
+ {"ld1.c.clr.acq.nta", M, OpX6aHint (5, 0x28, 3), {R1, MR3, IMM9b}},
+ {"ld2.c.clr.acq", M, OpX6aHint (5, 0x29, 0), {R1, MR3, IMM9b}},
+ {"ld2.c.clr.acq.nt1", M, OpX6aHint (5, 0x29, 1), {R1, MR3, IMM9b}},
+ {"ld2.c.clr.acq.nta", M, OpX6aHint (5, 0x29, 3), {R1, MR3, IMM9b}},
+ {"ld4.c.clr.acq", M, OpX6aHint (5, 0x2a, 0), {R1, MR3, IMM9b}},
+ {"ld4.c.clr.acq.nt1", M, OpX6aHint (5, 0x2a, 1), {R1, MR3, IMM9b}},
+ {"ld4.c.clr.acq.nta", M, OpX6aHint (5, 0x2a, 3), {R1, MR3, IMM9b}},
+ {"ld8.c.clr.acq", M, OpX6aHint (5, 0x2b, 0), {R1, MR3, IMM9b}},
+ {"ld8.c.clr.acq.nt1", M, OpX6aHint (5, 0x2b, 1), {R1, MR3, IMM9b}},
+ {"ld8.c.clr.acq.nta", M, OpX6aHint (5, 0x2b, 3), {R1, MR3, IMM9b}},
+
+ /* store w/increment by immediate */
+ {"st1", M, OpX6aHint (5, 0x30, 0), {MR3, R2, IMM9a}},
+ {"st1.nta", M, OpX6aHint (5, 0x30, 3), {MR3, R2, IMM9a}},
+ {"st2", M, OpX6aHint (5, 0x31, 0), {MR3, R2, IMM9a}},
+ {"st2.nta", M, OpX6aHint (5, 0x31, 3), {MR3, R2, IMM9a}},
+ {"st4", M, OpX6aHint (5, 0x32, 0), {MR3, R2, IMM9a}},
+ {"st4.nta", M, OpX6aHint (5, 0x32, 3), {MR3, R2, IMM9a}},
+ {"st8", M, OpX6aHint (5, 0x33, 0), {MR3, R2, IMM9a}},
+ {"st8.nta", M, OpX6aHint (5, 0x33, 3), {MR3, R2, IMM9a}},
+ {"st1.rel", M, OpX6aHint (5, 0x34, 0), {MR3, R2, IMM9a}},
+ {"st1.rel.nta", M, OpX6aHint (5, 0x34, 3), {MR3, R2, IMM9a}},
+ {"st2.rel", M, OpX6aHint (5, 0x35, 0), {MR3, R2, IMM9a}},
+ {"st2.rel.nta", M, OpX6aHint (5, 0x35, 3), {MR3, R2, IMM9a}},
+ {"st4.rel", M, OpX6aHint (5, 0x36, 0), {MR3, R2, IMM9a}},
+ {"st4.rel.nta", M, OpX6aHint (5, 0x36, 3), {MR3, R2, IMM9a}},
+ {"st8.rel", M, OpX6aHint (5, 0x37, 0), {MR3, R2, IMM9a}},
+ {"st8.rel.nta", M, OpX6aHint (5, 0x37, 3), {MR3, R2, IMM9a}},
+ {"st8.spill", M, OpX6aHint (5, 0x3b, 0), {MR3, R2, IMM9a}},
+ {"st8.spill.nta", M, OpX6aHint (5, 0x3b, 3), {MR3, R2, IMM9a}},
+
+ /* floating-point load */
+ {"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}},
+ {"ldfs.nt1", M, OpMXX6aHint (6, 0, 0, 0x02, 1), {F1, MR3}},
+ {"ldfs.nta", M, OpMXX6aHint (6, 0, 0, 0x02, 3), {F1, MR3}},
+ {"ldfd", M, OpMXX6aHint (6, 0, 0, 0x03, 0), {F1, MR3}},
+ {"ldfd.nt1", M, OpMXX6aHint (6, 0, 0, 0x03, 1), {F1, MR3}},
+ {"ldfd.nta", M, OpMXX6aHint (6, 0, 0, 0x03, 3), {F1, MR3}},
+ {"ldf8", M, OpMXX6aHint (6, 0, 0, 0x01, 0), {F1, MR3}},
+ {"ldf8.nt1", M, OpMXX6aHint (6, 0, 0, 0x01, 1), {F1, MR3}},
+ {"ldf8.nta", M, OpMXX6aHint (6, 0, 0, 0x01, 3), {F1, MR3}},
+ {"ldfe", M, OpMXX6aHint (6, 0, 0, 0x00, 0), {F1, MR3}},
+ {"ldfe.nt1", M, OpMXX6aHint (6, 0, 0, 0x00, 1), {F1, MR3}},
+ {"ldfe.nta", M, OpMXX6aHint (6, 0, 0, 0x00, 3), {F1, MR3}},
+ {"ldfs.s", M, OpMXX6aHint (6, 0, 0, 0x06, 0), {F1, MR3}},
+ {"ldfs.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x06, 1), {F1, MR3}},
+ {"ldfs.s.nta", M, OpMXX6aHint (6, 0, 0, 0x06, 3), {F1, MR3}},
+ {"ldfd.s", M, OpMXX6aHint (6, 0, 0, 0x07, 0), {F1, MR3}},
+ {"ldfd.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x07, 1), {F1, MR3}},
+ {"ldfd.s.nta", M, OpMXX6aHint (6, 0, 0, 0x07, 3), {F1, MR3}},
+ {"ldf8.s", M, OpMXX6aHint (6, 0, 0, 0x05, 0), {F1, MR3}},
+ {"ldf8.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x05, 1), {F1, MR3}},
+ {"ldf8.s.nta", M, OpMXX6aHint (6, 0, 0, 0x05, 3), {F1, MR3}},
+ {"ldfe.s", M, OpMXX6aHint (6, 0, 0, 0x04, 0), {F1, MR3}},
+ {"ldfe.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x04, 1), {F1, MR3}},
+ {"ldfe.s.nta", M, OpMXX6aHint (6, 0, 0, 0x04, 3), {F1, MR3}},
+ {"ldfs.a", M, OpMXX6aHint (6, 0, 0, 0x0a, 0), {F1, MR3}},
+ {"ldfs.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0a, 1), {F1, MR3}},
+ {"ldfs.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0a, 3), {F1, MR3}},
+ {"ldfd.a", M, OpMXX6aHint (6, 0, 0, 0x0b, 0), {F1, MR3}},
+ {"ldfd.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0b, 1), {F1, MR3}},
+ {"ldfd.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0b, 3), {F1, MR3}},
+ {"ldf8.a", M, OpMXX6aHint (6, 0, 0, 0x09, 0), {F1, MR3}},
+ {"ldf8.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x09, 1), {F1, MR3}},
+ {"ldf8.a.nta", M, OpMXX6aHint (6, 0, 0, 0x09, 3), {F1, MR3}},
+ {"ldfe.a", M, OpMXX6aHint (6, 0, 0, 0x08, 0), {F1, MR3}},
+ {"ldfe.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x08, 1), {F1, MR3}},
+ {"ldfe.a.nta", M, OpMXX6aHint (6, 0, 0, 0x08, 3), {F1, MR3}},
+ {"ldfs.sa", M, OpMXX6aHint (6, 0, 0, 0x0e, 0), {F1, MR3}},
+ {"ldfs.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0e, 1), {F1, MR3}},
+ {"ldfs.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0e, 3), {F1, MR3}},
+ {"ldfd.sa", M, OpMXX6aHint (6, 0, 0, 0x0f, 0), {F1, MR3}},
+ {"ldfd.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0f, 1), {F1, MR3}},
+ {"ldfd.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0f, 3), {F1, MR3}},
+ {"ldf8.sa", M, OpMXX6aHint (6, 0, 0, 0x0d, 0), {F1, MR3}},
+ {"ldf8.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0d, 1), {F1, MR3}},
+ {"ldf8.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0d, 3), {F1, MR3}},
+ {"ldfe.sa", M, OpMXX6aHint (6, 0, 0, 0x0c, 0), {F1, MR3}},
+ {"ldfe.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0c, 1), {F1, MR3}},
+ {"ldfe.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0c, 3), {F1, MR3}},
+ {"ldf.fill", M, OpMXX6aHint (6, 0, 0, 0x1b, 0), {F1, MR3}},
+ {"ldf.fill.nt1", M, OpMXX6aHint (6, 0, 0, 0x1b, 1), {F1, MR3}},
+ {"ldf.fill.nta", M, OpMXX6aHint (6, 0, 0, 0x1b, 3), {F1, MR3}},
+ {"ldfs.c.clr", M, OpMXX6aHint (6, 0, 0, 0x22, 0), {F1, MR3}},
+ {"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x22, 1), {F1, MR3}},
+ {"ldfs.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x22, 3), {F1, MR3}},
+ {"ldfd.c.clr", M, OpMXX6aHint (6, 0, 0, 0x23, 0), {F1, MR3}},
+ {"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x23, 1), {F1, MR3}},
+ {"ldfd.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x23, 3), {F1, MR3}},
+ {"ldf8.c.clr", M, OpMXX6aHint (6, 0, 0, 0x21, 0), {F1, MR3}},
+ {"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x21, 1), {F1, MR3}},
+ {"ldf8.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x21, 3), {F1, MR3}},
+ {"ldfe.c.clr", M, OpMXX6aHint (6, 0, 0, 0x20, 0), {F1, MR3}},
+ {"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x20, 1), {F1, MR3}},
+ {"ldfe.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x20, 3), {F1, MR3}},
+ {"ldfs.c.nc", M, OpMXX6aHint (6, 0, 0, 0x26, 0), {F1, MR3}},
+ {"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x26, 1), {F1, MR3}},
+ {"ldfs.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x26, 3), {F1, MR3}},
+ {"ldfd.c.nc", M, OpMXX6aHint (6, 0, 0, 0x27, 0), {F1, MR3}},
+ {"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x27, 1), {F1, MR3}},
+ {"ldfd.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x27, 3), {F1, MR3}},
+ {"ldf8.c.nc", M, OpMXX6aHint (6, 0, 0, 0x25, 0), {F1, MR3}},
+ {"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x25, 1), {F1, MR3}},
+ {"ldf8.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x25, 3), {F1, MR3}},
+ {"ldfe.c.nc", M, OpMXX6aHint (6, 0, 0, 0x24, 0), {F1, MR3}},
+ {"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x24, 1), {F1, MR3}},
+ {"ldfe.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x24, 3), {F1, MR3}},
+
+ {"ldfs", M, OpMXX6aHint (6, 1, 0, 0x02, 0), {F1, MR3, R2}},
+ {"ldfs.nt1", M, OpMXX6aHint (6, 1, 0, 0x02, 1), {F1, MR3, R2}},
+ {"ldfs.nta", M, OpMXX6aHint (6, 1, 0, 0x02, 3), {F1, MR3, R2}},
+ {"ldfd", M, OpMXX6aHint (6, 1, 0, 0x03, 0), {F1, MR3, R2}},
+ {"ldfd.nt1", M, OpMXX6aHint (6, 1, 0, 0x03, 1), {F1, MR3, R2}},
+ {"ldfd.nta", M, OpMXX6aHint (6, 1, 0, 0x03, 3), {F1, MR3, R2}},
+ {"ldf8", M, OpMXX6aHint (6, 1, 0, 0x01, 0), {F1, MR3, R2}},
+ {"ldf8.nt1", M, OpMXX6aHint (6, 1, 0, 0x01, 1), {F1, MR3, R2}},
+ {"ldf8.nta", M, OpMXX6aHint (6, 1, 0, 0x01, 3), {F1, MR3, R2}},
+ {"ldfe", M, OpMXX6aHint (6, 1, 0, 0x00, 0), {F1, MR3, R2}},
+ {"ldfe.nt1", M, OpMXX6aHint (6, 1, 0, 0x00, 1), {F1, MR3, R2}},
+ {"ldfe.nta", M, OpMXX6aHint (6, 1, 0, 0x00, 3), {F1, MR3, R2}},
+ {"ldfs.s", M, OpMXX6aHint (6, 1, 0, 0x06, 0), {F1, MR3, R2}},
+ {"ldfs.s.nt1", M, OpMXX6aHint (6, 1, 0, 0x06, 1), {F1, MR3, R2}},
+ {"ldfs.s.nta", M, OpMXX6aHint (6, 1, 0, 0x06, 3), {F1, MR3, R2}},
+ {"ldfd.s", M, OpMXX6aHint (6, 1, 0, 0x07, 0), {F1, MR3, R2}},
+ {"ldfd.s.nt1", M, OpMXX6aHint (6, 1, 0, 0x07, 1), {F1, MR3, R2}},
+ {"ldfd.s.nta", M, OpMXX6aHint (6, 1, 0, 0x07, 3), {F1, MR3, R2}},
+ {"ldf8.s", M, OpMXX6aHint (6, 1, 0, 0x05, 0), {F1, MR3, R2}},
+ {"ldf8.s.nt1", M, OpMXX6aHint (6, 1, 0, 0x05, 1), {F1, MR3, R2}},
+ {"ldf8.s.nta", M, OpMXX6aHint (6, 1, 0, 0x05, 3), {F1, MR3, R2}},
+ {"ldfe.s", M, OpMXX6aHint (6, 1, 0, 0x04, 0), {F1, MR3, R2}},
+ {"ldfe.s.nt1", M, OpMXX6aHint (6, 1, 0, 0x04, 1), {F1, MR3, R2}},
+ {"ldfe.s.nta", M, OpMXX6aHint (6, 1, 0, 0x04, 3), {F1, MR3, R2}},
+ {"ldfs.a", M, OpMXX6aHint (6, 1, 0, 0x0a, 0), {F1, MR3, R2}},
+ {"ldfs.a.nt1", M, OpMXX6aHint (6, 1, 0, 0x0a, 1), {F1, MR3, R2}},
+ {"ldfs.a.nta", M, OpMXX6aHint (6, 1, 0, 0x0a, 3), {F1, MR3, R2}},
+ {"ldfd.a", M, OpMXX6aHint (6, 1, 0, 0x0b, 0), {F1, MR3, R2}},
+ {"ldfd.a.nt1", M, OpMXX6aHint (6, 1, 0, 0x0b, 1), {F1, MR3, R2}},
+ {"ldfd.a.nta", M, OpMXX6aHint (6, 1, 0, 0x0b, 3), {F1, MR3, R2}},
+ {"ldf8.a", M, OpMXX6aHint (6, 1, 0, 0x09, 0), {F1, MR3, R2}},
+ {"ldf8.a.nt1", M, OpMXX6aHint (6, 1, 0, 0x09, 1), {F1, MR3, R2}},
+ {"ldf8.a.nta", M, OpMXX6aHint (6, 1, 0, 0x09, 3), {F1, MR3, R2}},
+ {"ldfe.a", M, OpMXX6aHint (6, 1, 0, 0x08, 0), {F1, MR3, R2}},
+ {"ldfe.a.nt1", M, OpMXX6aHint (6, 1, 0, 0x08, 1), {F1, MR3, R2}},
+ {"ldfe.a.nta", M, OpMXX6aHint (6, 1, 0, 0x08, 3), {F1, MR3, R2}},
+ {"ldfs.sa", M, OpMXX6aHint (6, 1, 0, 0x0e, 0), {F1, MR3, R2}},
+ {"ldfs.sa.nt1", M, OpMXX6aHint (6, 1, 0, 0x0e, 1), {F1, MR3, R2}},
+ {"ldfs.sa.nta", M, OpMXX6aHint (6, 1, 0, 0x0e, 3), {F1, MR3, R2}},
+ {"ldfd.sa", M, OpMXX6aHint (6, 1, 0, 0x0f, 0), {F1, MR3, R2}},
+ {"ldfd.sa.nt1", M, OpMXX6aHint (6, 1, 0, 0x0f, 1), {F1, MR3, R2}},
+ {"ldfd.sa.nta", M, OpMXX6aHint (6, 1, 0, 0x0f, 3), {F1, MR3, R2}},
+ {"ldf8.sa", M, OpMXX6aHint (6, 1, 0, 0x0d, 0), {F1, MR3, R2}},
+ {"ldf8.sa.nt1", M, OpMXX6aHint (6, 1, 0, 0x0d, 1), {F1, MR3, R2}},
+ {"ldf8.sa.nta", M, OpMXX6aHint (6, 1, 0, 0x0d, 3), {F1, MR3, R2}},
+ {"ldfe.sa", M, OpMXX6aHint (6, 1, 0, 0x0c, 0), {F1, MR3, R2}},
+ {"ldfe.sa.nt1", M, OpMXX6aHint (6, 1, 0, 0x0c, 1), {F1, MR3, R2}},
+ {"ldfe.sa.nta", M, OpMXX6aHint (6, 1, 0, 0x0c, 3), {F1, MR3, R2}},
+ {"ldf.fill", M, OpMXX6aHint (6, 1, 0, 0x1b, 0), {F1, MR3, R2}},
+ {"ldf.fill.nt1", M, OpMXX6aHint (6, 1, 0, 0x1b, 1), {F1, MR3, R2}},
+ {"ldf.fill.nta", M, OpMXX6aHint (6, 1, 0, 0x1b, 3), {F1, MR3, R2}},
+ {"ldfs.c.clr", M, OpMXX6aHint (6, 1, 0, 0x22, 0), {F1, MR3, R2}},
+ {"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 1, 0, 0x22, 1), {F1, MR3, R2}},
+ {"ldfs.c.clr.nta", M, OpMXX6aHint (6, 1, 0, 0x22, 3), {F1, MR3, R2}},
+ {"ldfd.c.clr", M, OpMXX6aHint (6, 1, 0, 0x23, 0), {F1, MR3, R2}},
+ {"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 1, 0, 0x23, 1), {F1, MR3, R2}},
+ {"ldfd.c.clr.nta", M, OpMXX6aHint (6, 1, 0, 0x23, 3), {F1, MR3, R2}},
+ {"ldf8.c.clr", M, OpMXX6aHint (6, 1, 0, 0x21, 0), {F1, MR3, R2}},
+ {"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 1, 0, 0x21, 1), {F1, MR3, R2}},
+ {"ldf8.c.clr.nta", M, OpMXX6aHint (6, 1, 0, 0x21, 3), {F1, MR3, R2}},
+ {"ldfe.c.clr", M, OpMXX6aHint (6, 1, 0, 0x20, 0), {F1, MR3, R2}},
+ {"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 1, 0, 0x20, 1), {F1, MR3, R2}},
+ {"ldfe.c.clr.nta", M, OpMXX6aHint (6, 1, 0, 0x20, 3), {F1, MR3, R2}},
+ {"ldfs.c.nc", M, OpMXX6aHint (6, 1, 0, 0x26, 0), {F1, MR3, R2}},
+ {"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 1, 0, 0x26, 1), {F1, MR3, R2}},
+ {"ldfs.c.nc.nta", M, OpMXX6aHint (6, 1, 0, 0x26, 3), {F1, MR3, R2}},
+ {"ldfd.c.nc", M, OpMXX6aHint (6, 1, 0, 0x27, 0), {F1, MR3, R2}},
+ {"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 1, 0, 0x27, 1), {F1, MR3, R2}},
+ {"ldfd.c.nc.nta", M, OpMXX6aHint (6, 1, 0, 0x27, 3), {F1, MR3, R2}},
+ {"ldf8.c.nc", M, OpMXX6aHint (6, 1, 0, 0x25, 0), {F1, MR3, R2}},
+ {"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 1, 0, 0x25, 1), {F1, MR3, R2}},
+ {"ldf8.c.nc.nta", M, OpMXX6aHint (6, 1, 0, 0x25, 3), {F1, MR3, R2}},
+ {"ldfe.c.nc", M, OpMXX6aHint (6, 1, 0, 0x24, 0), {F1, MR3, R2}},
+ {"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 1, 0, 0x24, 1), {F1, MR3, R2}},
+ {"ldfe.c.nc.nta", M, OpMXX6aHint (6, 1, 0, 0x24, 3), {F1, MR3, R2}},
+
+ /* floating-point store */
+ {"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}},
+ {"stfs.nta", M, OpMXX6aHint (6, 0, 0, 0x32, 3), {MR3, F2}},
+ {"stfd", M, OpMXX6aHint (6, 0, 0, 0x33, 0), {MR3, F2}},
+ {"stfd.nta", M, OpMXX6aHint (6, 0, 0, 0x33, 3), {MR3, F2}},
+ {"stf8", M, OpMXX6aHint (6, 0, 0, 0x31, 0), {MR3, F2}},
+ {"stf8.nta", M, OpMXX6aHint (6, 0, 0, 0x31, 3), {MR3, F2}},
+ {"stfe", M, OpMXX6aHint (6, 0, 0, 0x30, 0), {MR3, F2}},
+ {"stfe.nta", M, OpMXX6aHint (6, 0, 0, 0x30, 3), {MR3, F2}},
+ {"stf.spill", M, OpMXX6aHint (6, 0, 0, 0x3b, 0), {MR3, F2}},
+ {"stf.spill.nta", M, OpMXX6aHint (6, 0, 0, 0x3b, 3), {MR3, F2}},
+
+ /* floating-point load pair */
+ {"ldfps", M2, OpMXX6aHint (6, 0, 1, 0x02, 0), {F1, F2, MR3}},
+ {"ldfps.nt1", M2, OpMXX6aHint (6, 0, 1, 0x02, 1), {F1, F2, MR3}},
+ {"ldfps.nta", M2, OpMXX6aHint (6, 0, 1, 0x02, 3), {F1, F2, MR3}},
+ {"ldfpd", M2, OpMXX6aHint (6, 0, 1, 0x03, 0), {F1, F2, MR3}},
+ {"ldfpd.nt1", M2, OpMXX6aHint (6, 0, 1, 0x03, 1), {F1, F2, MR3}},
+ {"ldfpd.nta", M2, OpMXX6aHint (6, 0, 1, 0x03, 3), {F1, F2, MR3}},
+ {"ldfp8", M2, OpMXX6aHint (6, 0, 1, 0x01, 0), {F1, F2, MR3}},
+ {"ldfp8.nt1", M2, OpMXX6aHint (6, 0, 1, 0x01, 1), {F1, F2, MR3}},
+ {"ldfp8.nta", M2, OpMXX6aHint (6, 0, 1, 0x01, 3), {F1, F2, MR3}},
+ {"ldfps.s", M2, OpMXX6aHint (6, 0, 1, 0x06, 0), {F1, F2, MR3}},
+ {"ldfps.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x06, 1), {F1, F2, MR3}},
+ {"ldfps.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x06, 3), {F1, F2, MR3}},
+ {"ldfpd.s", M2, OpMXX6aHint (6, 0, 1, 0x07, 0), {F1, F2, MR3}},
+ {"ldfpd.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x07, 1), {F1, F2, MR3}},
+ {"ldfpd.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x07, 3), {F1, F2, MR3}},
+ {"ldfp8.s", M2, OpMXX6aHint (6, 0, 1, 0x05, 0), {F1, F2, MR3}},
+ {"ldfp8.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x05, 1), {F1, F2, MR3}},
+ {"ldfp8.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x05, 3), {F1, F2, MR3}},
+ {"ldfps.a", M2, OpMXX6aHint (6, 0, 1, 0x0a, 0), {F1, F2, MR3}},
+ {"ldfps.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0a, 1), {F1, F2, MR3}},
+ {"ldfps.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0a, 3), {F1, F2, MR3}},
+ {"ldfpd.a", M2, OpMXX6aHint (6, 0, 1, 0x0b, 0), {F1, F2, MR3}},
+ {"ldfpd.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0b, 1), {F1, F2, MR3}},
+ {"ldfpd.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0b, 3), {F1, F2, MR3}},
+ {"ldfp8.a", M2, OpMXX6aHint (6, 0, 1, 0x09, 0), {F1, F2, MR3}},
+ {"ldfp8.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x09, 1), {F1, F2, MR3}},
+ {"ldfp8.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x09, 3), {F1, F2, MR3}},
+ {"ldfps.sa", M2, OpMXX6aHint (6, 0, 1, 0x0e, 0), {F1, F2, MR3}},
+ {"ldfps.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0e, 1), {F1, F2, MR3}},
+ {"ldfps.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0e, 3), {F1, F2, MR3}},
+ {"ldfpd.sa", M2, OpMXX6aHint (6, 0, 1, 0x0f, 0), {F1, F2, MR3}},
+ {"ldfpd.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0f, 1), {F1, F2, MR3}},
+ {"ldfpd.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0f, 3), {F1, F2, MR3}},
+ {"ldfp8.sa", M2, OpMXX6aHint (6, 0, 1, 0x0d, 0), {F1, F2, MR3}},
+ {"ldfp8.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0d, 1), {F1, F2, MR3}},
+ {"ldfp8.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0d, 3), {F1, F2, MR3}},
+ {"ldfps.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x22, 0), {F1, F2, MR3}},
+ {"ldfps.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x22, 1), {F1, F2, MR3}},
+ {"ldfps.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x22, 3), {F1, F2, MR3}},
+ {"ldfpd.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x23, 0), {F1, F2, MR3}},
+ {"ldfpd.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x23, 1), {F1, F2, MR3}},
+ {"ldfpd.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x23, 3), {F1, F2, MR3}},
+ {"ldfp8.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x21, 0), {F1, F2, MR3}},
+ {"ldfp8.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x21, 1), {F1, F2, MR3}},
+ {"ldfp8.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x21, 3), {F1, F2, MR3}},
+ {"ldfps.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x26, 0), {F1, F2, MR3}},
+ {"ldfps.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x26, 1), {F1, F2, MR3}},
+ {"ldfps.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x26, 3), {F1, F2, MR3}},
+ {"ldfpd.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x27, 0), {F1, F2, MR3}},
+ {"ldfpd.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x27, 1), {F1, F2, MR3}},
+ {"ldfpd.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x27, 3), {F1, F2, MR3}},
+ {"ldfp8.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x25, 0), {F1, F2, MR3}},
+ {"ldfp8.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x25, 1), {F1, F2, MR3}},
+ {"ldfp8.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x25, 3), {F1, F2, MR3}},
+
+ /* floating-point load pair w/increment by immediate */
+#define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}
+ {"ldfps", LD (0x02, 0, C8)},
+ {"ldfps.nt1", LD (0x02, 1, C8)},
+ {"ldfps.nta", LD (0x02, 3, C8)},
+ {"ldfpd", LD (0x03, 0, C16)},
+ {"ldfpd.nt1", LD (0x03, 1, C16)},
+ {"ldfpd.nta", LD (0x03, 3, C16)},
+ {"ldfp8", LD (0x01, 0, C16)},
+ {"ldfp8.nt1", LD (0x01, 1, C16)},
+ {"ldfp8.nta", LD (0x01, 3, C16)},
+ {"ldfps.s", LD (0x06, 0, C8)},
+ {"ldfps.s.nt1", LD (0x06, 1, C8)},
+ {"ldfps.s.nta", LD (0x06, 3, C8)},
+ {"ldfpd.s", LD (0x07, 0, C16)},
+ {"ldfpd.s.nt1", LD (0x07, 1, C16)},
+ {"ldfpd.s.nta", LD (0x07, 3, C16)},
+ {"ldfp8.s", LD (0x05, 0, C16)},
+ {"ldfp8.s.nt1", LD (0x05, 1, C16)},
+ {"ldfp8.s.nta", LD (0x05, 3, C16)},
+ {"ldfps.a", LD (0x0a, 0, C8)},
+ {"ldfps.a.nt1", LD (0x0a, 1, C8)},
+ {"ldfps.a.nta", LD (0x0a, 3, C8)},
+ {"ldfpd.a", LD (0x0b, 0, C16)},
+ {"ldfpd.a.nt1", LD (0x0b, 1, C16)},
+ {"ldfpd.a.nta", LD (0x0b, 3, C16)},
+ {"ldfp8.a", LD (0x09, 0, C16)},
+ {"ldfp8.a.nt1", LD (0x09, 1, C16)},
+ {"ldfp8.a.nta", LD (0x09, 3, C16)},
+ {"ldfps.sa", LD (0x0e, 0, C8)},
+ {"ldfps.sa.nt1", LD (0x0e, 1, C8)},
+ {"ldfps.sa.nta", LD (0x0e, 3, C8)},
+ {"ldfpd.sa", LD (0x0f, 0, C16)},
+ {"ldfpd.sa.nt1", LD (0x0f, 1, C16)},
+ {"ldfpd.sa.nta", LD (0x0f, 3, C16)},
+ {"ldfp8.sa", LD (0x0d, 0, C16)},
+ {"ldfp8.sa.nt1", LD (0x0d, 1, C16)},
+ {"ldfp8.sa.nta", LD (0x0d, 3, C16)},
+ {"ldfps.c.clr", LD (0x22, 0, C8)},
+ {"ldfps.c.clr.nt1", LD (0x22, 1, C8)},
+ {"ldfps.c.clr.nta", LD (0x22, 3, C8)},
+ {"ldfpd.c.clr", LD (0x23, 0, C16)},
+ {"ldfpd.c.clr.nt1", LD (0x23, 1, C16)},
+ {"ldfpd.c.clr.nta", LD (0x23, 3, C16)},
+ {"ldfp8.c.clr", LD (0x21, 0, C16)},
+ {"ldfp8.c.clr.nt1", LD (0x21, 1, C16)},
+ {"ldfp8.c.clr.nta", LD (0x21, 3, C16)},
+ {"ldfps.c.nc", LD (0x26, 0, C8)},
+ {"ldfps.c.nc.nt1", LD (0x26, 1, C8)},
+ {"ldfps.c.nc.nta", LD (0x26, 3, C8)},
+ {"ldfpd.c.nc", LD (0x27, 0, C16)},
+ {"ldfpd.c.nc.nt1", LD (0x27, 1, C16)},
+ {"ldfpd.c.nc.nta", LD (0x27, 3, C16)},
+ {"ldfp8.c.nc", LD (0x25, 0, C16)},
+ {"ldfp8.c.nc.nt1", LD (0x25, 1, C16)},
+ {"ldfp8.c.nc.nta", LD (0x25, 3, C16)},
+#undef LD
+
+ /* line prefetch */
+ {"lfetch", M0, OpMXX6aHint (6, 0, 0, 0x2c, 0), {MR3}},
+ {"lfetch.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2c, 1), {MR3}},
+ {"lfetch.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2c, 2), {MR3}},
+ {"lfetch.nta", M0, OpMXX6aHint (6, 0, 0, 0x2c, 3), {MR3}},
+ {"lfetch.excl", M0, OpMXX6aHint (6, 0, 0, 0x2d, 0), {MR3}},
+ {"lfetch.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2d, 1), {MR3}},
+ {"lfetch.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2d, 2), {MR3}},
+ {"lfetch.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2d, 3), {MR3}},
+ {"lfetch.fault", M0, OpMXX6aHint (6, 0, 0, 0x2e, 0), {MR3}},
+ {"lfetch.fault.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2e, 1), {MR3}},
+ {"lfetch.fault.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2e, 2), {MR3}},
+ {"lfetch.fault.nta", M0, OpMXX6aHint (6, 0, 0, 0x2e, 3), {MR3}},
+ {"lfetch.fault.excl", M0, OpMXX6aHint (6, 0, 0, 0x2f, 0), {MR3}},
+ {"lfetch.fault.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2f, 1), {MR3}},
+ {"lfetch.fault.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2f, 2), {MR3}},
+ {"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2f, 3), {MR3}},
+
+ /* line prefetch w/increment by register */
+ {"lfetch", M0, OpMXX6aHint (6, 1, 0, 0x2c, 0), {MR3, R2}},
+ {"lfetch.nt1", M0, OpMXX6aHint (6, 1, 0, 0x2c, 1), {MR3, R2}},
+ {"lfetch.nt2", M0, OpMXX6aHint (6, 1, 0, 0x2c, 2), {MR3, R2}},
+ {"lfetch.nta", M0, OpMXX6aHint (6, 1, 0, 0x2c, 3), {MR3, R2}},
+ {"lfetch.excl", M0, OpMXX6aHint (6, 1, 0, 0x2d, 0), {MR3, R2}},
+ {"lfetch.excl.nt1", M0, OpMXX6aHint (6, 1, 0, 0x2d, 1), {MR3, R2}},
+ {"lfetch.excl.nt2", M0, OpMXX6aHint (6, 1, 0, 0x2d, 2), {MR3, R2}},
+ {"lfetch.excl.nta", M0, OpMXX6aHint (6, 1, 0, 0x2d, 3), {MR3, R2}},
+ {"lfetch.fault", M0, OpMXX6aHint (6, 1, 0, 0x2e, 0), {MR3, R2}},
+ {"lfetch.fault.nt1", M0, OpMXX6aHint (6, 1, 0, 0x2e, 1), {MR3, R2}},
+ {"lfetch.fault.nt2", M0, OpMXX6aHint (6, 1, 0, 0x2e, 2), {MR3, R2}},
+ {"lfetch.fault.nta", M0, OpMXX6aHint (6, 1, 0, 0x2e, 3), {MR3, R2}},
+ {"lfetch.fault.excl", M0, OpMXX6aHint (6, 1, 0, 0x2f, 0), {MR3, R2}},
+ {"lfetch.fault.excl.nt1", M0, OpMXX6aHint (6, 1, 0, 0x2f, 1), {MR3, R2}},
+ {"lfetch.fault.excl.nt2", M0, OpMXX6aHint (6, 1, 0, 0x2f, 2), {MR3, R2}},
+ {"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 1, 0, 0x2f, 3), {MR3, R2}},
+
+ /* semaphore operations */
+ {"setf.sig", M, OpMXX6a (6, 0, 1, 0x1c), {F1, R2}},
+ {"setf.exp", M, OpMXX6a (6, 0, 1, 0x1d), {F1, R2}},
+ {"setf.s", M, OpMXX6a (6, 0, 1, 0x1e), {F1, R2}},
+ {"setf.d", M, OpMXX6a (6, 0, 1, 0x1f), {F1, R2}},
+
+ {"ldfs", M, OpX6aHint (7, 0x02, 0), {F1, MR3, IMM9b}},
+ {"ldfs.nt1", M, OpX6aHint (7, 0x02, 1), {F1, MR3, IMM9b}},
+ {"ldfs.nta", M, OpX6aHint (7, 0x02, 3), {F1, MR3, IMM9b}},
+ {"ldfd", M, OpX6aHint (7, 0x03, 0), {F1, MR3, IMM9b}},
+ {"ldfd.nt1", M, OpX6aHint (7, 0x03, 1), {F1, MR3, IMM9b}},
+ {"ldfd.nta", M, OpX6aHint (7, 0x03, 3), {F1, MR3, IMM9b}},
+ {"ldf8", M, OpX6aHint (7, 0x01, 0), {F1, MR3, IMM9b}},
+ {"ldf8.nt1", M, OpX6aHint (7, 0x01, 1), {F1, MR3, IMM9b}},
+ {"ldf8.nta", M, OpX6aHint (7, 0x01, 3), {F1, MR3, IMM9b}},
+ {"ldfe", M, OpX6aHint (7, 0x00, 0), {F1, MR3, IMM9b}},
+ {"ldfe.nt1", M, OpX6aHint (7, 0x00, 1), {F1, MR3, IMM9b}},
+ {"ldfe.nta", M, OpX6aHint (7, 0x00, 3), {F1, MR3, IMM9b}},
+ {"ldfs.s", M, OpX6aHint (7, 0x06, 0), {F1, MR3, IMM9b}},
+ {"ldfs.s.nt1", M, OpX6aHint (7, 0x06, 1), {F1, MR3, IMM9b}},
+ {"ldfs.s.nta", M, OpX6aHint (7, 0x06, 3), {F1, MR3, IMM9b}},
+ {"ldfd.s", M, OpX6aHint (7, 0x07, 0), {F1, MR3, IMM9b}},
+ {"ldfd.s.nt1", M, OpX6aHint (7, 0x07, 1), {F1, MR3, IMM9b}},
+ {"ldfd.s.nta", M, OpX6aHint (7, 0x07, 3), {F1, MR3, IMM9b}},
+ {"ldf8.s", M, OpX6aHint (7, 0x05, 0), {F1, MR3, IMM9b}},
+ {"ldf8.s.nt1", M, OpX6aHint (7, 0x05, 1), {F1, MR3, IMM9b}},
+ {"ldf8.s.nta", M, OpX6aHint (7, 0x05, 3), {F1, MR3, IMM9b}},
+ {"ldfe.s", M, OpX6aHint (7, 0x04, 0), {F1, MR3, IMM9b}},
+ {"ldfe.s.nt1", M, OpX6aHint (7, 0x04, 1), {F1, MR3, IMM9b}},
+ {"ldfe.s.nta", M, OpX6aHint (7, 0x04, 3), {F1, MR3, IMM9b}},
+ {"ldfs.a", M, OpX6aHint (7, 0x0a, 0), {F1, MR3, IMM9b}},
+ {"ldfs.a.nt1", M, OpX6aHint (7, 0x0a, 1), {F1, MR3, IMM9b}},
+ {"ldfs.a.nta", M, OpX6aHint (7, 0x0a, 3), {F1, MR3, IMM9b}},
+ {"ldfd.a", M, OpX6aHint (7, 0x0b, 0), {F1, MR3, IMM9b}},
+ {"ldfd.a.nt1", M, OpX6aHint (7, 0x0b, 1), {F1, MR3, IMM9b}},
+ {"ldfd.a.nta", M, OpX6aHint (7, 0x0b, 3), {F1, MR3, IMM9b}},
+ {"ldf8.a", M, OpX6aHint (7, 0x09, 0), {F1, MR3, IMM9b}},
+ {"ldf8.a.nt1", M, OpX6aHint (7, 0x09, 1), {F1, MR3, IMM9b}},
+ {"ldf8.a.nta", M, OpX6aHint (7, 0x09, 3), {F1, MR3, IMM9b}},
+ {"ldfe.a", M, OpX6aHint (7, 0x08, 0), {F1, MR3, IMM9b}},
+ {"ldfe.a.nt1", M, OpX6aHint (7, 0x08, 1), {F1, MR3, IMM9b}},
+ {"ldfe.a.nta", M, OpX6aHint (7, 0x08, 3), {F1, MR3, IMM9b}},
+ {"ldfs.sa", M, OpX6aHint (7, 0x0e, 0), {F1, MR3, IMM9b}},
+ {"ldfs.sa.nt1", M, OpX6aHint (7, 0x0e, 1), {F1, MR3, IMM9b}},
+ {"ldfs.sa.nta", M, OpX6aHint (7, 0x0e, 3), {F1, MR3, IMM9b}},
+ {"ldfd.sa", M, OpX6aHint (7, 0x0f, 0), {F1, MR3, IMM9b}},
+ {"ldfd.sa.nt1", M, OpX6aHint (7, 0x0f, 1), {F1, MR3, IMM9b}},
+ {"ldfd.sa.nta", M, OpX6aHint (7, 0x0f, 3), {F1, MR3, IMM9b}},
+ {"ldf8.sa", M, OpX6aHint (7, 0x0d, 0), {F1, MR3, IMM9b}},
+ {"ldf8.sa.nt1", M, OpX6aHint (7, 0x0d, 1), {F1, MR3, IMM9b}},
+ {"ldf8.sa.nta", M, OpX6aHint (7, 0x0d, 3), {F1, MR3, IMM9b}},
+ {"ldfe.sa", M, OpX6aHint (7, 0x0c, 0), {F1, MR3, IMM9b}},
+ {"ldfe.sa.nt1", M, OpX6aHint (7, 0x0c, 1), {F1, MR3, IMM9b}},
+ {"ldfe.sa.nta", M, OpX6aHint (7, 0x0c, 3), {F1, MR3, IMM9b}},
+ {"ldf.fill", M, OpX6aHint (7, 0x1b, 0), {F1, MR3, IMM9b}},
+ {"ldf.fill.nt1", M, OpX6aHint (7, 0x1b, 1), {F1, MR3, IMM9b}},
+ {"ldf.fill.nta", M, OpX6aHint (7, 0x1b, 3), {F1, MR3, IMM9b}},
+ {"ldfs.c.clr", M, OpX6aHint (7, 0x22, 0), {F1, MR3, IMM9b}},
+ {"ldfs.c.clr.nt1", M, OpX6aHint (7, 0x22, 1), {F1, MR3, IMM9b}},
+ {"ldfs.c.clr.nta", M, OpX6aHint (7, 0x22, 3), {F1, MR3, IMM9b}},
+ {"ldfd.c.clr", M, OpX6aHint (7, 0x23, 0), {F1, MR3, IMM9b}},
+ {"ldfd.c.clr.nt1", M, OpX6aHint (7, 0x23, 1), {F1, MR3, IMM9b}},
+ {"ldfd.c.clr.nta", M, OpX6aHint (7, 0x23, 3), {F1, MR3, IMM9b}},
+ {"ldf8.c.clr", M, OpX6aHint (7, 0x21, 0), {F1, MR3, IMM9b}},
+ {"ldf8.c.clr.nt1", M, OpX6aHint (7, 0x21, 1), {F1, MR3, IMM9b}},
+ {"ldf8.c.clr.nta", M, OpX6aHint (7, 0x21, 3), {F1, MR3, IMM9b}},
+ {"ldfe.c.clr", M, OpX6aHint (7, 0x20, 0), {F1, MR3, IMM9b}},
+ {"ldfe.c.clr.nt1", M, OpX6aHint (7, 0x20, 1), {F1, MR3, IMM9b}},
+ {"ldfe.c.clr.nta", M, OpX6aHint (7, 0x20, 3), {F1, MR3, IMM9b}},
+ {"ldfs.c.nc", M, OpX6aHint (7, 0x26, 0), {F1, MR3, IMM9b}},
+ {"ldfs.c.nc.nt1", M, OpX6aHint (7, 0x26, 1), {F1, MR3, IMM9b}},
+ {"ldfs.c.nc.nta", M, OpX6aHint (7, 0x26, 3), {F1, MR3, IMM9b}},
+ {"ldfd.c.nc", M, OpX6aHint (7, 0x27, 0), {F1, MR3, IMM9b}},
+ {"ldfd.c.nc.nt1", M, OpX6aHint (7, 0x27, 1), {F1, MR3, IMM9b}},
+ {"ldfd.c.nc.nta", M, OpX6aHint (7, 0x27, 3), {F1, MR3, IMM9b}},
+ {"ldf8.c.nc", M, OpX6aHint (7, 0x25, 0), {F1, MR3, IMM9b}},
+ {"ldf8.c.nc.nt1", M, OpX6aHint (7, 0x25, 1), {F1, MR3, IMM9b}},
+ {"ldf8.c.nc.nta", M, OpX6aHint (7, 0x25, 3), {F1, MR3, IMM9b}},
+ {"ldfe.c.nc", M, OpX6aHint (7, 0x24, 0), {F1, MR3, IMM9b}},
+ {"ldfe.c.nc.nt1", M, OpX6aHint (7, 0x24, 1), {F1, MR3, IMM9b}},
+ {"ldfe.c.nc.nta", M, OpX6aHint (7, 0x24, 3), {F1, MR3, IMM9b}},
+
+ /* floating-point store w/increment by immediate */
+ {"stfs", M, OpX6aHint (7, 0x32, 0), {MR3, F2, IMM9a}},
+ {"stfs.nta", M, OpX6aHint (7, 0x32, 3), {MR3, F2, IMM9a}},
+ {"stfd", M, OpX6aHint (7, 0x33, 0), {MR3, F2, IMM9a}},
+ {"stfd.nta", M, OpX6aHint (7, 0x33, 3), {MR3, F2, IMM9a}},
+ {"stf8", M, OpX6aHint (7, 0x31, 0), {MR3, F2, IMM9a}},
+ {"stf8.nta", M, OpX6aHint (7, 0x31, 3), {MR3, F2, IMM9a}},
+ {"stfe", M, OpX6aHint (7, 0x30, 0), {MR3, F2, IMM9a}},
+ {"stfe.nta", M, OpX6aHint (7, 0x30, 3), {MR3, F2, IMM9a}},
+ {"stf.spill", M, OpX6aHint (7, 0x3b, 0), {MR3, F2, IMM9a}},
+ {"stf.spill.nta", M, OpX6aHint (7, 0x3b, 3), {MR3, F2, IMM9a}},
+
+ /* line prefetch w/increment by immediate */
+ {"lfetch", M0, OpX6aHint (7, 0x2c, 0), {MR3, IMM9b}},
+ {"lfetch.nt1", M0, OpX6aHint (7, 0x2c, 1), {MR3, IMM9b}},
+ {"lfetch.nt2", M0, OpX6aHint (7, 0x2c, 2), {MR3, IMM9b}},
+ {"lfetch.nta", M0, OpX6aHint (7, 0x2c, 3), {MR3, IMM9b}},
+ {"lfetch.excl", M0, OpX6aHint (7, 0x2d, 0), {MR3, IMM9b}},
+ {"lfetch.excl.nt1", M0, OpX6aHint (7, 0x2d, 1), {MR3, IMM9b}},
+ {"lfetch.excl.nt2", M0, OpX6aHint (7, 0x2d, 2), {MR3, IMM9b}},
+ {"lfetch.excl.nta", M0, OpX6aHint (7, 0x2d, 3), {MR3, IMM9b}},
+ {"lfetch.fault", M0, OpX6aHint (7, 0x2e, 0), {MR3, IMM9b}},
+ {"lfetch.fault.nt1", M0, OpX6aHint (7, 0x2e, 1), {MR3, IMM9b}},
+ {"lfetch.fault.nt2", M0, OpX6aHint (7, 0x2e, 2), {MR3, IMM9b}},
+ {"lfetch.fault.nta", M0, OpX6aHint (7, 0x2e, 3), {MR3, IMM9b}},
+ {"lfetch.fault.excl", M0, OpX6aHint (7, 0x2f, 0), {MR3, IMM9b}},
+ {"lfetch.fault.excl.nt1", M0, OpX6aHint (7, 0x2f, 1), {MR3, IMM9b}},
+ {"lfetch.fault.excl.nt2", M0, OpX6aHint (7, 0x2f, 2), {MR3, IMM9b}},
+ {"lfetch.fault.excl.nta", M0, OpX6aHint (7, 0x2f, 3), {MR3, IMM9b}},
+
+ {0}
+ };
+
+#undef M0
+#undef M
+#undef M2
+#undef bM
+#undef bX
+#undef bX2
+#undef bX3
+#undef bX4
+#undef bX6a
+#undef bX6b
+#undef bHint
+#undef mM
+#undef mX
+#undef mX2
+#undef mX3
+#undef mX4
+#undef mX6a
+#undef mX6b
+#undef mHint
+#undef OpX3
+#undef OpX3X6b
+#undef OpX3X4
+#undef OpX3X4X2
+#undef OpX6aHint
+#undef OpXX6aHint
+#undef OpMXX6a
+#undef OpMXX6aHint
--- /dev/null
+/* ia64-opc-x.c -- IA-64 `X' opcode table.
+ Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+ Contributed by Timothy Wall <twall@cygnus.com>
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 2, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+#include "ia64-opc.h"
+
+/* identify the specific X-unit type */
+#define X0 IA64_TYPE_X, 0
+#define X IA64_TYPE_X, 1
+
+/* instruction bit fields: */
+#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6)
+#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35)
+#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12)
+#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0)
+#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20)
+#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33)
+#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33)
+#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
+
+#define mBtype bBtype (-1)
+#define mD bD (-1)
+#define mPa bPa (-1)
+#define mPr bPr (-1)
+#define mVc bVc (-1)
+#define mWha bWha (-1)
+#define mX3 bX3 (-1)
+#define mX6 bX6 (-1)
+
+#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \
+ (mOp | mX3 | mX6)
+#define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc)
+#define OpPaWhaD(a,b,c,d) \
+ (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD)
+#define OpBtypePaWhaD(a,b,c,d,e) \
+ (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \
+ (mOp | mBtype | mPa | mWha | mD)
+#define OpBtypePaWhaDPr(a,b,c,d,e,f) \
+ (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \
+ (mOp | mBtype | mPa | mWha | mD | mPr)
+
+struct ia64_opcode ia64_opcodes_x[] =
+ {
+ {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}},
+ {"nop.x", X0, OpX3X6 (0, 0, 0x01), {IMMU62}},
+ {"movl", X, OpVc (6, 0), {R1, IMMU64}},
+#define BRL(a,b) \
+ X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, 0
+ {"brl.few", BRL (0, 0) | PSEUDO},
+ {"brl", BRL (0, 0) | PSEUDO},
+ {"brl.few.clr", BRL (0, 1) | PSEUDO},
+ {"brl.clr", BRL (0, 1) | PSEUDO},
+ {"brl.many", BRL (1, 0) | PSEUDO},
+ {"brl.many.clr", BRL (1, 1) | PSEUDO},
+#undef BRL
+#define BRL(a,b,c) \
+ X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0
+ {"brl.cond.sptk.few", BRL (0, 0, 0)},
+ {"brl.cond.sptk", BRL (0, 0, 0) | PSEUDO},
+ {"brl.cond.sptk.few.clr", BRL (0, 0, 1)},
+ {"brl.cond.sptk.clr", BRL (0, 0, 1) | PSEUDO},
+ {"brl.cond.spnt.few", BRL (0, 1, 0)},
+ {"brl.cond.spnt", BRL (0, 1, 0) | PSEUDO},
+ {"brl.cond.spnt.few.clr", BRL (0, 1, 1)},
+ {"brl.cond.spnt.clr", BRL (0, 1, 1) | PSEUDO},
+ {"brl.cond.dptk.few", BRL (0, 2, 0)},
+ {"brl.cond.dptk", BRL (0, 2, 0) | PSEUDO},
+ {"brl.cond.dptk.few.clr", BRL (0, 2, 1)},
+ {"brl.cond.dptk.clr", BRL (0, 2, 1) | PSEUDO},
+ {"brl.cond.dpnt.few", BRL (0, 3, 0)},
+ {"brl.cond.dpnt", BRL (0, 3, 0) | PSEUDO},
+ {"brl.cond.dpnt.few.clr", BRL (0, 3, 1)},
+ {"brl.cond.dpnt.clr", BRL (0, 3, 1) | PSEUDO},
+ {"brl.cond.sptk.many", BRL (1, 0, 0)},
+ {"brl.cond.sptk.many.clr", BRL (1, 0, 1)},
+ {"brl.cond.spnt.many", BRL (1, 1, 0)},
+ {"brl.cond.spnt.many.clr", BRL (1, 1, 1)},
+ {"brl.cond.dptk.many", BRL (1, 2, 0)},
+ {"brl.cond.dptk.many.clr", BRL (1, 2, 1)},
+ {"brl.cond.dpnt.many", BRL (1, 3, 0)},
+ {"brl.cond.dpnt.many.clr", BRL (1, 3, 1)},
+ {"brl.sptk.few", BRL (0, 0, 0)},
+ {"brl.sptk", BRL (0, 0, 0) | PSEUDO},
+ {"brl.sptk.few.clr", BRL (0, 0, 1)},
+ {"brl.sptk.clr", BRL (0, 0, 1) | PSEUDO},
+ {"brl.spnt.few", BRL (0, 1, 0)},
+ {"brl.spnt", BRL (0, 1, 0) | PSEUDO},
+ {"brl.spnt.few.clr", BRL (0, 1, 1)},
+ {"brl.spnt.clr", BRL (0, 1, 1) | PSEUDO},
+ {"brl.dptk.few", BRL (0, 2, 0)},
+ {"brl.dptk", BRL (0, 2, 0) | PSEUDO},
+ {"brl.dptk.few.clr", BRL (0, 2, 1)},
+ {"brl.dptk.clr", BRL (0, 2, 1) | PSEUDO},
+ {"brl.dpnt.few", BRL (0, 3, 0)},
+ {"brl.dpnt", BRL (0, 3, 0) | PSEUDO},
+ {"brl.dpnt.few.clr", BRL (0, 3, 1)},
+ {"brl.dpnt.clr", BRL (0, 3, 1) | PSEUDO},
+ {"brl.sptk.many", BRL (1, 0, 0)},
+ {"brl.sptk.many.clr", BRL (1, 0, 1)},
+ {"brl.spnt.many", BRL (1, 1, 0)},
+ {"brl.spnt.many.clr", BRL (1, 1, 1)},
+ {"brl.dptk.many", BRL (1, 2, 0)},
+ {"brl.dptk.many.clr", BRL (1, 2, 1)},
+ {"brl.dpnt.many", BRL (1, 3, 0)},
+ {"brl.dpnt.many.clr", BRL (1, 3, 1)},
+#undef BRL
+#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0
+ {"brl.call.sptk.few", BRL (0, 0, 0)},
+ {"brl.call.sptk", BRL (0, 0, 0) | PSEUDO},
+ {"brl.call.sptk.few.clr", BRL (0, 0, 1)},
+ {"brl.call.sptk.clr", BRL (0, 0, 1) | PSEUDO},
+ {"brl.call.spnt.few", BRL (0, 1, 0)},
+ {"brl.call.spnt", BRL (0, 1, 0) | PSEUDO},
+ {"brl.call.spnt.few.clr", BRL (0, 1, 1)},
+ {"brl.call.spnt.clr", BRL (0, 1, 1) | PSEUDO},
+ {"brl.call.dptk.few", BRL (0, 2, 0)},
+ {"brl.call.dptk", BRL (0, 2, 0) | PSEUDO},
+ {"brl.call.dptk.few.clr", BRL (0, 2, 1)},
+ {"brl.call.dptk.clr", BRL (0, 2, 1) | PSEUDO},
+ {"brl.call.dpnt.few", BRL (0, 3, 0)},
+ {"brl.call.dpnt", BRL (0, 3, 0) | PSEUDO},
+ {"brl.call.dpnt.few.clr", BRL (0, 3, 1)},
+ {"brl.call.dpnt.clr", BRL (0, 3, 1) | PSEUDO},
+ {"brl.call.sptk.many", BRL (1, 0, 0)},
+ {"brl.call.sptk.many.clr", BRL (1, 0, 1)},
+ {"brl.call.spnt.many", BRL (1, 1, 0)},
+ {"brl.call.spnt.many.clr", BRL (1, 1, 1)},
+ {"brl.call.dptk.many", BRL (1, 2, 0)},
+ {"brl.call.dptk.many.clr", BRL (1, 2, 1)},
+ {"brl.call.dpnt.many", BRL (1, 3, 0)},
+ {"brl.call.dpnt.many.clr", BRL (1, 3, 1)},
+#undef BRL
+ {0}
+ };
+
+#undef X0
+#undef X
+
+#undef bBtype
+#undef bD
+#undef bPa
+#undef bPr
+#undef bVc
+#undef bWha
+#undef bX3
+#undef bX6
+
+#undef mBtype
+#undef mD
+#undef mPa
+#undef mPr
+#undef mVc
+#undef mWha
+#undef mX3
+#undef mX6
+
+#undef OpX3X6
+#undef OpVc
+#undef OpPaWhaD
+#undef OpBtypePaWhaD
+#undef OpBtypePaWhaDPr
--- /dev/null
+/* ia64-opc.c -- Functions to access the compacted opcode table
+ Copyright (C) 1999 Free Software Foundation, Inc.
+ Written by Bob Manson of Cygnus Solutions, <manson@cygnus.com>
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 2, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+#include "ansidecl.h"
+#include "libiberty.h"
+#include "sysdep.h"
+#include "ia64-asmtab.h"
+#include "ia64-asmtab.c"
+
+const struct ia64_templ_desc ia64_templ_desc[16] =
+ {
+ { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */
+ { 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" },
+ { 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" },
+ { 0, { 0, }, "-3-" },
+ { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, /* 4 */
+ { 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" },
+ { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" },
+ { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" },
+ { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" }, /* 8 */
+ { 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" },
+ { 0, { 0, }, "-a-" },
+ { 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" },
+ { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" }, /* c */
+ { 0, { 0, }, "-d-" },
+ { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" },
+ { 0, { 0, }, "-f-" },
+ };
+
+
+/* Copy the prefix contained in *PTR (up to a '.' or a NUL) to DEST.
+ PTR will be adjusted to point to the start of the next portion
+ of the opcode, or at the NUL character. */
+
+static void
+get_opc_prefix (ptr, dest)
+ const char **ptr;
+ char *dest;
+{
+ char *c = strchr (*ptr, '.');
+ if (c != NULL)
+ {
+ memcpy (dest, *ptr, c - *ptr);
+ dest[c - *ptr] = '\0';
+ *ptr = c + 1;
+ }
+ else
+ {
+ int l = strlen (*ptr);
+ memcpy (dest, *ptr, l);
+ dest[l] = '\0';
+ *ptr += l;
+ }
+}
+\f
+/* Find the index of the entry in the string table corresponding to
+ STR; return -1 if one does not exist. */
+
+static short
+find_string_ent (str)
+ const char *str;
+{
+ short start = 0;
+ short end = sizeof (ia64_strings) / sizeof (const char *);
+ short i = (start + end) / 2;
+
+ if (strcmp (str, ia64_strings[end - 1]) > 0)
+ {
+ return -1;
+ }
+ while (start <= end)
+ {
+ int c = strcmp (str, ia64_strings[i]);
+ if (c < 0)
+ {
+ end = i - 1;
+ }
+ else if (c == 0)
+ {
+ return i;
+ }
+ else
+ {
+ start = i + 1;
+ }
+ i = (start + end) / 2;
+ }
+ return -1;
+}
+\f
+/* Find the opcode in the main opcode table whose name is STRINGINDEX, or
+ return -1 if one does not exist. */
+
+static short
+find_main_ent (nameindex)
+ short nameindex;
+{
+ short start = 0;
+ short end = sizeof (main_table) / sizeof (struct ia64_main_table);
+ short i = (start + end) / 2;
+
+ if (nameindex < main_table[0].name_index
+ || nameindex > main_table[end - 1].name_index)
+ {
+ return -1;
+ }
+ while (start <= end)
+ {
+ if (nameindex < main_table[i].name_index)
+ {
+ end = i - 1;
+ }
+ else if (nameindex == main_table[i].name_index)
+ {
+ while (i > 0 && main_table[i - 1].name_index == nameindex)
+ {
+ i--;
+ }
+ return i;
+ }
+ else
+ {
+ start = i + 1;
+ }
+ i = (start + end) / 2;
+ }
+ return -1;
+}
+\f
+/* Find the index of the entry in the completer table that is part of
+ MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or
+ return -1 if one does not exist. */
+
+static short
+find_completer (main_ent, prev_completer, name)
+ short main_ent;
+ short prev_completer;
+ const char *name;
+{
+ short name_index = find_string_ent (name);
+
+ if (name_index < 0)
+ {
+ return -1;
+ }
+
+ if (prev_completer == -1)
+ {
+ prev_completer = main_table[main_ent].completers;
+ }
+ else
+ {
+ prev_completer = completer_table[prev_completer].subentries;
+ }
+
+ while (prev_completer != -1)
+ {
+ if (completer_table[prev_completer].name_index == name_index)
+ {
+ return prev_completer;
+ }
+ prev_completer = completer_table[prev_completer].alternative;
+ }
+ return -1;
+}
+\f
+/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and
+ return the result. */
+
+static ia64_insn
+apply_completer (opcode, completer_index)
+ ia64_insn opcode;
+ int completer_index;
+{
+ ia64_insn mask = completer_table[completer_index].mask;
+ ia64_insn bits = completer_table[completer_index].bits;
+ int shiftamt = (completer_table[completer_index].offset & 63);
+
+ mask = mask << shiftamt;
+ bits = bits << shiftamt;
+ opcode = (opcode & ~mask) | bits;
+ return opcode;
+}
+\f
+/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in
+ the dis_table array, and return its value. (BITOFFSET is numbered
+ starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the
+ first byte in OP_POINTER.) */
+
+static int
+extract_op_bits (op_pointer, bitoffset, bits)
+ int op_pointer;
+ int bitoffset;
+ int bits;
+{
+ int res = 0;
+
+ op_pointer += (bitoffset / 8);
+
+ if (bitoffset % 8)
+ {
+ unsigned int op = dis_table[op_pointer++];
+ int numb = 8 - (bitoffset % 8);
+ int mask = (1 << numb) - 1;
+ int bata = (bits < numb) ? bits : numb;
+ int delta = numb - bata;
+
+ res = (res << bata) | ((op & mask) >> delta);
+ bitoffset += bata;
+ bits -= bata;
+ }
+ while (bits >= 8)
+ {
+ res = (res << 8) | (dis_table[op_pointer++] & 255);
+ bits -= 8;
+ }
+ if (bits > 0)
+ {
+ unsigned int op = (dis_table[op_pointer++] & 255);
+ res = (res << bits) | (op >> (8 - bits));
+ }
+ return res;
+}
+\f
+/* Examine the state machine entry at OP_POINTER in the dis_table
+ array, and extract its values into OPVAL and OP. The length of the
+ state entry in bits is returned. */
+
+static int
+extract_op (op_pointer, opval, op)
+ int op_pointer;
+ int *opval;
+ unsigned int *op;
+{
+ int oplen = 5;
+
+ *op = dis_table[op_pointer];
+
+ if ((*op) & 0x40)
+ {
+ opval[0] = extract_op_bits (op_pointer, oplen, 5);
+ oplen += 5;
+ }
+ switch ((*op) & 0x30)
+ {
+ case 0x10:
+ {
+ opval[1] = extract_op_bits (op_pointer, oplen, 8);
+ oplen += 8;
+ opval[1] += op_pointer;
+ break;
+ }
+ case 0x20:
+ {
+ opval[1] = extract_op_bits (op_pointer, oplen, 16);
+ if (! (opval[1] & 32768))
+ {
+ opval[1] += op_pointer;
+ }
+ oplen += 16;
+ break;
+ }
+ case 0x30:
+ {
+ oplen--;
+ opval[2] = extract_op_bits (op_pointer, oplen, 12);
+ oplen += 12;
+ opval[2] |= 32768;
+ break;
+ }
+ }
+ if (((*op) & 0x08) && (((*op) & 0x30) != 0x30))
+ {
+ opval[2] = extract_op_bits (op_pointer, oplen, 16);
+ oplen += 16;
+ if (! (opval[2] & 32768))
+ {
+ opval[2] += op_pointer;
+ }
+ }
+ return oplen;
+}
+\f
+/* Returns a non-zero value if the opcode in the main_table list at
+ PLACE matches OPCODE and is of type TYPE. */
+
+static int
+opcode_verify (opcode, place, type)
+ ia64_insn opcode;
+ int place;
+ enum ia64_insn_type type;
+{
+ if (main_table[place].opcode_type != type)
+ {
+ return 0;
+ }
+ if (main_table[place].flags
+ & (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT))
+ {
+ const struct ia64_operand *o1, *o2;
+ ia64_insn f2, f3;
+
+ if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3)
+ {
+ o1 = elf64_ia64_operands + IA64_OPND_F2;
+ o2 = elf64_ia64_operands + IA64_OPND_F3;
+ (*o1->extract) (o1, opcode, &f2);
+ (*o2->extract) (o2, opcode, &f3);
+ if (f2 != f3)
+ return 0;
+ }
+ else
+ {
+ ia64_insn len, count;
+
+ /* length must equal 64-count: */
+ o1 = elf64_ia64_operands + IA64_OPND_LEN6;
+ o2 = elf64_ia64_operands + main_table[place].operands[2];
+ (*o1->extract) (o1, opcode, &len);
+ (*o2->extract) (o2, opcode, &count);
+ if (len != 64 - count)
+ return 0;
+ }
+ }
+ return 1;
+}
+\f
+/* Find an instruction entry in the ia64_dis_names array that matches
+ opcode OPCODE and is of type TYPE. Returns either a positive index
+ into the array, or a negative value if an entry for OPCODE could
+ not be found. */
+
+static int
+locate_opcode_ent (opcode, type)
+ ia64_insn opcode;
+ enum ia64_insn_type type;
+{
+ int currtest[41];
+ int bitpos[41];
+ int op_ptr[41];
+ int currstatenum = 0;
+
+ currtest[currstatenum] = 0;
+ op_ptr[currstatenum] = 0;
+ bitpos[currstatenum] = 40;
+
+ while (1)
+ {
+ int op_pointer = op_ptr[currstatenum];
+ unsigned int op;
+ int currbitnum = bitpos[currstatenum];
+ int oplen;
+ int opval[3];
+ int next_op;
+ int currbit;
+
+ oplen = extract_op (op_pointer, opval, &op);
+
+ bitpos[currstatenum] = currbitnum;
+
+ /* Skip opval[0] bits in the instruction. */
+ if (op & 0x40)
+ {
+ currbitnum -= opval[0];
+ }
+
+ /* The value of the current bit being tested. */
+ currbit = opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0;
+ next_op = -1;
+
+ /* We always perform the tests specified in the current state in
+ a particular order, falling through to the next test if the
+ previous one failed. */
+ switch (currtest[currstatenum])
+ {
+ case 0:
+ currtest[currstatenum]++;
+ if (currbit == 0 && (op & 0x80))
+ {
+ /* Check for a zero bit. If this test solely checks for
+ a zero bit, we can check for up to 8 consecutive zero
+ bits (the number to check is specified by the lower 3
+ bits in the state code.)
+
+ If the state instruction matches, we go to the very
+ next state instruction; otherwise, try the next test. */
+
+ if ((op & 0xf8) == 0x80)
+ {
+ int count = op & 0x7;
+ int x;
+
+ for (x = 0; x <= count; x++)
+ {
+ int i =
+ opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0;
+ if (i)
+ {
+ break;
+ }
+ }
+ if (x > count)
+ {
+ next_op = op_pointer + ((oplen + 7) / 8);
+ currbitnum -= count;
+ break;
+ }
+ }
+ else if (! currbit)
+ {
+ next_op = op_pointer + ((oplen + 7) / 8);
+ break;
+ }
+ }
+ /* FALLTHROUGH */
+ case 1:
+ /* If the bit in the instruction is one, go to the state
+ instruction specified by opval[1]. */
+ currtest[currstatenum]++;
+ if (currbit && (op & 0x30) != 0 && ((op & 0x30) != 0x30))
+ {
+ next_op = opval[1];
+ break;
+ }
+ /* FALLTHROUGH */
+ case 2:
+ /* Don't care. Skip the current bit and go to the state
+ instruction specified by opval[2].
+
+ An encoding of 0x30 is special; this means that a 12-bit
+ offset into the ia64_dis_names[] array is specified. */
+ currtest[currstatenum]++;
+ if ((op & 0x08) || ((op & 0x30) == 0x30))
+ {
+ next_op = opval[2];
+ break;
+ }
+ }
+
+ /* If bit 15 is set in the address of the next state, an offset
+ in the ia64_dis_names array was specified instead. We then
+ check to see if an entry in the list of opcodes matches the
+ opcode we were given; if so, we have succeeded. */
+
+ if ((next_op >= 0) && (next_op & 32768))
+ {
+ short disent = next_op & 32767;
+
+ if (next_op > 65535)
+ {
+ abort ();
+ }
+
+ /* Run through the list of opcodes to check, trying to find
+ one that matches. */
+ while (disent >= 0)
+ {
+ int place = ia64_dis_names[disent].insn_index;
+
+ if (opcode_verify (opcode, place, type))
+ {
+ break;
+ }
+ if (ia64_dis_names[disent].next_flag)
+ {
+ disent++;
+ }
+ else
+ {
+ disent = -1;
+ }
+ }
+
+ if (disent >= 0)
+ {
+ return disent;
+ }
+ else
+ {
+ /* Failed to match; try the next test in this state. */
+ next_op = -2;
+ }
+ }
+
+ /* next_op == -1 is "back up to the previous state".
+ next_op == -2 is "stay in this state and try the next test".
+ Otherwise, transition to the state indicated by next_op. */
+
+ if (next_op == -1)
+ {
+ currstatenum--;
+ if (currstatenum < 0)
+ {
+ return -1;
+ }
+ }
+ else if (next_op >= 0)
+ {
+ currstatenum++;
+ bitpos[currstatenum] = currbitnum - 1;
+ op_ptr[currstatenum] = next_op;
+ currtest[currstatenum] = 0;
+ }
+ }
+}
+\f
+/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */
+
+static struct ia64_opcode *
+make_ia64_opcode (opcode, name, place, depind)
+ ia64_insn opcode;
+ const char *name;
+ int place;
+ int depind;
+{
+ struct ia64_opcode *res =
+ (struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode));
+ res->name = xstrdup (name);
+ res->type = main_table[place].opcode_type;
+ res->num_outputs = main_table[place].num_outputs;
+ res->opcode = opcode;
+ res->mask = main_table[place].mask;
+ res->operands[0] = main_table[place].operands[0];
+ res->operands[1] = main_table[place].operands[1];
+ res->operands[2] = main_table[place].operands[2];
+ res->operands[3] = main_table[place].operands[3];
+ res->operands[4] = main_table[place].operands[4];
+ res->flags = main_table[place].flags;
+ res->ent_index = place;
+ res->dependencies = &op_dependencies[depind];
+ return res;
+}
+\f
+/* Determine the ia64_opcode entry for the opcode specified by INSN
+ and TYPE. If a valid entry is not found, return NULL. */
+struct ia64_opcode *
+ia64_dis_opcode (insn, type)
+ ia64_insn insn;
+ enum ia64_insn_type type;
+{
+ int disent = locate_opcode_ent (insn, type);
+
+ if (disent < 0)
+ {
+ return NULL;
+ }
+ else
+ {
+ unsigned int cb = ia64_dis_names[disent].completer_index;
+ static char name[128];
+ int place = ia64_dis_names[disent].insn_index;
+ int ci = main_table[place].completers;
+ ia64_insn tinsn = main_table[place].opcode;
+
+ strcpy (name, ia64_strings [main_table[place].name_index]);
+
+ while (cb)
+ {
+ if (cb & 1)
+ {
+ int cname = completer_table[ci].name_index;
+
+ tinsn = apply_completer (tinsn, ci);
+
+ if (ia64_strings[cname][0] != '\0')
+ {
+ strcat (name, ".");
+ strcat (name, ia64_strings[cname]);
+ }
+ if (cb != 1)
+ {
+ ci = completer_table[ci].subentries;
+ }
+ }
+ else
+ {
+ ci = completer_table[ci].alternative;
+ }
+ if (ci < 0)
+ {
+ abort ();
+ }
+ cb = cb >> 1;
+ }
+ if (tinsn != (insn & main_table[place].mask))
+ {
+ abort ();
+ }
+ return make_ia64_opcode (insn, name, place,
+ completer_table[ci].dependencies);
+ }
+}
+\f
+/* Search the main_opcode table starting from PLACE for an opcode that
+ matches NAME. Return NULL if one is not found. */
+
+static struct ia64_opcode *
+ia64_find_matching_opcode (name, place)
+ const char *name;
+ short place;
+{
+ char op[129];
+ const char *suffix;
+ short name_index;
+
+ if (strlen (name) > 128)
+ {
+ return NULL;
+ }
+ suffix = name;
+ get_opc_prefix (&suffix, op);
+ name_index = find_string_ent (op);
+ if (name_index < 0)
+ {
+ return NULL;
+ }
+
+ while (main_table[place].name_index == name_index)
+ {
+ const char *curr_suffix = suffix;
+ ia64_insn curr_insn = main_table[place].opcode;
+ short completer = -1;
+
+ do {
+ if (suffix[0] == '\0')
+ {
+ completer = find_completer (place, completer, suffix);
+ }
+ else
+ {
+ get_opc_prefix (&curr_suffix, op);
+ completer = find_completer (place, completer, op);
+ }
+ if (completer != -1)
+ {
+ curr_insn = apply_completer (curr_insn, completer);
+ }
+ } while (completer != -1 && curr_suffix[0] != '\0');
+
+ if (completer != -1 && curr_suffix[0] == '\0'
+ && completer_table[completer].terminal_completer)
+ {
+ int depind = completer_table[completer].dependencies;
+ return make_ia64_opcode (curr_insn, name, place, depind);
+ }
+ else
+ {
+ place++;
+ }
+ }
+ return NULL;
+}
+\f
+/* Find the next opcode after PREV_ENT that matches PREV_ENT, or return NULL
+ if one does not exist.
+
+ It is the caller's responsibility to invoke ia64_free_opcode () to
+ release any resources used by the returned entry. */
+
+struct ia64_opcode *
+ia64_find_next_opcode (prev_ent)
+ struct ia64_opcode *prev_ent;
+{
+ return ia64_find_matching_opcode (prev_ent->name,
+ prev_ent->ent_index + 1);
+}
+
+/* Find the first opcode that matches NAME, or return NULL if it does
+ not exist.
+
+ It is the caller's responsibility to invoke ia64_free_opcode () to
+ release any resources used by the returned entry. */
+
+struct ia64_opcode *
+ia64_find_opcode (name)
+ const char *name;
+{
+ char op[129];
+ const char *suffix;
+ short place;
+ short name_index;
+
+ if (strlen (name) > 128)
+ {
+ return NULL;
+ }
+ suffix = name;
+ get_opc_prefix (&suffix, op);
+ name_index = find_string_ent (op);
+ if (name_index < 0)
+ {
+ return NULL;
+ }
+
+ place = find_main_ent (name_index);
+
+ if (place < 0)
+ {
+ return NULL;
+ }
+ return ia64_find_matching_opcode (name, place);
+}
+
+/* Free any resources used by ENT. */
+void
+ia64_free_opcode (ent)
+ struct ia64_opcode *ent;
+{
+ free ((void *)ent->name);
+ free (ent);
+}
+
+const struct ia64_dependency *
+ia64_find_dependency (index)
+ int index;
+{
+ index = DEP(index);
+
+ if (index < 0 || index >= sizeof(dependencies) / sizeof(dependencies[0]))
+ return NULL;
+
+ return &dependencies[index];
+}
--- /dev/null
+/* ia64-opc.h -- IA-64 opcode table.
+ Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 2, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+#ifndef IA64_OPC_H
+#define IA64_OPC_H
+
+#include "opcode/ia64.h"
+
+/* define a couple of abbreviations: */
+
+#define bOp(x) (((ia64_insn) ((x) & 0xf)) << 37)
+#define mOp bOp (-1)
+#define Op(x) bOp (x), mOp
+
+#define FIRST IA64_OPCODE_FIRST
+#define X_IN_MLX IA64_OPCODE_X_IN_MLX
+#define LAST IA64_OPCODE_LAST
+#define PRIV IA64_OPCODE_PRIV
+#define NO_PRED IA64_OPCODE_NO_PRED
+#define SLOT2 IA64_OPCODE_SLOT2
+#define PSEUDO IA64_OPCODE_PSEUDO
+#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3
+#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT
+#define MOD_RRBS IA64_OPCODE_MOD_RRBS
+
+#define AR_CCV IA64_OPND_AR_CCV
+#define AR_PFS IA64_OPND_AR_PFS
+#define C1 IA64_OPND_C1
+#define C8 IA64_OPND_C8
+#define C16 IA64_OPND_C16
+#define GR0 IA64_OPND_GR0
+#define IP IA64_OPND_IP
+#define PR IA64_OPND_PR
+#define PR_ROT IA64_OPND_PR_ROT
+#define PSR IA64_OPND_PSR
+#define PSR_L IA64_OPND_PSR_L
+#define PSR_UM IA64_OPND_PSR_UM
+
+#define AR3 IA64_OPND_AR3
+#define B1 IA64_OPND_B1
+#define B2 IA64_OPND_B2
+#define CR3 IA64_OPND_CR3
+#define F1 IA64_OPND_F1
+#define F2 IA64_OPND_F2
+#define F3 IA64_OPND_F3
+#define F4 IA64_OPND_F4
+#define P1 IA64_OPND_P1
+#define P2 IA64_OPND_P2
+#define R1 IA64_OPND_R1
+#define R2 IA64_OPND_R2
+#define R3 IA64_OPND_R3
+#define R3_2 IA64_OPND_R3_2
+
+#define CPUID_R3 IA64_OPND_CPUID_R3
+#define DBR_R3 IA64_OPND_DBR_R3
+#define DTR_R3 IA64_OPND_DTR_R3
+#define ITR_R3 IA64_OPND_ITR_R3
+#define IBR_R3 IA64_OPND_IBR_R3
+#define MR3 IA64_OPND_MR3
+#define MSR_R3 IA64_OPND_MSR_R3
+#define PKR_R3 IA64_OPND_PKR_R3
+#define PMC_R3 IA64_OPND_PMC_R3
+#define PMD_R3 IA64_OPND_PMD_R3
+#define RR_R3 IA64_OPND_RR_R3
+
+#define CCNT5 IA64_OPND_CCNT5
+#define CNT2a IA64_OPND_CNT2a
+#define CNT2b IA64_OPND_CNT2b
+#define CNT2c IA64_OPND_CNT2c
+#define CNT5 IA64_OPND_CNT5
+#define CNT6 IA64_OPND_CNT6
+#define CPOS6a IA64_OPND_CPOS6a
+#define CPOS6b IA64_OPND_CPOS6b
+#define CPOS6c IA64_OPND_CPOS6c
+#define IMM1 IA64_OPND_IMM1
+#define IMM14 IA64_OPND_IMM14
+#define IMM17 IA64_OPND_IMM17
+#define IMM22 IA64_OPND_IMM22
+#define IMM44 IA64_OPND_IMM44
+#define SOF IA64_OPND_SOF
+#define SOL IA64_OPND_SOL
+#define SOR IA64_OPND_SOR
+#define IMM8 IA64_OPND_IMM8
+#define IMM8U4 IA64_OPND_IMM8U4
+#define IMM8M1 IA64_OPND_IMM8M1
+#define IMM8M1U4 IA64_OPND_IMM8M1U4
+#define IMM8M1U8 IA64_OPND_IMM8M1U8
+#define IMM9a IA64_OPND_IMM9a
+#define IMM9b IA64_OPND_IMM9b
+#define IMMU2 IA64_OPND_IMMU2
+#define IMMU21 IA64_OPND_IMMU21
+#define IMMU24 IA64_OPND_IMMU24
+#define IMMU62 IA64_OPND_IMMU62
+#define IMMU64 IA64_OPND_IMMU64
+#define IMMU7a IA64_OPND_IMMU7a
+#define IMMU7b IA64_OPND_IMMU7b
+#define IMMU9 IA64_OPND_IMMU9
+#define INC3 IA64_OPND_INC3
+#define LEN4 IA64_OPND_LEN4
+#define LEN6 IA64_OPND_LEN6
+#define MBTYPE4 IA64_OPND_MBTYPE4
+#define MHTYPE8 IA64_OPND_MHTYPE8
+#define POS6 IA64_OPND_POS6
+#define TAG13 IA64_OPND_TAG13
+#define TAG13b IA64_OPND_TAG13b
+#define TGT25 IA64_OPND_TGT25
+#define TGT25b IA64_OPND_TGT25b
+#define TGT25c IA64_OPND_TGT25c
+#define TGT64 IA64_OPND_TGT64
+
+#endif
--- /dev/null
+Resource Name; Writers; Readers; Semantics of Dependency
+ALAT; chk.a.clr, IC:mem-readers-alat, IC:mem-writers, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, IC:chk-a, invala.e; none
+AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br.ret, cover, flushrs, loadrs, IC:mov-from-AR-BSP, rfi; impliedF
+AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, IC:mov-from-AR-BSPSTORE; impliedF
+AR[CCV]; IC:mov-to-AR-CCV; br.ia, IC:cmpxchg, IC:mov-from-AR-CCV; impliedF
+AR[EC]; IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC; br.call, brl.call, br.ia, IC:mod-sched-brs, IC:mov-from-AR-EC; impliedF
+AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; br.ia, IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0, fsetc, IC:mov-from-AR-FPSR; impliedF
+AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; br.ia, IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-from-AR-FPSR; impliedF
+AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; br.ia, IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-from-AR-FPSR; impliedF
+AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; br.ia, IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-from-AR-FPSR; impliedF
+AR[FPSR].sf0.flags; IC:fp-arith-s0, fclrf.s0, IC:fcmp-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; br.ia, fchkf, IC:mov-from-AR-FPSR; impliedF
+AR[FPSR].sf1.flags; IC:fp-arith-s1, fclrf.s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; br.ia, fchkf.s1, IC:mov-from-AR-FPSR; impliedF
+AR[FPSR].sf2.flags; IC:fp-arith-s2, fclrf.s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; br.ia, fchkf.s2, IC:mov-from-AR-FPSR; impliedF
+AR[FPSR].sf3.flags; IC:fp-arith-s3, fclrf.s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; br.ia, fchkf.s3, IC:mov-from-AR-FPSR; impliedF
+AR[FPSR].traps; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF
+AR[FPSR].rv; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF
+AR[ITC]; IC:mov-to-AR-ITC; br.ia, IC:mov-from-AR-ITC; impliedF
+AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; br.ia, IC:mov-from-AR-K+1; impliedF
+AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; br.ia, IC:mod-sched-brs-counted, IC:mov-from-AR-LC; impliedF
+AR[PFS]; br.call, brl.call; alloc, br.ia, br.ret, epc, IC:mov-from-AR-PFS; impliedF
+AR[PFS]; IC:mov-to-AR-PFS; alloc, br.ia, epc, IC:mov-from-AR-PFS; impliedF
+AR[PFS]; IC:mov-to-AR-PFS; br.ret; none
+AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RNAT; impliedF
+AR[RSC]; IC:mov-to-AR-RSC; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RSC, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-RNAT, IC:mov-from-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF
+AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; br.ia, ld8.fill, IC:mov-from-AR-UNAT; impliedF
+AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; br.ia, IC:mov-from-AR-rv+1; none
+AR%, % in 48-63, 112-127; IC:mov-to-AR-ig+1; br.ia, IC:mov-from-AR-ig+1; impliedF
+BR%, % in 0 - 7; br.call+1, brl.call+1; IC:indirect-brs+1, IC:indirect-brp+1, IC:mov-from-BR+1; impliedF
+BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brs+1; none
+BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brp+1, IC:mov-from-BR+1; impliedF
+CFM; IC:mod-sched-brs; IC:mod-sched-brs; impliedF
+CFM; IC:mod-sched-brs; cover, alloc, rfi, loadrs, br.ret, br.call, brl.call; impliedF
+CFM; IC:mod-sched-brs; IC:cfm-readers+2; impliedF
+CFM; br.call, brl.call, br.ret, clrrrb, cover, rfi; IC:cfm-readers; impliedF
+CFM; alloc; IC:cfm-readers; none
+CPUID#; IC:none; IC:mov-from-IND-CPUID+3; specific
+CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-from-CR-CMCV; data
+CR[DCR]; IC:mov-to-CR-DCR; IC:mov-from-CR-DCR, IC:mem-readers-spec; data
+CR[EOI]; IC:mov-to-CR-EOI; IC:none; SC Section 10.8.3.4
+CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-from-CR-GPTA, thash; data
+CR[IFA]; IC:mov-to-CR-IFA; itc.i, itc.d, itr.i, itr.d; implied
+CR[IFA]; IC:mov-to-CR-IFA; IC:mov-from-CR-IFA; data
+CR[IFS]; IC:mov-to-CR-IFS; IC:mov-from-CR-IFS; data
+CR[IFS]; IC:mov-to-CR-IFS; rfi; implied
+CR[IFS]; cover; rfi, IC:mov-from-CR-IFS; implied
+CR[IHA]; IC:mov-to-CR-IHA; IC:mov-from-CR-IHA; data
+CR[IIM]; IC:mov-to-CR-IIM; IC:mov-from-CR-IIM; data
+CR[IIP]; IC:mov-to-CR-IIP; IC:mov-from-CR-IIP; data
+CR[IIP]; IC:mov-to-CR-IIP; rfi; implied
+CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-from-CR-IIPA; data
+CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-from-CR-IPSR; data
+CR[IPSR]; IC:mov-to-CR-IPSR; rfi; implied
+CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IRR+1; data
+CR[ISR]; IC:mov-to-CR-ISR; IC:mov-from-CR-ISR; data
+CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-from-CR-ITIR; data
+CR[ITIR]; IC:mov-to-CR-ITIR; itc.i, itc.d, itr.i, itc.d; implied
+CR[ITM]; IC:mov-to-CR-ITM; IC:mov-from-CR-ITM; data
+CR[ITV]; IC:mov-to-CR-ITV; IC:mov-from-CR-ITV; data
+CR[IVA]; IC:mov-to-CR-IVA; IC:mov-from-CR-IVA; instr
+CR[IVR]; IC:none; IC:mov-from-CR-IVR; SC Section 10.8.3.2
+CR[LID]; IC:mov-to-CR-LID; IC:mov-from-CR-LID; SC Section 10.8.3.1
+CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-from-CR-LRR+1; data
+CR[PMV]; IC:mov-to-CR-PMV; IC:mov-from-CR-PMV; data
+CR[PTA]; IC:mov-to-CR-PTA; IC:mov-from-CR-PTA, thash; data
+CR[TPR]; IC:mov-to-CR-TPR; IC:mov-from-CR-TPR, IC:mov-from-CR-IVR; data
+CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-PSR-l, rfi, rsm, ssm; SC Section 10.8.3.3
+CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:mov-from-CR-rv+1; none
+DBR#; IC:mov-to-IND-DBR+3; IC:mov-from-IND-DBR+3; impliedF
+DBR#; IC:mov-to-IND-DBR+3; IC:probe-all, IC:lfetch-all, IC:mem-readers, IC:mem-writers; data
+DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data
+DTC; itc.i, itc.d, itr.i, itr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; impliedF
+DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none
+DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF
+DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF
+DTR; itr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data
+DTR; itr.d; ptc.g, ptc.ga, ptc.l, ptr.d, itr.d; impliedF
+DTR; ptr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data
+DTR; ptr.d; ptc.g, ptc.ga, ptc.l, ptr.d; none
+DTR; ptr.d; itr.d, itc.d; impliedF
+FR%, % in 0 - 1; IC:none; IC:fr-readers+1; none
+FR%, % in 2 - 127; IC:fr-writers+1\IC:ldf-c+1\IC:ldfp-c+1; IC:fr-readers+1; impliedF
+FR%, % in 2 - 127; IC:ldf-c+1, IC:ldfp-c+1; IC:fr-readers+1; none
+GR0; IC:none; IC:gr-readers+1, IC:mov-immediate; none
+GR%, % in 1 - 127; IC:ld-c+1+13; IC:gr-readers+1; none
+GR%, % in 1 - 127; IC:gr-writers+1\IC:ld-c+1+13; IC:gr-readers+1; impliedF
+IBR#; IC:mov-to-IND-IBR+3; IC:mov-from-IND-IBR+3; impliedF
+InService*; IC:mov-to-CR-EOI; IC:mov-from-CR-IVR; data
+InService*; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF
+InService*; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; impliedF
+IP; IC:all; IC:all; none
+ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; epc; instr
+ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF
+ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptr.i, ptr.d, ptc.e, ptc.g, ptc.ga, ptc.l; none
+ITC; itc.i, itc.d, itr.i, itr.d; epc; instr
+ITC; itc.i, itc.d, itr.i, itr.d; itc.d, itc.i, itr.d, itr.i, ptr.d, ptr.i, ptc.g, ptc.ga, ptc.l; impliedF
+ITC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF
+ITR; itr.i; itr.i, itc.i, ptc.g, ptc.ga, ptc.l, ptr.i; impliedF
+ITR; itr.i; epc; instr
+ITR; ptr.i; itc.i, itr.i; impliedF
+ITR; ptr.i; ptc.g, ptc.ga, ptc.l, ptr.i; none
+ITR; ptr.i; epc; instr
+memory; IC:mem-writers; IC:mem-readers; none
+MSR#; IC:mov-to-IND-MSR+5; IC:mov-from-IND-MSR+5; specific
+PKR#; IC:mov-to-IND-PKR+3; IC:mem-readers, IC:mem-writers, IC:mov-from-IND-PKR+4, IC:probe-all; data
+PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none
+PKR#; IC:mov-to-IND-PKR+3; IC:mov-from-IND-PKR+3; impliedF
+PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF
+PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMC+3; impliedF
+PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMD+3; SC+3 Section 12.1.1
+PMD#; IC:mov-to-IND-PMD+3; IC:mov-from-IND-PMD+3; impliedF
+PR0; IC:pr-writers+1; IC:pr-readers-br+1, IC:pr-readers-nobr-nomovpr+1 , IC:mov-from-PR+12, IC:mov-to-PR+12; none
+PR%, % in 1 - 62; IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1 , IC:mov-from-PR, IC:mov-to-PR+12; impliedF
+PR%, % in 1 - 62; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF
+PR%, % in 1 - 62; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none
+PR63; IC:mod-sched-brs, IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1 , IC:mov-from-PR, IC:mov-to-PR+12; impliedF
+PR63; IC:pr-writers-fp+1, IC:mod-sched-brs; IC:pr-readers-br+1; impliedF
+PR63; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none
+PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied
+PSR.ac; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data
+PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF
+PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied
+PSR.be; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data
+PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF
+PSR.bn; bsw, rfi; IC:gr-readers+10, IC:gr-writers+10; impliedF
+PSR.cpl; epc, br.ret, rfi; IC:priv-ops, br.call, brl.call, epc, IC:mov-from-AR-ITC, IC:mov-to-AR-ITC, IC:mov-to-AR-RSC, IC:mov-to-AR-K, IC:mov-from-IND-PMD, IC:probe-all, IC:mem-readers, IC:mem-writers, IC:lfetch-all; implied
+PSR.da; rfi; IC:mem-readers, IC:lfetch-fault, IC:mem-writers, IC:probe-fault; data
+PSR.db; IC:mov-to-PSR-l; IC:mem-readers, IC:mem-writers, IC:probe-fault; data
+PSR.db; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF
+PSR.db; rfi; IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:probe-fault; data
+PSR.dd; rfi; IC:mem-readers, IC:probe-fault, IC:mem-writers, IC:lfetch-fault; data
+PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:fr-readers+8, IC:fr-writers+8; data
+PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
+PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:fr-writers+8, IC:fr-readers+8; data
+PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
+PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; br.ia; data
+PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
+PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data
+PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
+PSR.ed; rfi; IC:lfetch-all, IC:mem-readers-spec; data
+PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF
+PSR.i; rfi; IC:mov-from-PSR; data
+PSR.ia; rfi; IC:none; none
+PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
+PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; cover, itc.i, itc.d, itr.i, itr.d, IC:mov-from-CR-ITIR, IC:mov-from-CR-IFS, IC:mov-from-CR-IIM, IC:mov-from-CR-IIP, IC:mov-from-CR-IPSR, IC:mov-from-CR-ISR, IC:mov-from-CR-IFA, IC:mov-from-CR-IHA, IC:mov-from-CR-IIPA, IC:mov-to-CR-ITIR, IC:mov-to-CR-IFS, IC:mov-to-CR-IIM, IC:mov-to-CR-IIP, IC:mov-to-CR-IPSR, IC:mov-to-CR-ISR, IC:mov-to-CR-IFA, IC:mov-to-CR-IHA, IC:mov-to-CR-IIPA; data
+PSR.id; rfi; IC:none; none
+PSR.is; br.ia, rfi; IC:none; none
+PSR.it; rfi; IC:branches, IC:mov-from-PSR, chk, epc, fchkf; data
+PSR.lp; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF
+PSR.lp; IC:mov-to-PSR-l; br.ret; data
+PSR.lp; rfi; IC:mov-from-PSR, br.ret; data
+PSR.mc; rfi; IC:mov-from-PSR; none
+PSR.mfh; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF
+PSR.mfl; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF
+PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers, IC:probe-all; data
+PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
+PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
+PSR.ri; rfi; IC:none; none
+PSR.rt; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF
+PSR.rt; IC:mov-to-PSR-l; alloc, flushrs, loadrs; data
+PSR.rt; rfi; IC:mov-from-PSR, alloc, flushrs, loadrs; data
+PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
+PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-AR-ITC; data
+PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
+PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-IND-PMD, IC:mov-to-PSR-um, rum, sum; data
+PSR.ss; rfi; IC:all; data
+PSR.tb; IC:mov-to-PSR-l, rfi; IC:branches, chk, fchkf; data
+PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
+PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF
+RR#; IC:mov-to-IND-RR+6; IC:mem-readers, IC:mem-writers, itc.i, itc.d, itr.i, itr.d, IC:probe-all, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, tak, thash, tpa, ttag; data
+RR#; IC:mov-to-IND-RR+6; IC:mov-from-IND-RR+6; impliedF
+RSE; IC:rse-writers+14; IC:rse-readers+14; impliedF
--- /dev/null
+Resource Name; Readers; Writers; Results of Dependency
+PR63; IC:pr-readers-br+1; IC:mod-sched-brs; impliedF
--- /dev/null
+Resource Name; Writers; Writers; Semantics of Dependency
+ALAT; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; none
+AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; impliedF
+AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; impliedF
+AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF
+AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; impliedF
+AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; IC:mov-to-AR-FPSR, fsetc.s0; impliedF
+AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; IC:mov-to-AR-FPSR, fsetc.s1; impliedF
+AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; IC:mov-to-AR-FPSR, fsetc.s2; impliedF
+AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; IC:mov-to-AR-FPSR, fsetc.s3; impliedF
+AR[FPSR].sf0.flags; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; none
+AR[FPSR].sf0.flags; fclrf.s0, IC:fcmp-s0, IC:fp-arith-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; fclrf.s0, IC:mov-to-AR-FPSR; impliedF
+AR[FPSR].sf1.flags; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; none
+AR[FPSR].sf1.flags; fclrf.s1, IC:fcmp-s1, IC:fp-arith-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; fclrf.s1, IC:mov-to-AR-FPSR; impliedF
+AR[FPSR].sf2.flags; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; none
+AR[FPSR].sf2.flags; fclrf.s2, IC:fcmp-s2, IC:fp-arith-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; fclrf.s2, IC:mov-to-AR-FPSR; impliedF
+AR[FPSR].sf3.flags; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; none
+AR[FPSR].sf3.flags; fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; fclrf.s3, IC:mov-to-AR-FPSR; impliedF
+AR[FPSR].rv; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF
+AR[FPSR].traps; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF
+AR[ITC]; IC:mov-to-AR-ITC; IC:mov-to-AR-ITC; impliedF
+AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; IC:mov-to-AR-K+1; impliedF
+AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; impliedF
+AR[PFS]; br.call, brl.call; br.call, brl.call; none
+AR[PFS]; br.call, brl.call; IC:mov-to-AR-PFS; impliedF
+AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF
+AR[RSC]; IC:mov-to-AR-RSC; IC:mov-to-AR-RSC; impliedF
+AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; IC:mov-to-AR-UNAT, st8.spill; impliedF
+AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; IC:none; none
+AR%, % in 48 - 63, 112-127; IC:mov-to-AR-ig+1; IC:mov-to-AR-ig+1; impliedF
+BR%, % in 0 - 7; br.call+1, brl.call+1; IC:mov-to-BR+1; impliedF
+BR%, % in 0 - 7; IC:mov-to-BR+1; IC:mov-to-BR+1; impliedF
+BR%, % in 0 - 7; br.call+1, brl.call+1; br.call+1, brl.call+1; none
+CFM; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; impliedF
+CPUID#; IC:none; IC:none; none
+CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-to-CR-CMCV; impliedF
+CR[DCR]; IC:mov-to-CR-DCR; IC:mov-to-CR-DCR; impliedF
+CR[EOI]; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; SC Section 10.8.3.4
+CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-to-CR-GPTA; impliedF
+CR[IFA]; IC:mov-to-CR-IFA; IC:mov-to-CR-IFA; impliedF
+CR[IFS]; IC:mov-to-CR-IFS, cover; IC:mov-to-CR-IFS, cover; impliedF
+CR[IHA]; IC:mov-to-CR-IHA; IC:mov-to-CR-IHA; impliedF
+CR[IIM]; IC:mov-to-CR-IIM; IC:mov-to-CR-IIM; impliedF
+CR[IIP]; IC:mov-to-CR-IIP; IC:mov-to-CR-IIP; impliedF
+CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-to-CR-IIPA; impliedF
+CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-to-CR-IPSR; impliedF
+CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF
+CR[ISR]; IC:mov-to-CR-ISR; IC:mov-to-CR-ISR; impliedF
+CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-to-CR-ITIR; impliedF
+CR[ITM]; IC:mov-to-CR-ITM; IC:mov-to-CR-ITM; impliedF
+CR[ITV]; IC:mov-to-CR-ITV; IC:mov-to-CR-ITV; impliedF
+CR[IVA]; IC:mov-to-CR-IVA; IC:mov-to-CR-IVA; impliedF
+CR[IVR]; IC:none; IC:none; SC
+CR[LID]; IC:mov-to-CR-LID; IC:mov-to-CR-LID; SC
+CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-to-CR-LRR+1; impliedF
+CR[PMV]; IC:mov-to-CR-PMV; IC:mov-to-CR-PMV; impliedF
+CR[PTA]; IC:mov-to-CR-PTA; IC:mov-to-CR-PTA; impliedF
+CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-CR-TPR; impliedF
+CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:none; none
+DBR#; IC:mov-to-IND-DBR+3; IC:mov-to-IND-DBR+3; impliedF
+DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none
+DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF
+DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF
+DTR; itr.d; itr.d; impliedF
+DTR; itr.d; ptr.d; impliedF
+DTR; ptr.d; ptr.d; none
+FR%, % in 0 - 1; IC:none; IC:none; none
+FR%, % in 2 - 127; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; impliedF
+GR0; IC:none; IC:none; none
+GR%, % in 1 - 127; IC:ld-c+1, IC:gr-writers+1; IC:ld-c+1, IC:gr-writers+1; impliedF
+IBR#; IC:mov-to-IND-IBR+3; IC:mov-to-IND-IBR+3; impliedF
+InService*; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; SC
+IP; IC:all; IC:all; none
+ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none
+ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF
+ITR; itr.i; itr.i, ptr.i; impliedF
+ITR; ptr.i; ptr.i; none
+memory; IC:mem-writers; IC:mem-writers; none
+MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC
+PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none
+PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF
+PMC#; IC:mov-to-IND-PMC+3; IC:mov-to-IND-PMC+3; impliedF
+PMD#; IC:mov-to-IND-PMD+3; IC:mov-to-IND-PMD+3; impliedF
+PR0; IC:pr-writers+1; IC:pr-writers+1; none
+PR%, % in 1 - 62; IC:pr-and-writers+1; IC:pr-and-writers+1; none
+PR%, % in 1 - 62; IC:pr-or-writers+1; IC:pr-or-writers+1; none
+PR%, % in 1 - 62; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR+7; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR+7; impliedF
+PR63; IC:pr-and-writers+1; IC:pr-and-writers+1; none
+PR63; IC:pr-or-writers+1; IC:pr-or-writers+1; none
+PR63; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR+7; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR+7; impliedF
+PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.bn; bsw, rfi; bsw, rfi; impliedF
+PSR.cpl; epc, br.ret, rfi; epc, br.ret, rfi; impliedF
+PSR.da; rfi; rfi; impliedF
+PSR.db; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF
+PSR.dd; rfi; rfi; impliedF
+PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.ed; rfi; rfi; impliedF
+PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.ia; rfi; rfi; impliedF
+PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.id; rfi; rfi; impliedF
+PSR.is; br.ia, rfi; br.ia, rfi; impliedF
+PSR.it; rfi; rfi; impliedF
+PSR.lp; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF
+PSR.mc; rfi; rfi; impliedF
+PSR.mfh; IC:fr-writers+9; IC:fr-writers+9; none
+PSR.mfh; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.mfl; IC:fr-writers+9; IC:fr-writers+9; none
+PSR.mfl; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.ri; rfi; rfi; impliedF
+PSR.rt; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF
+PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+PSR.ss; rfi; rfi; impliedF
+PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF
+PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
+RR#; IC:mov-to-IND-RR+6; IC:mov-to-IND-RR+6; impliedF
+RSE; IC:rse-writers+14; IC:rse-writers+14; impliedF
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