drm/amd/display: Block FPO / SubVP (DRR) on HDMI VRR configs

[Description]
- Current policy does not support HDMI VRR by default, so we
  cannot enable FPO / SubVP (DRR) cases

Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 2278e61..e7459fd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -979,8 +979,11 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
        }
        // Use ignore_msa_timing_param flag to identify as DRR
        if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) {
-               // SUBVP + DRR case
-               schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]);
+               // SUBVP + DRR case -- don't enable SubVP + DRR for HDMI VRR cases
+               if (context->res_ctx.pipe_ctx[vblank_index].stream->allow_freesync)
+                       schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]);
+               else
+                       schedulable = false;
        } else if (found) {
                main_timing = &subvp_pipe->stream->timing;
                phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
@@ -1195,7 +1198,7 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
                                            pipe->stream->mall_stream_config.type == SUBVP_NONE) {
                                                non_subvp_pipes++;
                                                // Use ignore_msa_timing_param flag to identify as DRR
-                                               if (pipe->stream->ignore_msa_timing_param) {
+                                               if (pipe->stream->ignore_msa_timing_param && pipe->stream->allow_freesync) {
                                                        drr_pipe_found = true;
                                                        drr_pipe_index = i;
                                                }