uint32_t config;
if (!STE_VALID(ste)) {
- qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n");
+ if (!event->inval_ste_allowed) {
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n");
+ }
goto bad_ste;
}
if (!span) {
/* l2ptr is not valid */
- qemu_log_mask(LOG_GUEST_ERROR,
- "invalid sid=%d (L1STD span=0)\n", sid);
+ if (!event->inval_ste_allowed) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "invalid sid=%d (L1STD span=0)\n", sid);
+ }
event->type = SMMU_EVT_C_BAD_STREAMID;
return -EINVAL;
}
SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
SMMUv3State *s = sdev->smmu;
uint32_t sid = smmu_get_sid(sdev);
- SMMUEventInfo event = {.type = SMMU_EVT_NONE, .sid = sid};
+ SMMUEventInfo event = {.type = SMMU_EVT_NONE,
+ .sid = sid,
+ .inval_ste_allowed = false};
SMMUPTWEventInfo ptw_info = {};
SMMUTranslationStatus status;
SMMUState *bs = ARM_SMMU(s);
dma_addr_t iova)
{
SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
- SMMUEventInfo event = {};
+ SMMUEventInfo event = {.inval_ste_allowed = true};
SMMUTransTableInfo *tt;
SMMUTransCfg *cfg;
IOMMUTLBEntry entry;
cfg = smmuv3_get_config(sdev, &event);
if (!cfg) {
- qemu_log_mask(LOG_GUEST_ERROR,
- "%s error decoding the configuration for iommu mr=%s\n",
- __func__, mr->parent_obj.name);
return;
}