drm/amdgpu: cleanup VA IOCTL

Remove the unnecessary returned status and make the IOCTL write only.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index e8409fe..0ec2222 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -505,7 +505,7 @@ error_free:
 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
                          struct drm_file *filp)
 {
-       union drm_amdgpu_gem_va *args = data;
+       struct drm_amdgpu_gem_va *args = data;
        struct drm_gem_object *gobj;
        struct amdgpu_device *adev = dev->dev_private;
        struct amdgpu_fpriv *fpriv = filp->driver_priv;
@@ -514,95 +514,73 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
        uint32_t invalid_flags, va_flags = 0;
        int r = 0;
 
-       if (!adev->vm_manager.enabled) {
-               memset(args, 0, sizeof(*args));
-               args->out.result = AMDGPU_VA_RESULT_ERROR;
+       if (!adev->vm_manager.enabled)
                return -ENOTTY;
-       }
 
-       if (args->in.va_address < AMDGPU_VA_RESERVED_SIZE) {
+       if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
                dev_err(&dev->pdev->dev,
                        "va_address 0x%lX is in reserved area 0x%X\n",
-                       (unsigned long)args->in.va_address,
+                       (unsigned long)args->va_address,
                        AMDGPU_VA_RESERVED_SIZE);
-               memset(args, 0, sizeof(*args));
-               args->out.result = AMDGPU_VA_RESULT_ERROR;
                return -EINVAL;
        }
 
        invalid_flags = ~(AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
                        AMDGPU_VM_PAGE_EXECUTABLE);
-       if ((args->in.flags & invalid_flags)) {
+       if ((args->flags & invalid_flags)) {
                dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
-                       args->in.flags, invalid_flags);
-               memset(args, 0, sizeof(*args));
-               args->out.result = AMDGPU_VA_RESULT_ERROR;
+                       args->flags, invalid_flags);
                return -EINVAL;
        }
 
-       switch (args->in.operation) {
+       switch (args->operation) {
        case AMDGPU_VA_OP_MAP:
        case AMDGPU_VA_OP_UNMAP:
                break;
        default:
                dev_err(&dev->pdev->dev, "unsupported operation %d\n",
-                       args->in.operation);
-               memset(args, 0, sizeof(*args));
-               args->out.result = AMDGPU_VA_RESULT_ERROR;
+                       args->operation);
                return -EINVAL;
        }
 
-       gobj = drm_gem_object_lookup(dev, filp, args->in.handle);
-       if (gobj == NULL) {
-               memset(args, 0, sizeof(*args));
-               args->out.result = AMDGPU_VA_RESULT_ERROR;
+       gobj = drm_gem_object_lookup(dev, filp, args->handle);
+       if (gobj == NULL)
                return -ENOENT;
-       }
+
        rbo = gem_to_amdgpu_bo(gobj);
        r = amdgpu_bo_reserve(rbo, false);
        if (r) {
-               if (r != -ERESTARTSYS) {
-                       memset(args, 0, sizeof(*args));
-                       args->out.result = AMDGPU_VA_RESULT_ERROR;
-               }
                drm_gem_object_unreference_unlocked(gobj);
                return r;
        }
+
        bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo);
        if (!bo_va) {
-               memset(args, 0, sizeof(*args));
-               args->out.result = AMDGPU_VA_RESULT_ERROR;
-               drm_gem_object_unreference_unlocked(gobj);
+               amdgpu_bo_unreserve(rbo);
                return -ENOENT;
        }
 
-       switch (args->in.operation) {
+       switch (args->operation) {
        case AMDGPU_VA_OP_MAP:
-               if (args->in.flags & AMDGPU_VM_PAGE_READABLE)
+               if (args->flags & AMDGPU_VM_PAGE_READABLE)
                        va_flags |= AMDGPU_PTE_READABLE;
-               if (args->in.flags & AMDGPU_VM_PAGE_WRITEABLE)
+               if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
                        va_flags |= AMDGPU_PTE_WRITEABLE;
-               if (args->in.flags & AMDGPU_VM_PAGE_EXECUTABLE)
+               if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
                        va_flags |= AMDGPU_PTE_EXECUTABLE;
-               r = amdgpu_vm_bo_map(adev, bo_va, args->in.va_address,
-                                    args->in.offset_in_bo, args->in.map_size,
+               r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
+                                    args->offset_in_bo, args->map_size,
                                     va_flags);
                break;
        case AMDGPU_VA_OP_UNMAP:
-               r = amdgpu_vm_bo_unmap(adev, bo_va, args->in.va_address);
+               r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
                break;
        default:
                break;
        }
 
-       if (!r) {
+       if (!r)
                amdgpu_gem_va_update_vm(adev, bo_va);
-               memset(args, 0, sizeof(*args));
-               args->out.result = AMDGPU_VA_RESULT_OK;
-       } else {
-               memset(args, 0, sizeof(*args));
-               args->out.result = AMDGPU_VA_RESULT_ERROR;
-       }
 
        drm_gem_object_unreference_unlocked(gobj);
        return r;

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 3b911b6..4c465e1 100644 (file)
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -55,7 +55,7 @@
 #define DRM_IOCTL_AMDGPU_INFO          DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
 #define DRM_IOCTL_AMDGPU_GEM_METADATA  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
-#define DRM_IOCTL_AMDGPU_GEM_VA                DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va)
+#define DRM_IOCTL_AMDGPU_GEM_VA                DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
 #define DRM_IOCTL_AMDGPU_WAIT_CS       DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
 #define DRM_IOCTL_AMDGPU_GEM_OP                DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
 #define DRM_IOCTL_AMDGPU_GEM_USERPTR   DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
@@ -290,10 +290,6 @@ struct drm_amdgpu_gem_op {
 #define AMDGPU_VA_OP_MAP                       1
 #define AMDGPU_VA_OP_UNMAP                     2
 
-#define AMDGPU_VA_RESULT_OK                    0
-#define AMDGPU_VA_RESULT_ERROR                 1
-#define AMDGPU_VA_RESULT_VA_INVALID_ALIGNMENT  2
-
 /* Mapping flags */
 /* readable mapping */
 #define AMDGPU_VM_PAGE_READABLE                (1 << 1)
@@ -302,7 +298,7 @@ struct drm_amdgpu_gem_op {
 /* executable mapping, new for VI */
 #define AMDGPU_VM_PAGE_EXECUTABLE      (1 << 3)
 
-struct drm_amdgpu_gem_va_in {
+struct drm_amdgpu_gem_va {
        /* GEM object handle */
        uint32_t handle;
        uint32_t _pad;
@@ -319,16 +315,6 @@ struct drm_amdgpu_gem_va_in {
        uint64_t map_size;
 };
 
-struct drm_amdgpu_gem_va_out {
-       uint32_t result;
-       uint32_t _pad;
-};
-
-union drm_amdgpu_gem_va {
-       struct drm_amdgpu_gem_va_in  in;
-       struct drm_amdgpu_gem_va_out out;
-};
-
 #define AMDGPU_HW_IP_GFX          0
 #define AMDGPU_HW_IP_COMPUTE      1
 #define AMDGPU_HW_IP_DMA          2