mips64
parisc
ppc
+ ppc64
s390
sh4
sparc
mkstemp
pld
posix_memalign
- ppc64
round
roundf
sdl
;;
ppc64)
arch="ppc"
+ subarch="ppc64"
enable fast_64bit
enable fast_unaligned
;;
G5|g5|970|ppc970|PowerPC970|power4*|Power4*)
add_cflags -mcpu=970 -mpowerpc-gfxopt -mpowerpc64
warn_altivec disabled PPC970
- enable ppc64
;;
Cell|CELL|cell)
add_cflags -mcpu=cell
warn_altivec disabled Cell
- enable ppc64 ldbrx
+ enable ldbrx
;;
# targets that do NOT support conditional mov (cmov)
i[345]86|pentium|pentium-mmx|k6|k6-[23]|winchip-c6|winchip2|c3)
void powerpc_display_perf_report(void);
/* the 604* have 2, the G3* have 4, the G4s have 6,
and the G5 are completely different (they MUST use
- HAVE_PPC64, and let's hope all future 64 bis PPC
+ ARCH_PPC64, and let's hope all future 64 bis PPC
will use the same PMCs... */
#define POWERPC_NUM_PMC_ENABLED 6
/* if you add to the enum below, also add to the perfname array
};
extern unsigned long long perfdata[POWERPC_NUM_PMC_ENABLED][powerpc_perf_total][powerpc_data_total];
-#if !HAVE_PPC64
+#if !ARCH_PPC64
#define POWERP_PMC_DATATYPE unsigned long
#define POWERPC_GET_PMC1(a) __asm__ volatile("mfspr %0, 937" : "=r" (a))
#define POWERPC_GET_PMC2(a) __asm__ volatile("mfspr %0, 938" : "=r" (a))
#define POWERPC_GET_PMC5(a) do {} while (0)
#define POWERPC_GET_PMC6(a) do {} while (0)
#endif
-#else /* HAVE_PPC64 */
+#else /* ARCH_PPC64 */
#define POWERP_PMC_DATATYPE unsigned long long
#define POWERPC_GET_PMC1(a) __asm__ volatile("mfspr %0, 771" : "=r" (a))
#define POWERPC_GET_PMC2(a) __asm__ volatile("mfspr %0, 772" : "=r" (a))
#define POWERPC_GET_PMC5(a) do {} while (0)
#define POWERPC_GET_PMC6(a) do {} while (0)
#endif
-#endif /* HAVE_PPC64 */
+#endif /* ARCH_PPC64 */
#define POWERPC_PERF_DECLARE(a, cond) \
POWERP_PMC_DATATYPE \
pmc_start[POWERPC_NUM_PMC_ENABLED], \