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perf arm-spe: Add raw decoding for SPEv1.3 MTE and MOPS load/store
authorRob Herring <robh@kernel.org>
Mon, 27 Mar 2023 16:20:57 +0000 (11:20 -0500)
committerArnaldo Carvalho de Melo <acme@redhat.com>
Tue, 4 Apr 2023 12:39:57 +0000 (09:39 -0300)
Arm SPEv1.3 adds new load/store operation subclasses for Memory Tagging
Extension (MTE) and memory operations (MOPS). The memory operations
are memcpy and memset. Add support for decoding these new subclasses in
the raw decoding.

Reviewed-by: Leo Yan <leo.yan@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20230327162057.4057188-1-robh@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

index fed4741..a454c67 100644 (file)
@@ -381,6 +381,15 @@ static int arm_spe_pkt_desc_op_type(const struct arm_spe_pkt *packet,
                case SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG:
                        arm_spe_pkt_out_string(&err, &buf, &buf_len, " NV-SYSREG");
                        break;
+               case SPE_OP_PKT_LDST_SUBCLASS_MTE_TAG:
+                       arm_spe_pkt_out_string(&err, &buf, &buf_len, " MTE-TAG");
+                       break;
+               case SPE_OP_PKT_LDST_SUBCLASS_MEMCPY:
+                       arm_spe_pkt_out_string(&err, &buf, &buf_len, " MEMCPY");
+                       break;
+               case SPE_OP_PKT_LDST_SUBCLASS_MEMSET:
+                       arm_spe_pkt_out_string(&err, &buf, &buf_len, " MEMSET");
+                       break;
                default:
                        break;
                }
index f75ed3a..464a912 100644 (file)
@@ -123,6 +123,9 @@ enum arm_spe_events {
 #define SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP       0x4
 #define SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG    0x10
 #define SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG     0x30
+#define SPE_OP_PKT_LDST_SUBCLASS_MTE_TAG       0x14
+#define SPE_OP_PKT_LDST_SUBCLASS_MEMCPY                0x20
+#define SPE_OP_PKT_LDST_SUBCLASS_MEMSET                0x25
 
 #define SPE_OP_PKT_IS_LDST_ATOMIC(v)           (((v) & (GENMASK_ULL(7, 5) | BIT(1))) == 0x2)