drm/amd/powerplay: update ppatomfwctl (v2)

Add new get_smc_dpm_information api to fetch the smu dpm
info from the vbios.

v2: deal with updated table format.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
index 560c1c1..55f9b30 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
@@ -532,6 +532,7 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
        boot_values->usVddci    = info->bootup_vddci_mv;
        boot_values->usMvddc    = info->bootup_mvddc_mv;
        boot_values->usVddGfx   = info->bootup_vddgfx_mv;
+       boot_values->ucCoolingID = info->coolingsolution_id;
        boot_values->ulSocClk   = 0;
        boot_values->ulDCEFClk   = 0;
 
@@ -543,3 +544,89 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
 
        return 0;
 }
+
+int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
+               struct pp_atomfwctrl_smc_dpm_parameters *param)
+{
+       struct atom_smc_dpm_info_v4_1 *info;
+       uint16_t ix;
+
+       ix = GetIndexIntoMasterDataTable(smc_dpm_info);
+       info = (struct atom_smc_dpm_info_v4_1 *)
+               cgs_atom_get_data_table(hwmgr->device,
+                               ix, NULL, NULL, NULL);
+       if (!info) {
+               pr_info("Error retrieving BIOS Table Address!");
+               return -EINVAL;
+       }
+
+       param->liquid1_i2c_address = info->liquid1_i2c_address;
+       param->liquid2_i2c_address = info->liquid2_i2c_address;
+       param->vr_i2c_address = info->vr_i2c_address;
+       param->plx_i2c_address = info->plx_i2c_address;
+
+       param->liquid_i2c_linescl = info->liquid_i2c_linescl;
+       param->liquid_i2c_linesda = info->liquid_i2c_linesda;
+       param->vr_i2c_linescl = info->vr_i2c_linescl;
+       param->vr_i2c_linesda = info->vr_i2c_linesda;
+
+       param->plx_i2c_linescl = info->plx_i2c_linescl;
+       param->plx_i2c_linesda = info->plx_i2c_linesda;
+       param->vrsensorpresent = info->vrsensorpresent;
+       param->liquidsensorpresent = info->liquidsensorpresent;
+
+       param->maxvoltagestepgfx = info->maxvoltagestepgfx;
+       param->maxvoltagestepsoc = info->maxvoltagestepsoc;
+
+       param->vddgfxvrmapping = info->vddgfxvrmapping;
+       param->vddsocvrmapping = info->vddsocvrmapping;
+       param->vddmem0vrmapping = info->vddmem0vrmapping;
+       param->vddmem1vrmapping = info->vddmem1vrmapping;
+
+       param->gfxulvphasesheddingmask = info->gfxulvphasesheddingmask;
+       param->soculvphasesheddingmask = info->soculvphasesheddingmask;
+
+       param->gfxmaxcurrent = info->gfxmaxcurrent;
+       param->gfxoffset = info->gfxoffset;
+       param->padding_telemetrygfx = info->padding_telemetrygfx;
+
+       param->socmaxcurrent = info->socmaxcurrent;
+       param->socoffset = info->socoffset;
+       param->padding_telemetrysoc = info->padding_telemetrysoc;
+
+       param->mem0maxcurrent = info->mem0maxcurrent;
+       param->mem0offset = info->mem0offset;
+       param->padding_telemetrymem0 = info->padding_telemetrymem0;
+
+       param->mem1maxcurrent = info->mem1maxcurrent;
+       param->mem1offset = info->mem1offset;
+       param->padding_telemetrymem1 = info->padding_telemetrymem1;
+
+       param->acdcgpio = info->acdcgpio;
+       param->acdcpolarity = info->acdcpolarity;
+       param->vr0hotgpio = info->vr0hotgpio;
+       param->vr0hotpolarity = info->vr0hotpolarity;
+
+       param->vr1hotgpio = info->vr1hotgpio;
+       param->vr1hotpolarity = info->vr1hotpolarity;
+       param->padding1 = info->padding1;
+       param->padding2 = info->padding2;
+
+       param->ledpin0 = info->ledpin0;
+       param->ledpin1 = info->ledpin1;
+       param->ledpin2 = info->ledpin2;
+
+       param->gfxclkspreadenabled = info->gfxclkspreadenabled;
+       param->gfxclkspreadpercent = info->gfxclkspreadpercent;
+       param->gfxclkspreadfreq = info->gfxclkspreadfreq;
+
+       param->uclkspreadenabled = info->uclkspreadenabled;
+       param->uclkspreadpercent = info->uclkspreadpercent;
+       param->uclkspreadfreq = info->uclkspreadfreq;
+
+       param->socclkspreadenabled = info->socclkspreadenabled;
+       param->socclkspreadpercent = info->socclkspreadpercent;
+       param->socclkspreadfreq = info->socclkspreadfreq;
+
+       return 0;
+}

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
index 8e6b1f0..a957d8f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
@@ -140,6 +140,69 @@ struct pp_atomfwctrl_bios_boot_up_values {
        uint16_t   usVddci;
        uint16_t   usMvddc;
        uint16_t   usVddGfx;
+       uint8_t    ucCoolingID;
+};
+
+struct pp_atomfwctrl_smc_dpm_parameters
+{
+  uint8_t  liquid1_i2c_address;
+  uint8_t  liquid2_i2c_address;
+  uint8_t  vr_i2c_address;
+  uint8_t  plx_i2c_address;
+  uint8_t  liquid_i2c_linescl;
+  uint8_t  liquid_i2c_linesda;
+  uint8_t  vr_i2c_linescl;
+  uint8_t  vr_i2c_linesda;
+  uint8_t  plx_i2c_linescl;
+  uint8_t  plx_i2c_linesda;
+  uint8_t  vrsensorpresent;
+  uint8_t  liquidsensorpresent;
+  uint16_t maxvoltagestepgfx;
+  uint16_t maxvoltagestepsoc;
+  uint8_t  vddgfxvrmapping;
+  uint8_t  vddsocvrmapping;
+  uint8_t  vddmem0vrmapping;
+  uint8_t  vddmem1vrmapping;
+  uint8_t  gfxulvphasesheddingmask;
+  uint8_t  soculvphasesheddingmask;
+
+  uint16_t gfxmaxcurrent;
+  uint8_t  gfxoffset;
+  uint8_t  padding_telemetrygfx;
+  uint16_t socmaxcurrent;
+  uint8_t  socoffset;
+  uint8_t  padding_telemetrysoc;
+  uint16_t mem0maxcurrent;
+  uint8_t  mem0offset;
+  uint8_t  padding_telemetrymem0;
+  uint16_t mem1maxcurrent;
+  uint8_t  mem1offset;
+  uint8_t  padding_telemetrymem1;
+
+  uint8_t  acdcgpio;
+  uint8_t  acdcpolarity;
+  uint8_t  vr0hotgpio;
+  uint8_t  vr0hotpolarity;
+  uint8_t  vr1hotgpio;
+  uint8_t  vr1hotpolarity;
+  uint8_t  padding1;
+  uint8_t  padding2;
+
+  uint8_t  ledpin0;
+  uint8_t  ledpin1;
+  uint8_t  ledpin2;
+
+  uint8_t  gfxclkspreadenabled;
+  uint8_t  gfxclkspreadpercent;
+  uint16_t gfxclkspreadfreq;
+
+  uint8_t  uclkspreadenabled;
+  uint8_t  uclkspreadpercent;
+  uint16_t uclkspreadfreq;
+
+  uint8_t socclkspreadenabled;
+  uint8_t socclkspreadpercent;
+  uint16_t socclkspreadfreq;
 };
 
 int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
@@ -161,6 +224,8 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
 
 int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
                        struct pp_atomfwctrl_bios_boot_up_values *boot_values);
+int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
+                       struct pp_atomfwctrl_smc_dpm_parameters *param);
 
 #endif