// Make v4f16 (only) fcmp operations utilise vector instructions
// v8f16 support will be a litle more complicated
- if (LHS.getValueType().getVectorElementType() == MVT::f16) {
- if (!FullFP16 && LHS.getValueType().getVectorNumElements() == 4) {
+ if (!FullFP16 && LHS.getValueType().getVectorElementType() == MVT::f16) {
+ if (LHS.getValueType().getVectorNumElements() == 4) {
LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, LHS);
RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, RHS);
SDValue NewSetcc = DAG.getSetCC(dl, MVT::v4i16, LHS, RHS, CC);
return SDValue();
}
- assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
- LHS.getValueType().getVectorElementType() == MVT::f64);
+ assert((!FullFP16 && LHS.getValueType().getVectorElementType() != MVT::f16) ||
+ LHS.getValueType().getVectorElementType() != MVT::f128);
// Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
// clean. Some of them require two branches to implement.
; CHECK-FP16-LABEL: test_fcmp_une:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ne
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ne
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ne
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ne
-; CHECK-FP16: ret
+; CHECK-FP16: fcmeq v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp une <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_ueq:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: ret
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ueq <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_ugt:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, hi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, hi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, hi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, hi
-; CHECK-FP16: ret
+; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ugt <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_uge:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, pl
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, pl
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, pl
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, pl
-; CHECK-FP16: ret
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp uge <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_ult:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, lt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, lt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, lt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, lt
-; CHECK-FP16: ret
+; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ult <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_ule:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, le
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, le
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, le
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, le
-; CHECK-FP16: ret
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ule <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_uno:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vs
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vs
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vs
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vs
-; CHECK-FP16: ret
+; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp uno <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_one:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: ret
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp one <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_oeq:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: ret
+; CHECK-FP16: fcmeq v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp oeq <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_ogt:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, gt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, gt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, gt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, gt
-; CHECK-FP16: ret
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ogt <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_oge:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ge
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ge
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ge
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ge
-; CHECK-FP16: ret
+; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp oge <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_olt:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: ret
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp olt <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_ole:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ls
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ls
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ls
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ls
-; CHECK-FP16: ret
+; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ole <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_ord:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vc
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vc
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vc
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vc
-; CHECK-FP16: ret
+; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ord <4 x half> %a, %b
ret <4 x i1> %1
}
; CHECK-FP16-LABEL: test_fcmp_une:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmeq v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp une <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_ueq:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ueq <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_ugt:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ugt <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_uge:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp uge <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_ult:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ult <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_ule:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ule <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_uno:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp uno <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_one:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp one <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_oeq:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmeq v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp oeq <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_ogt:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ogt <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_oge:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp oge <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_olt:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp olt <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_ole:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ole <8 x half> %a, %b
ret <8 x i1> %1
; CHECK-FP16-LABEL: test_fcmp_ord:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ord <8 x half> %a, %b
ret <8 x i1> %1