The broken bot (clang-ppc64le-linux-multistage) is doign a shared-object build,
so I guess using lookupBankedRegByEncoding in the disassembler is a layering
violation?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324604
91177308-0d34-0410-b5e6-
96231b3b80d8
// The table of encodings for these banked registers comes from B9.2.3 of the
// ARM ARM. There are patterns, but nothing regular enough to make this logic
// neater. So by fiat, these values are UNPREDICTABLE:
- if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
- return MCDisassembler::Fail;
+ if (!R) {
+ if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
+ SysM == 0x1a || SysM == 0x1b)
+ return MCDisassembler::SoftFail;
+ } else {
+ if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
+ SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
+ return MCDisassembler::SoftFail;
+ }
Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
-# RUN: not llvm-mc -disassemble %s -mcpu cortex-a15 -triple armv7 2>&1 | FileCheck %s
+# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple armv7 2>&1 | FileCheck %s
# This file is checking ARMv7 encodings which are globally invalid, usually due
# to the constraints of the instructions not being met. For example invalid
[0x3d 0x3c 0xa0 0xf4]
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x3d 0x3c 0xa0 0xf4]
-
-
-#------------------------------------------------------------------------------
-# Undefined encodings for MSR/MRS (banked register)
-#------------------------------------------------------------------------------
-# These have a banked register encoding of 0b111111, which is unallocated.
-
-# msr <invalid>, r0
-[0x00,0xf3,0x6f,0xe1]
-# CHECK: invalid instruction encoding
-# CHECK-NEXT: [0x00,0xf3,0x6f,0xe1]
-
-# mrs r0, <invalid>
-[0x00,0x03,0x4f,0xe1]
-# CHECK: invalid instruction encoding
-# CHECK-NEXT: [0x00,0x03,0x4f,0xe1]
-# RUN: not llvm-mc -disassemble %s -mcpu cortex-a15 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
+# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
# RUN: not llvm-mc -disassemble %s -mcpu cortex-a53 -triple thumbv8 2>&1 | FileCheck %s
# This file is checking Thumbv7 encodings which are globally invalid, usually due
[0x63 0xeb 0x2d 0x46]
# CHECK-V7: warning: potentially undefined instruction encoding
# CHECK-V7-NEXT: [0x63 0xeb 0x2d 0x46]
-
-#------------------------------------------------------------------------------
-# Undefined encodings for MSR/MRS (banked register)
-#------------------------------------------------------------------------------
-# These have a banked register encoding of 0b111111, which is unallocated.
-
-# msr <invalid>, r0
-[0x90,0xf3,0x30,0x8f]
-# CHECK: invalid instruction encoding
-# CHECK-NEXT: [0x90,0xf3,0x30,0x8f]
-
-# mrs r0, <invalid>
-[0xff,0xf3,0x30,0x80]
-# CHECK: invalid instruction encoding
-# CHECK-NEXT: [0xff,0xf3,0x30,0x80]