drm/amd/display: Clean up some DCN1 guards

Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 84b1f51..9084a32 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -58,6 +58,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
                *h = dal_cmd_tbl_helper_dce112_get_table2();
                return true;
 #endif
+
        case DCE_VERSION_12_0:
                *h = dal_cmd_tbl_helper_dce112_get_table2();
                return true;

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 9c2faf8..bab07f8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1109,7 +1109,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
 
        /* 3rd param should be true, temp w/a for RV*/
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-       core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0);
+       core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version < DCN_VERSION_1_0);
 #else
        core_dc->hwss.set_bandwidth(core_dc, context, true);
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 4403d82..dea2943 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -120,6 +120,8 @@ struct resource_pool *dc_create_resource_pool(
                        num_virtual_links, dc);
                break;
 #endif
+
+
        default:
                break;
        }

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 142b3a0..2205491 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -589,6 +589,7 @@ static uint32_t dce110_get_pix_clk_dividers(
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
        case DCN_VERSION_1_0:
 #endif
+
                dce112_get_pix_clk_dividers_helper(clk_src,
                                pll_settings, pix_clk_params);
                break;
@@ -901,6 +902,7 @@ static bool dce110_program_pix_clk(
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
        case DCN_VERSION_1_0:
 #endif
+
                if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
                        bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
                                                        pll_settings->use_external_clk;

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index f30cd4d..37d074f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -614,7 +614,7 @@ static bool dce_apply_clock_voltage_request(
        }
        if (send_request) {
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-               if (clk->ctx->dce_version == DCN_VERSION_1_0) {
+               if (clk->ctx->dce_version >= DCN_VERSION_1_0) {
                        struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc);
                        /*use dcfclk request voltage*/
                        clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index aa4777a..1193659 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1104,11 +1104,11 @@ static enum dc_status apply_single_controller_ctx_to_hw(
                        true : false);
 
        resource_build_info_frame(pipe_ctx);
-
+       dce110_update_info_frame(pipe_ctx);
        if (!pipe_ctx_old->stream) {
                core_link_enable_stream(pipe_ctx);
 
-       dce110_update_info_frame(pipe_ctx);
+
                if (dc_is_dp_signal(pipe_ctx->stream->signal))
                        dce110_unblank_stream(pipe_ctx,
                                &stream->sink->link->cur_link_settings);
@@ -1664,7 +1664,7 @@ enum dc_status dce110_apply_ctx_to_hw(
        apply_min_clocks(dc, context, &clocks_state, true);
 
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-       if (dc->ctx->dce_version == DCN_VERSION_1_0) {
+       if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
                if (context->bw.dcn.calc_clk.fclk_khz
                                > dc->current_context->bw.dcn.cur_clk.fclk_khz) {
                        struct dm_pp_clock_for_voltage_req clock;

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index 8a8b619..425f1c4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -84,6 +84,7 @@ bool dal_hw_factory_init(
                dal_hw_factory_dcn10_init(factory);
                return true;
 #endif
+
        default:
                ASSERT_CRITICAL(false);
                return false;

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 36c082b..3b55d45 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -80,6 +80,7 @@ bool dal_hw_translate_init(
                dal_hw_translate_dcn10_init(translate);
                return true;
 #endif
+
        default:
                BREAK_TO_DEBUGGER();
                return false;

diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
index 45e766e..10061cc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
@@ -88,10 +88,11 @@ struct i2caux *dal_i2caux_create(
                return dal_i2caux_dce100_create(ctx);
        case DCE_VERSION_12_0:
                return dal_i2caux_dce120_create(ctx);
-       #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
        case DCN_VERSION_1_0:
                return dal_i2caux_dcn10_create(ctx);
-       #endif
+#endif
+
        default:
                BREAK_TO_DEBUGGER();
                return NULL;