arm64: dts: renesas: r9a09g011: Add eMMC and SDHI support

The RZ/V2M comes with 2 SDHI interfaces and 1 eMMC interface.
Add the relevant nodes to the SoC specific device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221213230129.549968-5-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index 0373ec4..dd35a8f 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -69,6 +69,54 @@
                        clock-names = "clk";
                };
 
+               sdhi0: mmc@85000000 {
+                       compatible = "renesas,sdhi-r9a09g011",
+                                    "renesas,rcar-gen3-sdhi";
+                       reg = <0x0 0x85000000 0 0x2000>;
+                       interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
+                                <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
+                                <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
+                                <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
+                       clock-names = "core", "clkh", "cd", "aclk";
+                       resets = <&cpg R9A09G011_SDI0_IXRST>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               sdhi1: mmc@85010000  {
+                       compatible = "renesas,sdhi-r9a09g011",
+                                    "renesas,rcar-gen3-sdhi";
+                       reg = <0x0 0x85010000 0 0x2000>;
+                       interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
+                                <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>,
+                                <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>,
+                                <&cpg CPG_MOD R9A09G011_SDI1_ACLK>;
+                       clock-names = "core", "clkh", "cd", "aclk";
+                       resets = <&cpg R9A09G011_SDI1_IXRST>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               emmc: mmc@85020000  {
+                       compatible = "renesas,sdhi-r9a09g011",
+                                    "renesas,rcar-gen3-sdhi";
+                       reg = <0x0 0x85020000 0 0x2000>;
+                       interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>,
+                                <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>,
+                                <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>,
+                                <&cpg CPG_MOD R9A09G011_EMM_ACLK>;
+                       clock-names = "core", "clkh", "cd", "aclk";
+                       resets = <&cpg R9A09G011_EMM_IXRST>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
                avb: ethernet@a3300000 {
                        compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m";
                        reg = <0 0xa3300000 0 0x800>;