; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
-define i64 @addc_adde(i64 %a, i64 %b) {
+define i64 @addc_adde(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: addc_adde:
; RV32I: # %bb.0:
; RV32I-NEXT: add a1, a1, a3
ret i64 %1
}
-define i64 @subc_sube(i64 %a, i64 %b) {
+define i64 @subc_sube(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: subc_sube:
; RV32I: # %bb.0:
; RV32I-NEXT: sub a1, a1, a3
declare i64 @llvm.smul.fix.i64 (i64, i64, i32)
-define i64 @addcarry(i64 %x, i64 %y) {
+define i64 @addcarry(i64 %x, i64 %y) nounwind {
; RISCV32-LABEL: addcarry:
; RISCV32: # %bb.0:
; RISCV32-NEXT: mul a4, a0, a3
; RV64I-only instructions
-define signext i32 @addiw(i32 signext %a) {
+define signext i32 @addiw(i32 signext %a) nounwind {
; RV64I-LABEL: addiw:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 123
ret i32 %1
}
-define signext i32 @slliw(i32 signext %a) {
+define signext i32 @slliw(i32 signext %a) nounwind {
; RV64I-LABEL: slliw:
; RV64I: # %bb.0:
; RV64I-NEXT: slliw a0, a0, 17
ret i32 %1
}
-define signext i32 @srliw(i32 %a) {
+define signext i32 @srliw(i32 %a) nounwind {
; RV64I-LABEL: srliw:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 8
ret i32 %1
}
-define signext i32 @sraiw(i32 %a) {
+define signext i32 @sraiw(i32 %a) nounwind {
; RV64I-LABEL: sraiw:
; RV64I: # %bb.0:
; RV64I-NEXT: sraiw a0, a0, 9
ret i32 %1
}
-define signext i32 @sextw(i32 zeroext %a) {
+define signext i32 @sextw(i32 zeroext %a) nounwind {
; RV64I-LABEL: sextw:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0
ret i32 %a
}
-define signext i32 @addw(i32 signext %a, i32 signext %b) {
+define signext i32 @addw(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: addw:
; RV64I: # %bb.0:
; RV64I-NEXT: addw a0, a0, a1
ret i32 %1
}
-define signext i32 @subw(i32 signext %a, i32 signext %b) {
+define signext i32 @subw(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: subw:
; RV64I: # %bb.0:
; RV64I-NEXT: subw a0, a0, a1
ret i32 %1
}
-define signext i32 @sllw(i32 signext %a, i32 zeroext %b) {
+define signext i32 @sllw(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sllw:
; RV64I: # %bb.0:
; RV64I-NEXT: sllw a0, a0, a1
ret i32 %1
}
-define signext i32 @srlw(i32 signext %a, i32 zeroext %b) {
+define signext i32 @srlw(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: srlw:
; RV64I: # %bb.0:
; RV64I-NEXT: srlw a0, a0, a1
ret i32 %1
}
-define signext i32 @sraw(i64 %a, i32 zeroext %b) {
+define signext i32 @sraw(i64 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sraw:
; RV64I: # %bb.0:
; RV64I-NEXT: sraw a0, a0, a1
; higher bits were masked to zero for the comparison.
define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp,
- i32 signext %val) {
+ i32 signext %val) nounwind {
; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64IA: # %bb.0: # %entry
; RV64IA-NEXT: .LBB0_1: # %entry
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-define i32 @bare_select(i1 %a, i32 %b, i32 %c) {
+define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: bare_select:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
ret i32 %1
}
-define float @bare_select_float(i1 %a, float %b, float %c) {
+define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
; RV32I-LABEL: bare_select_float:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
; RUN: -o /dev/null 2>&1
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s
-define void @relax_bcc(i1 %a) {
+define void @relax_bcc(i1 %a) nounwind {
; CHECK-LABEL: relax_bcc:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
ret void
}
-define i32 @relax_jal(i1 %a) {
+define i32 @relax_jal(i1 %a) nounwind {
; CHECK-LABEL: relax_jal:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-define void @foo(i32 %a, i32 *%b, i1 %c) {
+define void @foo(i32 %a, i32 *%b, i1 %c) nounwind {
; RV32I-LABEL: foo:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a3, 0(a1)
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) {
+define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) nounwind {
; RV32I-LABEL: getSetCCResultType:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lw a1, 12(a0)
@g = global [1048576 x i8] zeroinitializer, align 1
-define dso_local void @multiple_stores() local_unnamed_addr {
+define dso_local void @multiple_stores() local_unnamed_addr nounwind {
; CHECK-LABEL: multiple_stores:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s)
ret void
}
-define dso_local void @control_flow_with_mem_access() local_unnamed_addr #0 {
+define dso_local void @control_flow_with_mem_access() local_unnamed_addr nounwind {
; CHECK-LABEL: control_flow_with_mem_access:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s)
; lui a0, 18 ---> offset
; addi a0, a0, -160
; add a0, a0, a1 ---> base + offset.
-define i8* @big_offset_neg_addi() {
+define i8* @big_offset_neg_addi() nounwind {
; CHECK-LABEL: big_offset_neg_addi:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(g+73568)
; addi a0, a0, %lo(g)
; lui a1, 128 ---> offset
; add a0, a0, a1 ---> base + offset.
-define i8* @big_offset_lui_tail() {
+define i8* @big_offset_lui_tail() nounwind {
; CHECK-LABEL: big_offset_lui_tail:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(g+524288)
ret i8* getelementptr inbounds ([1048576 x i8], [1048576 x i8]* @g, i32 0, i32 524288)
}
-define dso_local i32* @big_offset_one_use() local_unnamed_addr {
+define dso_local i32* @big_offset_one_use() local_unnamed_addr nounwind {
; CHECK-LABEL: big_offset_one_use:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s+16572)
ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 5)
}
-define dso_local i32* @small_offset_one_use() local_unnamed_addr {
+define dso_local i32* @small_offset_one_use() local_unnamed_addr nounwind {
; CHECK-LABEL: small_offset_one_use:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s+160)
ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1)
}
-; Function Attrs: norecurse nounwind optsize readonly
-define dso_local i32* @control_flow_no_mem(i32 %n) local_unnamed_addr #1 {
+define dso_local i32* @control_flow_no_mem(i32 %n) local_unnamed_addr nounwind {
; CHECK-LABEL: control_flow_no_mem:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s)
declare void @abort()
-define dso_local void @one_store() local_unnamed_addr {
+define dso_local void @one_store() local_unnamed_addr nounwind {
; CHECK-LABEL: one_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s+160)
@gi = external global i32
-define i32 @constraint_r(i32 %a) {
+define i32 @constraint_r(i32 %a) nounwind {
; RV32I-LABEL: constraint_r:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, %hi(gi)
ret i32 %2
}
-define i32 @constraint_i(i32 %a) {
+define i32 @constraint_i(i32 %a) nounwind {
; RV32I-LABEL: constraint_i:
; RV32I: # %bb.0:
; RV32I-NEXT: #APP
ret i32 %2
}
-define void @constraint_m(i32* %a) {
+define void @constraint_m(i32* %a) nounwind {
; RV32I-LABEL: constraint_m:
; RV32I: # %bb.0:
; RV32I-NEXT: #APP
ret void
}
-define i32 @constraint_m2(i32* %a) {
+define i32 @constraint_m2(i32* %a) nounwind {
; RV32I-LABEL: constraint_m2:
; RV32I: # %bb.0:
; RV32I-NEXT: #APP
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-define void @jt(i32 %in, i32* %out) {
+define void @jt(i32 %in, i32* %out) nounwind {
; RV32I-LABEL: jt:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi a2, zero, 2
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64 %s
-define void @test1(float* %a, float* %b) {
+define void @test1(float* %a, float* %b) nounwind {
; RV32-LABEL: test1:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a1, 0(a1)
ret void
}
-define void @test2(double* %a, double* %b) {
+define void @test2(double* %a, double* %b) nounwind {
; RV32-LABEL: test2:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a2, 4(a1)
ret void
}
-define void @test3(fp128* %a, fp128* %b) {
+define void @test3(fp128* %a, fp128* %b) nounwind {
; RV32-LABEL: test3:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a2, 12(a1)
; These IR sequences will generate ISD::ROTL and ISD::ROTR nodes, that the
; RISC-V backend must be able to select
-define i32 @rotl(i32 %x, i32 %y) {
+define i32 @rotl(i32 %x, i32 %y) nounwind {
; RV32I-LABEL: rotl:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 32
ret i32 %d
}
-define i32 @rotr(i32 %x, i32 %y) {
+define i32 @rotr(i32 %x, i32 %y) nounwind {
; RV32I-LABEL: rotr:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 32
; patterns might make the mistake of assuming that a (sext_inreg foo, i32) can
; only be produced when sign-extending an i32 type.
-define i64 @tricky_shl(i64 %a, i64 %b) {
+define i64 @tricky_shl(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: tricky_shl:
; RV64I: # %bb.0:
; RV64I-NEXT: sll a0, a0, a1
ret i64 %3
}
-define i64 @tricky_lshr(i64 %a, i64 %b) {
+define i64 @tricky_lshr(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: tricky_lshr:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
ret i64 %2
}
-define i64 @tricky_ashr(i64 %a, i64 %b) {
+define i64 @tricky_ashr(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: tricky_ashr:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0
; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-define i32 @foo(i32 %a, i32 *%b) {
+define i32 @foo(i32 %a, i32 *%b) nounwind {
; RV32I-LABEL: foo:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a1)
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
-define i8 @sext_i1_to_i8(i1 %a) {
+define i8 @sext_i1_to_i8(i1 %a) nounwind {
; RV32I-LABEL: sext_i1_to_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
ret i8 %1
}
-define i16 @sext_i1_to_i16(i1 %a) {
+define i16 @sext_i1_to_i16(i1 %a) nounwind {
; RV32I-LABEL: sext_i1_to_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
ret i16 %1
}
-define i32 @sext_i1_to_i32(i1 %a) {
+define i32 @sext_i1_to_i32(i1 %a) nounwind {
; RV32I-LABEL: sext_i1_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
ret i32 %1
}
-define i64 @sext_i1_to_i64(i1 %a) {
+define i64 @sext_i1_to_i64(i1 %a) nounwind {
; RV32I-LABEL: sext_i1_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
ret i64 %1
}
-define i16 @sext_i8_to_i16(i8 %a) {
+define i16 @sext_i8_to_i16(i8 %a) nounwind {
; RV32I-LABEL: sext_i8_to_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 24
ret i16 %1
}
-define i32 @sext_i8_to_i32(i8 %a) {
+define i32 @sext_i8_to_i32(i8 %a) nounwind {
; RV32I-LABEL: sext_i8_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 24
ret i32 %1
}
-define i64 @sext_i8_to_i64(i8 %a) {
+define i64 @sext_i8_to_i64(i8 %a) nounwind {
; RV32I-LABEL: sext_i8_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 24
ret i64 %1
}
-define i32 @sext_i16_to_i32(i16 %a) {
+define i32 @sext_i16_to_i32(i16 %a) nounwind {
; RV32I-LABEL: sext_i16_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 16
ret i32 %1
}
-define i64 @sext_i16_to_i64(i16 %a) {
+define i64 @sext_i16_to_i64(i16 %a) nounwind {
; RV32I-LABEL: sext_i16_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 16
ret i64 %1
}
-define i64 @sext_i32_to_i64(i32 %a) {
+define i64 @sext_i32_to_i64(i32 %a) nounwind {
; RV32I-LABEL: sext_i32_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: srai a1, a0, 31
ret i64 %1
}
-define i8 @zext_i1_to_i8(i1 %a) {
+define i8 @zext_i1_to_i8(i1 %a) nounwind {
; RV32I-LABEL: zext_i1_to_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
ret i8 %1
}
-define i16 @zext_i1_to_i16(i1 %a) {
+define i16 @zext_i1_to_i16(i1 %a) nounwind {
; RV32I-LABEL: zext_i1_to_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
ret i16 %1
}
-define i32 @zext_i1_to_i32(i1 %a) {
+define i32 @zext_i1_to_i32(i1 %a) nounwind {
; RV32I-LABEL: zext_i1_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
ret i32 %1
}
-define i64 @zext_i1_to_i64(i1 %a) {
+define i64 @zext_i1_to_i64(i1 %a) nounwind {
; RV32I-LABEL: zext_i1_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
ret i64 %1
}
-define i16 @zext_i8_to_i16(i8 %a) {
+define i16 @zext_i8_to_i16(i8 %a) nounwind {
; RV32I-LABEL: zext_i8_to_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
ret i16 %1
}
-define i32 @zext_i8_to_i32(i8 %a) {
+define i32 @zext_i8_to_i32(i8 %a) nounwind {
; RV32I-LABEL: zext_i8_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
ret i32 %1
}
-define i64 @zext_i8_to_i64(i8 %a) {
+define i64 @zext_i8_to_i64(i8 %a) nounwind {
; RV32I-LABEL: zext_i8_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
ret i64 %1
}
-define i32 @zext_i16_to_i32(i16 %a) {
+define i32 @zext_i16_to_i32(i16 %a) nounwind {
; RV32I-LABEL: zext_i16_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
ret i32 %1
}
-define i64 @zext_i16_to_i64(i16 %a) {
+define i64 @zext_i16_to_i64(i16 %a) nounwind {
; RV32I-LABEL: zext_i16_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
ret i64 %1
}
-define i64 @zext_i32_to_i64(i32 %a) {
+define i64 @zext_i32_to_i64(i32 %a) nounwind {
; RV32I-LABEL: zext_i32_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a1, zero
ret i64 %1
}
-define i1 @trunc_i8_to_i1(i8 %a) {
+define i1 @trunc_i8_to_i1(i8 %a) nounwind {
; RV32I-LABEL: trunc_i8_to_i1:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
ret i1 %1
}
-define i1 @trunc_i16_to_i1(i16 %a) {
+define i1 @trunc_i16_to_i1(i16 %a) nounwind {
; RV32I-LABEL: trunc_i16_to_i1:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
ret i1 %1
}
-define i1 @trunc_i32_to_i1(i32 %a) {
+define i1 @trunc_i32_to_i1(i32 %a) nounwind {
; RV32I-LABEL: trunc_i32_to_i1:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
ret i1 %1
}
-define i1 @trunc_i64_to_i1(i64 %a) {
+define i1 @trunc_i64_to_i1(i64 %a) nounwind {
; RV32I-LABEL: trunc_i64_to_i1:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
ret i1 %1
}
-define i8 @trunc_i16_to_i8(i16 %a) {
+define i8 @trunc_i16_to_i8(i16 %a) nounwind {
; RV32I-LABEL: trunc_i16_to_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
ret i8 %1
}
-define i8 @trunc_i32_to_i8(i32 %a) {
+define i8 @trunc_i32_to_i8(i32 %a) nounwind {
; RV32I-LABEL: trunc_i32_to_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
ret i8 %1
}
-define i8 @trunc_i64_to_i8(i64 %a) {
+define i8 @trunc_i64_to_i8(i64 %a) nounwind {
; RV32I-LABEL: trunc_i64_to_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
ret i8 %1
}
-define i16 @trunc_i32_to_i16(i32 %a) {
+define i16 @trunc_i32_to_i16(i32 %a) nounwind {
; RV32I-LABEL: trunc_i32_to_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
ret i16 %1
}
-define i16 @trunc_i64_to_i16(i64 %a) {
+define i16 @trunc_i64_to_i16(i64 %a) nounwind {
; RV32I-LABEL: trunc_i64_to_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
ret i16 %1
}
-define i32 @trunc_i64_to_i32(i64 %a) {
+define i32 @trunc_i64_to_i32(i64 %a) nounwind {
; RV32I-LABEL: trunc_i64_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
; Perform tail call optimization for global address.
declare i32 @callee_tail(i32 %i)
-define i32 @caller_tail(i32 %i) {
+define i32 @caller_tail(i32 %i) nounwind {
; CHECK-LABEL: caller_tail
; CHECK: tail callee_tail
entry:
; Perform indirect tail call optimization (for function pointer call).
declare void @callee_indirect1()
declare void @callee_indirect2()
-define void @caller_indirect_tail(i32 %a) {
+define void @caller_indirect_tail(i32 %a) nounwind {
; CHECK-LABEL: caller_indirect_tail
; CHECK-NOT: call callee_indirect1
; CHECK-NOT: call callee_indirect2
; Do not tail call optimize functions with varargs.
declare i32 @callee_varargs(i32, ...)
-define void @caller_varargs(i32 %a, i32 %b) {
+define void @caller_varargs(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: caller_varargs
; CHECK-NOT: tail callee_varargs
; CHECK: call callee_varargs
; Do not tail call optimize if stack is used to pass parameters.
declare i32 @callee_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n)
-define i32 @caller_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n) {
+define i32 @caller_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n) nounwind {
; CHECK-LABEL: caller_args
; CHECK-NOT: tail callee_args
; CHECK: call callee_args
; Do not tail call optimize if parameters need to be passed indirectly.
declare i32 @callee_indirect_args(fp128 %a)
-define void @caller_indirect_args() {
+define void @caller_indirect_args() nounwind {
; CHECK-LABEL: caller_indirect_args
; CHECK-NOT: tail callee_indirect_args
; CHECK: call callee_indirect_args
; calls) is implementation-defined, so we cannot rely on the linker replacing
; the tail call with a return.
declare extern_weak void @callee_weak()
-define void @caller_weak() {
+define void @caller_weak() nounwind {
; CHECK-LABEL: caller_weak
; CHECK-NOT: tail callee_weak
; CHECK: call callee_weak
; we want to reuse during a tail call. Do not tail call optimize functions with
; byval parameters.
declare i32 @callee_byval(i32** byval %a)
-define i32 @caller_byval() {
+define i32 @caller_byval() nounwind {
; CHECK-LABEL: caller_byval
; CHECK-NOT: tail callee_byval
; CHECK: call callee_byval
@a = global %struct.A zeroinitializer
declare void @callee_struct(%struct.A* sret %a)
-define void @caller_nostruct() {
+define void @caller_nostruct() nounwind {
; CHECK-LABEL: caller_nostruct
; CHECK-NOT: tail callee_struct
; CHECK: call callee_struct
; Do not tail call optimize if caller uses structret semantics.
declare void @callee_nostruct()
-define void @caller_struct(%struct.A* sret %a) {
+define void @caller_struct(%struct.A* sret %a) nounwind {
; CHECK-LABEL: caller_struct
; CHECK-NOT: tail callee_nostruct
; CHECK: call callee_nostruct
@bytes = global [5 x i8] zeroinitializer, align 1
-define i32 @test_zext_i8() {
+define i32 @test_zext_i8() nounwind {
; RV32I-LABEL: test_zext_i8:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(bytes)
@shorts = global [5 x i16] zeroinitializer, align 2
-define i32 @test_zext_i16() {
+define i32 @test_zext_i16() nounwind {
; RV32I-LABEL: test_zext_i16:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(shorts)