2005-08-30 Paul Brook <paul@codesourcery.com>

opcodes/
	* arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
gas/testsuite/
	* gas/arm/thumb.d: Change "sub rn, rn, rn" to "subs rn, rn, rn".
	* gas/arm/thumb32.d: Ditto.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4b09b7a..1d8ed02 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2005-08-30  Paul Brook  <paul@codesourcery.com>
+
+       * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
+
 2005-08-26  Jan Beulich  <jbeulich@novell.com>
 
        * i386-dis.c (intel_operand_size): New, broken out from OP_E for

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index dbf91be..0f05501 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -724,9 +724,9 @@ static const struct opcode16 thumb_opcodes[] =
   {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop\t%O"},
   /* format 2 */
   {ARM_EXT_V4T, 0x1800, 0xFE00, "adds\t%0-2r, %3-5r, %6-8r"},
-  {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"},
+  {ARM_EXT_V4T, 0x1A00, 0xFE00, "subs\t%0-2r, %3-5r, %6-8r"},
   {ARM_EXT_V4T, 0x1C00, 0xFE00, "adds\t%0-2r, %3-5r, #%6-8d"},
-  {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"},
+  {ARM_EXT_V4T, 0x1E00, 0xFE00, "subs\t%0-2r, %3-5r, #%6-8d"},
   /* format 8 */
   {ARM_EXT_V4T, 0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"},
   {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"},