* cpu/mep-c5.cpu: New.
* cpu/mep-core.cpu: Add C5 support.
* cpu/mep.opc: Likewise.
[opcodes]
* mep-asm.c: Regenerate.
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
[sid]
* component/cache/cache.cxx (cache_component::cache_component):
Add write_hint_pin(). Attach it to write-hint.
(cache_component::write_hint): New.
* component/cache/cache.h (write_hint_pin): New.
(write_hint): New.
* component/cgen-cpu/mep/Makefile.am: Regenerate.
* component/cgen-cpu/mep/Makefile.in: Regenerate.
* component/cgen-cpu/mep/mep-core1-decode.cxx: Regenerate.
* component/cgen-cpu/mep/mep-core1-decode.h: Regenerate.
* component/cgen-cpu/mep/mep-core1-defs.h: Regenerate.
* component/cgen-cpu/mep/mep-core1-model.cxx: Regenerate.
* component/cgen-cpu/mep/mep-core1-model.h: Regenerate.
* component/cgen-cpu/mep/mep-core1-sem.cxx: Regenerate.
* component/cgen-cpu/mep/mep-decode.cxx: Regenerate.
* component/cgen-cpu/mep/mep-decode.h: Regenerate.
* component/cgen-cpu/mep/mep-defs.h: Regenerate.
* component/cgen-cpu/mep/mep-desc.h: Regenerate.
* component/cgen-cpu/mep/mep-model.cxx: Regenerate.
* component/cgen-cpu/mep/mep-model.h: Regenerate.
* component/cgen-cpu/mep/mep-sem.cxx: Regenerate.
* component/cgen-cpu/mep/mep.cxx (mep_cpu): Connect
write-hint pin.
(do_cache): Add C5 support.
(do_cache_prefetch): Likewise.
(do_casb3, do_cash3, do_casw3): New.
* component/cgen-cpu/mep/mep.h: Add C5 support and write-hint pin.
(do_casb3, do_cash3, do_casw3): New.
* component/families/mep/Makefile.in: Regenerate.
* component/families/mep/dsu.in: Add C5 support.
* main/dynamic/mainDynamic.cxx: Add C5 support.
* main/dynamic/mepCfg.cxx: Connect write-hint pin.
* main/dynamic/mepCfg.h: Add C5 support.
--- /dev/null
+; Insns introduced for the MeP-c5 core
+;
+
+(dnf f-c5n4 "extended field" (all-mep-core-isas) 16 4)
+(dnf f-c5n5 "extended field" (all-mep-core-isas) 20 4)
+(dnf f-c5n6 "extended field" (all-mep-core-isas) 24 4)
+(dnf f-c5n7 "extended field" (all-mep-core-isas) 28 4)
+(dnf f-rl5 "register l c5" (all-mep-core-isas) 20 4)
+(dnf f-12s20 "extended field" (all-mep-core-isas) 20 12)
+
+(dnop rl5 "register Rl c5" (all-mep-core-isas) h-gpr f-rl5)
+(dnop cdisp12 "copro addend (12 bits)" (all-mep-core-isas) h-sint f-12s20)
+
+(dnci stcb_r "store in control bus space" (VOLATILE (MACH c5))
+ "stcb $rn,($rma)"
+ (+ MAJ_7 rn rma (f-sub4 12))
+ (c-call VOID "do_stcb" rn (and rma #xffff))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-stcb))))
+
+(dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3))
+ "ldcb $rn,($rma)"
+ (+ MAJ_7 rn rma (f-sub4 13))
+ (set rn (c-call SI "do_ldcb" (and rma #xffff)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-ldcb)
+ (unit u-exec)
+ (unit u-ldcb-gpr (out loadreg rn)))))
+
+(dnci pref "cache prefetch" ((MACH c5) VOLATILE)
+ "pref $cimm4,($rma)"
+ (+ MAJ_7 cimm4 rma (f-sub4 5))
+ (sequence ()
+ (c-call VOID "check_option_dcache" pc)
+ (c-call VOID "do_cache_prefetch" cimm4 rma pc))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci prefd "cache prefetch" ((MACH c5) VOLATILE)
+ "pref $cimm4,$sdisp16($rma)"
+ (+ MAJ_15 cimm4 rma (f-sub4 3) sdisp16)
+ (sequence ()
+ (c-call VOID "check_option_dcache" pc)
+ (c-call VOID "do_cache_prefetch" cimm4 (add INT rma (ext SI sdisp16)) pc))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+ "casb3 $rl5,$rn,($rm)"
+ (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x0))
+ (sequence ()
+ (c-call VOID "do_casb3" (index-of rl5) rn rm pc)
+ (set rl5 rl5)
+ )
+ ((mep (unit u-use-gpr (in usereg rl5))
+ (unit u-load-gpr (out loadreg rl5))
+ (unit u-exec))))
+
+(dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+ "cash3 $rl5,$rn,($rm)"
+ (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x1))
+ (sequence ()
+ (c-call VOID "do_cash3" (index-of rl5) rn rm pc)
+ (set rl5 rl5)
+ )
+ ((mep (unit u-use-gpr (in usereg rl5))
+ (unit u-load-gpr (out loadreg rl5))
+ (unit u-exec))))
+
+(dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+ "casw3 $rl5,$rn,($rm)"
+ (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x2))
+ (sequence ()
+ (c-call VOID "do_casw3" (index-of rl5) rn rm pc)
+ (set rl5 rl5)
+ )
+ ((mep (unit u-use-gpr (in usereg rl5))
+ (unit u-load-gpr (out loadreg rl5))
+ (unit u-exec))))
+
+
+
+(dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "sbcp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 0) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
+ (set (mem QI (add rma (ext SI cdisp12))) (and crn #xff)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "lbcp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 4) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem QI (add rma (ext SI cdisp12))))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "lbucp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 12) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem QI (add rma (ext SI cdisp12))))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+
+(dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "shcp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 1) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
+ (set (mem HI (add rma (ext SI cdisp12))) (and crn #xffff)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "lhcp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 5) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem HI (add rma (ext SI cdisp12))))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "lhucp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 13) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem HI (add rma (ext SI cdisp12))))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+
+(dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
+ "lbucpa $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xC) (f-ext62 #x0) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem QI rma)))
+ (set rma (add rma cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
+ "lhucpa $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xD) (f-ext62 #x0) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+ (set rma (add rma (ext SI cdisp10a2))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbucpm0 "lbucpm0" (OPTIONAL_CP_INSN (MACH c5))
+ "lbucpm0 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x2) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem QI rma)))
+ (set rma (mod0 cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhucpm0 "lhucpm0" (OPTIONAL_CP_INSN (MACH c5))
+ "lhucpm0 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x2) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+ (set rma (mod0 cdisp10a2)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbucpm1 "lbucpm1" (OPTIONAL_CP_INSN (MACH c5))
+ "lbucpm1 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x3) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem QI rma)))
+ (set rma (mod1 cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhucpm1 "lhucpm1" (OPTIONAL_CP_INSN)
+ "lhucpm1 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x3) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+ (set rma (mod1 cdisp10a2)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci uci "uci" ((MACH c5) VOLATILE)
+ "uci $rn,$rm,$uimm16"
+ (+ MAJ_15 rn rm (f-sub4 2) simm16)
+ (set rn (c-call SI "do_UCI" rn rm (zext SI uimm16) pc))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnf f-c5-rnm "register n/m" (all-mep-isas) 4 8)
+(dnf f-c5-rm "register m" (all-mep-isas) 8 4)
+(df f-c5-16u16 "general 16-bit u-val" (all-mep-isas) 16 16 UINT #f #f)
+
+(dnmf f-c5-rmuimm20 "20-bit immediate in Rm/Imm16" (all-mep-isas) UINT
+ (f-c5-rm f-c5-16u16)
+ (sequence () ; insert
+ (set (ifield f-c5-rm) (srl (ifield f-c5-rmuimm20) 16))
+ (set (ifield f-c5-16u16) (and (ifield f-c5-rmuimm20) #xffff))
+ )
+ (sequence () ; extract
+ (set (ifield f-c5-rmuimm20) (or (ifield f-c5-16u16)
+ (sll (ifield f-c5-rm) 16)))
+ )
+ )
+(dnop c5rmuimm20 "20-bit immediate in rm and imm16" (all-mep-core-isas) h-uint f-c5-rmuimm20)
+
+(dnmf f-c5-rnmuimm24 "24-bit immediate in Rm/Imm16" (all-mep-isas) UINT
+ (f-c5-rnm f-c5-16u16)
+ (sequence () ; insert
+ (set (ifield f-c5-rnm) (srl (ifield f-c5-rnmuimm24) 16))
+ (set (ifield f-c5-16u16) (and (ifield f-c5-rnmuimm24) #xffff))
+ )
+ (sequence () ; extract
+ (set (ifield f-c5-rnmuimm24) (or (ifield f-c5-16u16)
+ (sll (ifield f-c5-rnm) 16)))
+ )
+ )
+(dnop c5rnmuimm24 "24-bit immediate in rn, rm, and imm16" (all-mep-core-isas) h-uint f-c5-rnmuimm24)
+
+(dnci dsp "dsp" ((MACH c5) VOLATILE)
+ "dsp $rn,$rm,$uimm16"
+ (+ MAJ_15 rn rm (f-sub4 0) uimm16)
+ (set rn (c-call SI "do_DSP" rn rm (zext SI uimm16) pc))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dncmi dsp0 "dsp0" ((MACH c5) NO-DIS VOLATILE)
+ "dsp0 $c5rnmuimm24"
+ (emit dsp
+ (rn (sll c5rnmuimm24 20))
+ (rm (and (sll c5rnmuimm24 16) #xf))
+ (uimm16 (and c5rnmuimm24 #xffff)))
+ )
+
+(dncmi dsp1 "dsp1" ((MACH c5) NO-DIS VOLATILE)
+ "dsp1 $rn,$c5rmuimm20"
+ (emit dsp
+ rn
+ (rm (sll c5rnmuimm24 16))
+ (uimm16 (and c5rnmuimm24 #xffff)))
+ )
(name mep)
(comment "Toshiba MeP Media Engine")
(insn-lsb0? #f) ;; work around cgen limitation
- (machs mep h1)
+ (machs mep h1 c5)
isa-enum
)
isa-enum
)
+(define-mach
+ (name c5)
+ (comment "C5 media engine")
+ (cpu mepf)
+ isa-enum
+)
+
(define-model
(name mep)
(comment "MeP media engine processor")
- (mach mep) ; mach gets changed by MeP-Integrator
+ (mach c5) ; mach gets changed by MeP-Integrator
(unit u-exec "execution unit" ()
1 1 ; issue done
(dnf f-sub3 "sub opcode (3 bits)" (all-mep-core-isas) 13 3)
(dnf f-sub4 "sub opcode (4 bits)" (all-mep-core-isas) 12 4)
(dnf f-ext "extended field" (all-mep-core-isas) 16 8)
+(dnf f-ext4 "extended field 16:4" (all-mep-core-isas) 16 4)
+(dnf f-ext62 "extended field 20:2" (all-mep-core-isas) 20 2)
(dnf f-crn "copro register n" (all-mep-core-isas) 4 4)
(df f-csrn-hi "cr hi 1u15" (all-mep-core-isas) 15 1 UINT #f #f)
; These are all for the coprocessor opcodes
-(df f-8s24 "copro b-offset (8 bits)" (all-mep-core-isas) 24 8 INT #f #f)
-(df f-8s24a2 "copro h-offset (8 bits)" (all-mep-core-isas) 24 7 INT
- ((value pc) (sra SI value 1))
- ((value pc) (sll SI value 1)))
-(df f-8s24a4 "copro w-offset (8 bits)" (all-mep-core-isas) 24 6 INT
- ((value pc) (sra SI value 2))
- ((value pc) (sll SI value 2)))
-(df f-8s24a8 "copro m-offset (8 bits)" (all-mep-core-isas) 24 5 INT
- ((value pc) (sra SI value 3))
- ((value pc) (sll SI value 3)))
+; The field is like IJKiiiiiii where I and J are toggled if K is set,
+; for compatibility with older cores.
+(define-pmacro (compute-cdisp10 val)
+ (cond SI
+ ((and SI (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x200)
+ (sub (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x400))
+ (else
+ (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)))
+ )
+ )
+
+(df f-cdisp10 "cop imm10" (all-mep-core-isas) 22 10 UINT
+ ((value pc) (compute-cdisp10 value))
+ ((value pc) (compute-cdisp10 value))
+ )
; Non-contiguous fields.
(dnop cimm4 "cache immed'te (4 bits)" (all-mep-core-isas) h-uint f-rn)
(dnop cimm5 "clip immediate (5 bits)" (all-mep-core-isas) h-uint f-5u24)
-(dnop cdisp8 "copro addend (8 bits)" (all-mep-core-isas) h-sint f-8s24)
-(dpop cdisp8a2 "copro addend (8 bits)" (all-mep-core-isas (ALIGN 2)) h-sint f-8s24a2 "mep_align")
-(dpop cdisp8a4 "copro addend (8 bits)" (all-mep-core-isas (ALIGN 4)) h-sint f-8s24a4 "mep_align")
-(dpop cdisp8a8 "copro addend (8 bits)" (all-mep-core-isas (ALIGN 8)) h-sint f-8s24a8 "mep_align")
+
+(dpop cdisp10 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
+(dpop cdisp10a2 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
+(dpop cdisp10a4 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
+(dpop cdisp10a8 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
; Special operand representing the various ways that the literal zero can be
; specified.
\f
+; pmacros needed for coprocessor modulo addressing.
+
+; Taken from supplement ``The operation of the modulo addressing'' in
+; Toshiba documentation rev 2.2, p. 34.
+
+(define-pmacro (compute-mask0)
+ (sequence SI ((SI temp))
+ (set temp (or mb0 me0))
+ (srl (const SI -1) (c-call SI "do_ldz" temp))))
+
+(define-pmacro (mod0 immed)
+ (sequence SI ((SI modulo-mask))
+ (set modulo-mask (compute-mask0))
+ (if SI (eq (and rma modulo-mask) me0)
+ (or (and rma (inv modulo-mask)) mb0)
+ (add rma (ext SI immed)))))
+
+(define-pmacro (compute-mask1)
+ (sequence SI ((SI temp))
+ (set temp (or mb1 me1))
+ (srl (const SI -1) (c-call SI "do_ldz" temp))))
+
+(define-pmacro (mod1 immed)
+ (sequence SI ((SI modulo-mask))
+ (set modulo-mask (compute-mask1))
+ (if SI (eq (and rma modulo-mask) me1)
+ (or (and rma (inv modulo-mask)) mb1)
+ (add rma (ext SI immed)))))
+
+\f
; Instructions.
; A pmacro for use in semantic bodies of unimplemented insns.
; Core specific instructions
; (include "mep-h1.cpu") ; -- exposed by MeP-Integrator
+(include "mep-c5.cpu") ; -- exposed by MeP-Integrator
; Load/store instructions.
(unit u-exec))))
(dnci sbcpa "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
- "sbcpa $crn,($rma+),$cdisp8"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext 0) cdisp8)
+ "sbcpa $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 0) (f-ext62 0) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" rma)
(set (mem QI rma) (and crn #xff))
- (set rma (add rma (ext SI cdisp8))))
+ (set rma (add rma (ext SI cdisp10))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
- "lbcpa $crn,($rma+),$cdisp8"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x40) cdisp8)
+ "lbcpa $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x0) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI rma)))
- (set rma (add rma (ext SI cdisp8))))
+ (set rma (add rma (ext SI cdisp10))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcpa "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
- "shcpa $crn,($rma+),$cdisp8a2"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x10) cdisp8a2 (f-31 0))
+ "shcpa $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x0) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 1)))
(set (mem HI (and rma (inv SI 1))) (and crn #xffff))
- (set rma (add rma (ext SI cdisp8a2))))
+ (set rma (add rma (ext SI cdisp10a2))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
- "lhcpa $crn,($rma+),$cdisp8a2"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x50) cdisp8a2 (f-31 0))
+ "lhcpa $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x0) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (and rma (inv SI 1)))))
- (set rma (add rma (ext SI cdisp8a2))))
+ (set rma (add rma (ext SI cdisp10a2))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpa "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
- "swcpa $crn,($rma+),$cdisp8a4"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x20) cdisp8a4 (f-30 0) (f-31 0))
+ "swcpa $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x0) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
- (set rma (add rma (ext SI cdisp8a4))))
+ (set rma (add rma (ext SI cdisp10a4))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpa "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
- "lwcpa $crn,($rma+),$cdisp8a4"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x60) cdisp8a4 (f-30 0) (f-31 0))
+ "lwcpa $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x0) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and rma (inv SI 3))))
- (set rma (add rma (ext SI cdisp8a4))))
+ (set rma (add rma (ext SI cdisp10a4))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpa "smcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
- "smcpa $crn64,($rma+),$cdisp8a8"
- (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x30) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
+ "smcpa $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x0) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call VOID "check_write_to_text" rma)
- (c-call "do_smcpa" (index-of rma) cdisp8a8 crn64 pc)
+ (c-call "do_smcpa" (index-of rma) cdisp10a8 crn64 pc)
(set rma rma)) ; reference as output for intrinsic generation
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpa "lmcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
- "lmcpa $crn64,($rma+),$cdisp8a8"
- (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x70) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
+ "lmcpa $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x0) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
- (set crn64 (c-call DI "do_lmcpa" (index-of rma) cdisp8a8 pc))
+ (set crn64 (c-call DI "do_lmcpa" (index-of rma) cdisp10a8 pc))
(set rma rma)) ; reference as output for intrinsic generation
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
\f
-; pmacros needed for coprocessor modulo addressing.
-
-; Taken from supplement ``The operation of the modulo addressing'' in
-; Toshiba documentation rev 2.2, p. 34.
-
-(define-pmacro (compute-mask0)
- (sequence SI ((SI temp))
- (set temp (or mb0 me0))
- (srl (const SI -1) (c-call SI "do_ldz" temp))))
-
-(define-pmacro (mod0 immed)
- (sequence SI ((SI modulo-mask))
- (set modulo-mask (compute-mask0))
- (if SI (eq (and rma modulo-mask) me0)
- (or (and rma (inv modulo-mask)) mb0)
- (add rma (ext SI immed)))))
-
-(define-pmacro (compute-mask1)
- (sequence SI ((SI temp))
- (set temp (or mb1 me1))
- (srl (const SI -1) (c-call SI "do_ldz" temp))))
-
-(define-pmacro (mod1 immed)
- (sequence SI ((SI modulo-mask))
- (set modulo-mask (compute-mask1))
- (if SI (eq (and rma modulo-mask) me1)
- (or (and rma (inv modulo-mask)) mb1)
- (add rma (ext SI immed)))))
-
(dnci sbcpm0 "sbcpm0" (OPTIONAL_CP_INSN)
- "sbcpm0 $crn,($rma+),$cdisp8"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x08) cdisp8)
+ "sbcpm0 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x2) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" rma)
(set (mem QI rma) (and crn #xff))
- (set rma (mod0 cdisp8)))
+ (set rma (mod0 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcpm0 "lbcpm0" (OPTIONAL_CP_INSN)
- "lbcpm0 $crn,($rma+),$cdisp8"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x48) cdisp8)
+ "lbcpm0 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x2) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI rma)))
- (set rma (mod0 cdisp8)))
+ (set rma (mod0 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcpm0 "shcpm0" (OPTIONAL_CP_INSN)
- "shcpm0 $crn,($rma+),$cdisp8a2"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x18) cdisp8a2 (f-31 0))
+ "shcpm0 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x2) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 1)))
(set (mem HI (and rma (inv SI 1))) (and crn #xffff))
- (set rma (mod0 cdisp8a2)))
+ (set rma (mod0 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcpm0 "lhcpm0" (OPTIONAL_CP_INSN)
- "lhcpm0 $crn,($rma+),$cdisp8a2"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x58) cdisp8a2 (f-31 0))
+ "lhcpm0 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x2) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (and rma (inv SI 1)))))
- (set rma (mod0 cdisp8a2)))
+ (set rma (mod0 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpm0 "swcpm0" (OPTIONAL_CP_INSN)
- "swcpm0 $crn,($rma+),$cdisp8a4"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x28) cdisp8a4 (f-30 0) (f-31 0))
+ "swcpm0 $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x2) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
- (set rma (mod0 cdisp8a4)))
+ (set rma (mod0 cdisp10a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpm0 "lwcpm0" (OPTIONAL_CP_INSN)
- "lwcpm0 $crn,($rma+),$cdisp8a4"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x68) cdisp8a4 (f-30 0) (f-31 0))
+ "lwcpm0 $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x2) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and rma (inv SI 3))))
- (set rma (mod0 cdisp8a4)))
+ (set rma (mod0 cdisp10a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpm0 "smcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
- "smcpm0 $crn64,($rma+),$cdisp8a8"
- (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x38) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
+ "smcpm0 $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x2) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call VOID "check_write_to_text" rma)
(c-call "do_smcp" rma crn64 pc)
- (set rma (mod0 cdisp8a8)))
+ (set rma (mod0 cdisp10a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpm0 "lmcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
- "lmcpm0 $crn64,($rma+),$cdisp8a8"
- (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x78) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
+ "lmcpm0 $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x2) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcp" rma pc))
- (set rma (mod0 cdisp8a8)))
+ (set rma (mod0 cdisp10a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sbcpm1 "sbcpm1" (OPTIONAL_CP_INSN)
- "sbcpm1 $crn,($rma+),$cdisp8"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x0c) cdisp8)
+ "sbcpm1 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x3) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" rma)
(set (mem QI rma) (and crn #xff))
- (set rma (mod1 cdisp8)))
+ (set rma (mod1 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcpm1 "lbcpm1" (OPTIONAL_CP_INSN)
- "lbcpm1 $crn,($rma+),$cdisp8"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x4c) cdisp8)
+ "lbcpm1 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x3) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI rma)))
- (set rma (mod1 cdisp8)))
+ (set rma (mod1 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcpm1 "shcpm1" (OPTIONAL_CP_INSN)
- "shcpm1 $crn,($rma+),$cdisp8a2"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x1c) cdisp8a2 (f-31 0))
+ "shcpm1 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x3) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 1)))
(set (mem HI (and rma (inv SI 1))) (and crn #xffff))
- (set rma (mod1 cdisp8a2)))
+ (set rma (mod1 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcpm1 "lhcpm1" (OPTIONAL_CP_INSN)
- "lhcpm1 $crn,($rma+),$cdisp8a2"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x5c) cdisp8a2 (f-31 0))
+ "lhcpm1 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x3) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (and rma (inv SI 1)))))
- (set rma (mod1 cdisp8a2)))
+ (set rma (mod1 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpm1 "swcpm1" (OPTIONAL_CP_INSN)
- "swcpm1 $crn,($rma+),$cdisp8a4"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x2c) cdisp8a4 (f-30 0) (f-31 0))
+ "swcpm1 $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x3) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
- (set rma (mod1 cdisp8a4)))
+ (set rma (mod1 cdisp10a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpm1 "lwcpm1" (OPTIONAL_CP_INSN)
- "lwcpm1 $crn,($rma+),$cdisp8a4"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x6c) cdisp8a4 (f-30 0) (f-31 0))
+ "lwcpm1 $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x3) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem SI (and rma (inv SI 3)))))
- (set rma (mod1 cdisp8a4)))
+ (set rma (mod1 cdisp10a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpm1 "smcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
- "smcpm1 $crn64,($rma+),$cdisp8a8"
- (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x3c) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
+ "smcpm1 $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x3) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call "do_smcp" rma crn64 pc)
(c-call VOID "check_write_to_text" rma)
- (set rma (mod1 cdisp8a8)))
+ (set rma (mod1 cdisp10a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpm1 "lmcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
- "lmcpm1 $crn64,($rma+),$cdisp8a8"
- (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x7c) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
+ "lmcpm1 $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x3) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcp" rma pc))
- (set rma (mod1 cdisp8a8)))
+ (set rma (mod1 cdisp10a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnri 21 MAJ_7 15)
(dnri 22 MAJ_12 7)
(dnri 23 MAJ_14 13)
-(dnri 24 MAJ_15 3)
-(dnri 25 MAJ_15 6)
+;(dnri 24 MAJ_15 3)
(dnri 26 MAJ_15 8)
-; begin non-mep-h1 reserved insns
-(dnri 16 MAJ_7 5)
-(dnri 18 MAJ_7 12)
-(dnri 19 MAJ_7 13)
-; end non-mep-h1 reserved insns
+; begin core-specific reserved insns
+; end core-specific reserved insns
\f
; Macro instructions.
/* -- asm.c */
+#include "elf/mep.h"
+
#define CGEN_VALIDATE_INSN_SUPPORTED
const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
case MEP_OPERAND_PCREL12A2:
case MEP_OPERAND_PCREL17A2:
case MEP_OPERAND_PCREL24A2:
- case MEP_OPERAND_CDISP8A2:
- case MEP_OPERAND_CDISP8A4:
- case MEP_OPERAND_CDISP8A8:
err = cgen_parse_signed_integer (cd, strp, type, field);
break;
case MEP_OPERAND_PCABS24A2:
case MEP_OPERAND_PCREL24A2:
case MEP_OPERAND_PCABS24A2:
case MEP_OPERAND_UDISP7A2:
- case MEP_OPERAND_CDISP8A2:
lsbs = *field & 1;
break;
case MEP_OPERAND_UDISP7A4:
case MEP_OPERAND_UIMM7A4:
case MEP_OPERAND_ADDR24A4:
- case MEP_OPERAND_CDISP8A4:
lsbs = *field & 3;
break;
- case MEP_OPERAND_CDISP8A8:
lsbs = *field & 7;
break;
default:
return parse_mep_alignu (cd, strp, opindex, valuep);
}
+static ATTRIBUTE_UNUSED const char *
+parse_cdisp10 (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ long *valuep)
+{
+ const char *errmsg = 0;
+ signed long value;
+ long have_zero = 0;
+ int wide = 0;
+ int alignment;
+
+ switch (opindex)
+ {
+ case MEP_OPERAND_CDISP10A4:
+ alignment = 2;
+ break;
+ case MEP_OPERAND_CDISP10A2:
+ alignment = 1;
+ break;
+ case MEP_OPERAND_CDISP10:
+ default:
+ alignment = 0;
+ break;
+ }
+
+ if (MEP_CPU == EF_MEP_CPU_C5)
+ wide = 1;
+
+ if (strncmp (*strp, "0x0", 3) == 0
+ || (**strp == '0' && *(*strp + 1) != 'x'))
+ have_zero = 1;
+
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+ if (errmsg)
+ return errmsg;
+
+ if (wide)
+ {
+ if (value < -512 || value > 511)
+ return _("Immediate is out of range -512 to 511");
+ }
+ else
+ {
+ if (value < -128 || value > 127)
+ return _("Immediate is out of range -128 to 127");
+ }
+
+ if (value & ((1<<alignment)-1))
+ return _("Value is not aligned enough");
+
+ /* If this field may require a relocation then use larger dsp16. */
+ if (! have_zero && value == 0)
+ return (wide ? _("Immediate is out of range -512 to 511")
+ : _("Immediate is out of range -128 to 127"));
+
+ *valuep = value;
+ return 0;
+}
+
/* BEGIN LIGHTWEIGHT MACRO PROCESSOR. */
#define MAXARGS 9
{
/* config-map-start */
/* Default entry: mep core only, all options enabled. */
- { "", 0, EF_MEP_CPU_C4, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
- { "default", CONFIG_DEFAULT, EF_MEP_CPU_C4, 0, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
+ { "", 0, EF_MEP_CPU_C5, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
+ { "default", CONFIG_DEFAULT, EF_MEP_CPU_C5, 0, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
0
| (1 << CGEN_INSN_OPTIONAL_MUL_INSN)
| (1 << CGEN_INSN_OPTIONAL_DIV_INSN)
case EF_MEP_CPU_H1:
mach |= (1 << MACH_H1);
break;
+ case EF_MEP_CPU_C5:
+ mach |= (1 << MACH_MEP);
+ mach |= (1 << MACH_C5);
+ break;
default:
break;
}
/* -- asm.c */
+#include "elf/mep.h"
+
#define CGEN_VALIDATE_INSN_SUPPORTED
const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
case MEP_OPERAND_PCREL12A2:
case MEP_OPERAND_PCREL17A2:
case MEP_OPERAND_PCREL24A2:
- case MEP_OPERAND_CDISP8A2:
- case MEP_OPERAND_CDISP8A4:
- case MEP_OPERAND_CDISP8A8:
err = cgen_parse_signed_integer (cd, strp, type, field);
break;
case MEP_OPERAND_PCABS24A2:
case MEP_OPERAND_PCREL24A2:
case MEP_OPERAND_PCABS24A2:
case MEP_OPERAND_UDISP7A2:
- case MEP_OPERAND_CDISP8A2:
lsbs = *field & 1;
break;
case MEP_OPERAND_UDISP7A4:
case MEP_OPERAND_UIMM7A4:
case MEP_OPERAND_ADDR24A4:
- case MEP_OPERAND_CDISP8A4:
lsbs = *field & 3;
break;
- case MEP_OPERAND_CDISP8A8:
lsbs = *field & 7;
break;
default:
return parse_mep_alignu (cd, strp, opindex, valuep);
}
+static ATTRIBUTE_UNUSED const char *
+parse_cdisp10 (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ long *valuep)
+{
+ const char *errmsg = 0;
+ signed long value;
+ long have_zero = 0;
+ int wide = 0;
+ int alignment;
+
+ switch (opindex)
+ {
+ case MEP_OPERAND_CDISP10A4:
+ alignment = 2;
+ break;
+ case MEP_OPERAND_CDISP10A2:
+ alignment = 1;
+ break;
+ case MEP_OPERAND_CDISP10:
+ default:
+ alignment = 0;
+ break;
+ }
+
+ if (MEP_CPU == EF_MEP_CPU_C5)
+ wide = 1;
+
+ if (strncmp (*strp, "0x0", 3) == 0
+ || (**strp == '0' && *(*strp + 1) != 'x'))
+ have_zero = 1;
+
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+ if (errmsg)
+ return errmsg;
+
+ if (wide)
+ {
+ if (value < -512 || value > 511)
+ return _("Immediate is out of range -512 to 511");
+ }
+ else
+ {
+ if (value < -128 || value > 127)
+ return _("Immediate is out of range -128 to 127");
+ }
+
+ if (value & ((1<<alignment)-1))
+ return _("Value is not aligned enough");
+
+ /* If this field may require a relocation then use larger dsp16. */
+ if (! have_zero && value == 0)
+ return (wide ? _("Immediate is out of range -512 to 511")
+ : _("Immediate is out of range -128 to 127"));
+
+ *valuep = value;
+ return 0;
+}
+
/* BEGIN LIGHTWEIGHT MACRO PROCESSOR. */
#define MAXARGS 9
case MEP_OPERAND_ADDR24A4 :
errmsg = parse_mep_alignu (cd, strp, MEP_OPERAND_ADDR24A4, (unsigned long *) (& fields->f_24u8a4n));
break;
+ case MEP_OPERAND_C5RMUIMM20 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_C5RMUIMM20, (unsigned long *) (& fields->f_c5_rmuimm20));
+ break;
+ case MEP_OPERAND_C5RNMUIMM24 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_C5RNMUIMM24, (unsigned long *) (& fields->f_c5_rnmuimm24));
+ break;
case MEP_OPERAND_CALLNUM :
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CALLNUM, (unsigned long *) (& fields->f_callnum));
break;
case MEP_OPERAND_CCRN :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr, & fields->f_ccrn);
break;
- case MEP_OPERAND_CDISP8 :
- errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_CDISP8, (long *) (& fields->f_8s24));
+ case MEP_OPERAND_CDISP10 :
+ errmsg = parse_cdisp10 (cd, strp, MEP_OPERAND_CDISP10, (long *) (& fields->f_cdisp10));
+ break;
+ case MEP_OPERAND_CDISP10A2 :
+ errmsg = parse_cdisp10 (cd, strp, MEP_OPERAND_CDISP10A2, (long *) (& fields->f_cdisp10));
break;
- case MEP_OPERAND_CDISP8A2 :
- errmsg = parse_mep_align (cd, strp, MEP_OPERAND_CDISP8A2, (long *) (& fields->f_8s24a2));
+ case MEP_OPERAND_CDISP10A4 :
+ errmsg = parse_cdisp10 (cd, strp, MEP_OPERAND_CDISP10A4, (long *) (& fields->f_cdisp10));
break;
- case MEP_OPERAND_CDISP8A4 :
- errmsg = parse_mep_align (cd, strp, MEP_OPERAND_CDISP8A4, (long *) (& fields->f_8s24a4));
+ case MEP_OPERAND_CDISP10A8 :
+ errmsg = parse_cdisp10 (cd, strp, MEP_OPERAND_CDISP10A8, (long *) (& fields->f_cdisp10));
break;
- case MEP_OPERAND_CDISP8A8 :
- errmsg = parse_mep_align (cd, strp, MEP_OPERAND_CDISP8A8, (long *) (& fields->f_8s24a8));
+ case MEP_OPERAND_CDISP12 :
+ errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_CDISP12, (long *) (& fields->f_12s20));
break;
case MEP_OPERAND_CIMM4 :
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CIMM4, (unsigned long *) (& fields->f_rn));
case MEP_OPERAND_RL :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rl);
break;
+ case MEP_OPERAND_RL5 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rl5);
+ break;
case MEP_OPERAND_RM :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rm);
break;
{ "base", MACH_BASE },
{ "mep", MACH_MEP },
{ "h1", MACH_H1 },
+ { "c5", MACH_C5 },
{ "max", MACH_MAX },
{ 0, 0 }
};
static const CGEN_MACH mep_cgen_mach_table[] = {
{ "mep", "mep", MACH_MEP, 16 },
{ "h1", "h1", MACH_H1, 16 },
+ { "c5", "c5", MACH_C5, 16 },
{ 0, 0, 0, 0 }
};
{ MEP_F_SUB3, "f-sub3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_SUB4, "f-sub4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_EXT, "f-ext", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_EXT4, "f-ext4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_EXT62, "f-ext62", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_CRN, "f-crn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_CSRN_HI, "f-csrn-hi", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_CSRN_LO, "f-csrn-lo", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_16U16, "f-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_12U16, "f-12u16", 0, 32, 16, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_3U29, "f-3u29", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
- { MEP_F_8S24, "f-8s24", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
- { MEP_F_8S24A2, "f-8s24a2", 0, 32, 24, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
- { MEP_F_8S24A4, "f-8s24a4", 0, 32, 24, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
- { MEP_F_8S24A8, "f-8s24a8", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_CDISP10, "f-cdisp10", 0, 32, 22, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_24U8A4N_HI, "f-24u8a4n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_24U8A4N_LO, "f-24u8a4n-lo", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_24U8A4N, "f-24u8a4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_CCRN_HI, "f-ccrn-hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_CCRN_LO, "f-ccrn-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ MEP_F_CCRN, "f-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_C5N4, "f-c5n4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_C5N5, "f-c5n5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_C5N6, "f-c5n6", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_C5N7, "f-c5n7", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_RL5, "f-rl5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_12S20, "f-12s20", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_C5_RNM, "f-c5-rnm", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_C5_RM, "f-c5-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_C5_16U16, "f-c5-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_C5_RMUIMM20, "f-c5-rmuimm20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { MEP_F_C5_RNMUIMM24, "f-c5-rnmuimm24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [];
/* multi ifield definitions */
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_LO] } },
{ 0, { (const PTR) 0 } }
};
+const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RM] } },
+ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
+ { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RNM] } },
+ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
+ { 0, { (const PTR) 0 } }
+};
/* The operand table. */
{ "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
-/* cdisp8: copro addend (8 bits) */
- { "cdisp8", MEP_OPERAND_CDISP8, HW_H_SINT, 24, 8,
- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24] } },
+/* cdisp10: comment */
+ { "cdisp10", MEP_OPERAND_CDISP10, HW_H_SINT, 22, 10,
+ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* cdisp10a2: comment */
+ { "cdisp10a2", MEP_OPERAND_CDISP10A2, HW_H_SINT, 22, 10,
+ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* cdisp10a4: comment */
+ { "cdisp10a4", MEP_OPERAND_CDISP10A4, HW_H_SINT, 22, 10,
+ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* cdisp10a8: comment */
+ { "cdisp10a8", MEP_OPERAND_CDISP10A8, HW_H_SINT, 22, 10,
+ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
-/* cdisp8a2: comment */
- { "cdisp8a2", MEP_OPERAND_CDISP8A2, HW_H_SINT, 24, 7,
- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A2] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } } },
-/* cdisp8a4: comment */
- { "cdisp8a4", MEP_OPERAND_CDISP8A4, HW_H_SINT, 24, 6,
- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A4] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
-/* cdisp8a8: comment */
- { "cdisp8a8", MEP_OPERAND_CDISP8A8, HW_H_SINT, 24, 5,
- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A8] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 8, 0 } } } } },
/* zero: Zero operand */
{ "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* rl5: register Rl c5 */
+ { "rl5", MEP_OPERAND_RL5, HW_H_GPR, 20, 4,
+ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL5] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* cdisp12: copro addend (12 bits) */
+ { "cdisp12", MEP_OPERAND_CDISP12, HW_H_SINT, 20, 12,
+ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S20] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* c5rmuimm20: 20-bit immediate in rm and imm16 */
+ { "c5rmuimm20", MEP_OPERAND_C5RMUIMM20, HW_H_UINT, 8, 20,
+ { 2, { (const PTR) &MEP_F_C5_RMUIMM20_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* c5rnmuimm24: 24-bit immediate in rn, rm, and imm16 */
+ { "c5rnmuimm24", MEP_OPERAND_C5RNMUIMM24, HW_H_UINT, 4, 24,
+ { 2, { (const PTR) &MEP_F_C5_RNMUIMM24_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cp_flag: branch condition register */
{ "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
{ 0, { (const PTR) 0 } },
A `num' value of zero is thus invalid.
Also, the special `invalid' insn resides here. */
{ 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } },
+/* stcb $rn,($rma) */
+ {
+ MEP_INSN_STCB_R, "stcb_r", "stcb", 16,
+ { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* ldcb $rn,($rma) */
+ {
+ MEP_INSN_LDCB_R, "ldcb_r", "ldcb", 16,
+ { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* pref $cimm4,($rma) */
+ {
+ MEP_INSN_PREF, "pref", "pref", 16,
+ { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* pref $cimm4,$sdisp16($rma) */
+ {
+ MEP_INSN_PREFD, "prefd", "pref", 32,
+ { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* casb3 $rl5,$rn,($rm) */
+ {
+ MEP_INSN_CASB3, "casb3", "casb3", 32,
+ { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* cash3 $rl5,$rn,($rm) */
+ {
+ MEP_INSN_CASH3, "cash3", "cash3", 32,
+ { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* casw3 $rl5,$rn,($rm) */
+ {
+ MEP_INSN_CASW3, "casw3", "casw3", 32,
+ { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* sbcp $crn,$cdisp12($rma) */
+ {
+ MEP_INSN_SBCP, "sbcp", "sbcp", 32,
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* lbcp $crn,$cdisp12($rma) */
+ {
+ MEP_INSN_LBCP, "lbcp", "lbcp", 32,
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* lbucp $crn,$cdisp12($rma) */
+ {
+ MEP_INSN_LBUCP, "lbucp", "lbucp", 32,
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* shcp $crn,$cdisp12($rma) */
+ {
+ MEP_INSN_SHCP, "shcp", "shcp", 32,
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* lhcp $crn,$cdisp12($rma) */
+ {
+ MEP_INSN_LHCP, "lhcp", "lhcp", 32,
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* lhucp $crn,$cdisp12($rma) */
+ {
+ MEP_INSN_LHUCP, "lhucp", "lhucp", 32,
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* lbucpa $crn,($rma+),$cdisp10 */
+ {
+ MEP_INSN_LBUCPA, "lbucpa", "lbucpa", 32,
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* lhucpa $crn,($rma+),$cdisp10a2 */
+ {
+ MEP_INSN_LHUCPA, "lhucpa", "lhucpa", 32,
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* lbucpm0 $crn,($rma+),$cdisp10 */
+ {
+ MEP_INSN_LBUCPM0, "lbucpm0", "lbucpm0", 32,
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* lhucpm0 $crn,($rma+),$cdisp10a2 */
+ {
+ MEP_INSN_LHUCPM0, "lhucpm0", "lhucpm0", 32,
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* lbucpm1 $crn,($rma+),$cdisp10 */
+ {
+ MEP_INSN_LBUCPM1, "lbucpm1", "lbucpm1", 32,
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* lhucpm1 $crn,($rma+),$cdisp10a2 */
+ {
+ MEP_INSN_LHUCPM1, "lhucpm1", "lhucpm1", 32,
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* uci $rn,$rm,$uimm16 */
+ {
+ MEP_INSN_UCI, "uci", "uci", 32,
+ { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* dsp $rn,$rm,$uimm16 */
+ {
+ MEP_INSN_DSP, "dsp", "dsp", 32,
+ { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
/* sb $rnc,($rma) */
{
MEP_INSN_SB, "sb", "sb", 16,
MEP_INSN_LMCP16, "lmcp16", "lmcp", 32,
{ 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* sbcpa $crn,($rma+),$cdisp8 */
+/* sbcpa $crn,($rma+),$cdisp10 */
{
MEP_INSN_SBCPA, "sbcpa", "sbcpa", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* lbcpa $crn,($rma+),$cdisp8 */
+/* lbcpa $crn,($rma+),$cdisp10 */
{
MEP_INSN_LBCPA, "lbcpa", "lbcpa", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* shcpa $crn,($rma+),$cdisp8a2 */
+/* shcpa $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_SHCPA, "shcpa", "shcpa", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* lhcpa $crn,($rma+),$cdisp8a2 */
+/* lhcpa $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_LHCPA, "lhcpa", "lhcpa", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* swcpa $crn,($rma+),$cdisp8a4 */
+/* swcpa $crn,($rma+),$cdisp10a4 */
{
MEP_INSN_SWCPA, "swcpa", "swcpa", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* lwcpa $crn,($rma+),$cdisp8a4 */
+/* lwcpa $crn,($rma+),$cdisp10a4 */
{
MEP_INSN_LWCPA, "lwcpa", "lwcpa", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* smcpa $crn64,($rma+),$cdisp8a8 */
+/* smcpa $crn64,($rma+),$cdisp10a8 */
{
MEP_INSN_SMCPA, "smcpa", "smcpa", 32,
{ 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* lmcpa $crn64,($rma+),$cdisp8a8 */
+/* lmcpa $crn64,($rma+),$cdisp10a8 */
{
MEP_INSN_LMCPA, "lmcpa", "lmcpa", 32,
{ 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* sbcpm0 $crn,($rma+),$cdisp8 */
+/* sbcpm0 $crn,($rma+),$cdisp10 */
{
MEP_INSN_SBCPM0, "sbcpm0", "sbcpm0", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* lbcpm0 $crn,($rma+),$cdisp8 */
+/* lbcpm0 $crn,($rma+),$cdisp10 */
{
MEP_INSN_LBCPM0, "lbcpm0", "lbcpm0", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* shcpm0 $crn,($rma+),$cdisp8a2 */
+/* shcpm0 $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_SHCPM0, "shcpm0", "shcpm0", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* lhcpm0 $crn,($rma+),$cdisp8a2 */
+/* lhcpm0 $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_LHCPM0, "lhcpm0", "lhcpm0", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* swcpm0 $crn,($rma+),$cdisp8a4 */
+/* swcpm0 $crn,($rma+),$cdisp10a4 */
{
MEP_INSN_SWCPM0, "swcpm0", "swcpm0", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* lwcpm0 $crn,($rma+),$cdisp8a4 */
+/* lwcpm0 $crn,($rma+),$cdisp10a4 */
{
MEP_INSN_LWCPM0, "lwcpm0", "lwcpm0", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* smcpm0 $crn64,($rma+),$cdisp8a8 */
+/* smcpm0 $crn64,($rma+),$cdisp10a8 */
{
MEP_INSN_SMCPM0, "smcpm0", "smcpm0", 32,
{ 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* lmcpm0 $crn64,($rma+),$cdisp8a8 */
+/* lmcpm0 $crn64,($rma+),$cdisp10a8 */
{
MEP_INSN_LMCPM0, "lmcpm0", "lmcpm0", 32,
{ 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* sbcpm1 $crn,($rma+),$cdisp8 */
+/* sbcpm1 $crn,($rma+),$cdisp10 */
{
MEP_INSN_SBCPM1, "sbcpm1", "sbcpm1", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* lbcpm1 $crn,($rma+),$cdisp8 */
+/* lbcpm1 $crn,($rma+),$cdisp10 */
{
MEP_INSN_LBCPM1, "lbcpm1", "lbcpm1", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* shcpm1 $crn,($rma+),$cdisp8a2 */
+/* shcpm1 $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_SHCPM1, "shcpm1", "shcpm1", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* lhcpm1 $crn,($rma+),$cdisp8a2 */
+/* lhcpm1 $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_LHCPM1, "lhcpm1", "lhcpm1", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* swcpm1 $crn,($rma+),$cdisp8a4 */
+/* swcpm1 $crn,($rma+),$cdisp10a4 */
{
MEP_INSN_SWCPM1, "swcpm1", "swcpm1", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* lwcpm1 $crn,($rma+),$cdisp8a4 */
+/* lwcpm1 $crn,($rma+),$cdisp10a4 */
{
MEP_INSN_LWCPM1, "lwcpm1", "lwcpm1", 32,
{ 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* smcpm1 $crn64,($rma+),$cdisp8a8 */
+/* smcpm1 $crn64,($rma+),$cdisp10a8 */
{
MEP_INSN_SMCPM1, "smcpm1", "smcpm1", 32,
{ 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* lmcpm1 $crn64,($rma+),$cdisp8a8 */
+/* lmcpm1 $crn64,($rma+),$cdisp10a8 */
{
MEP_INSN_LMCPM1, "lmcpm1", "lmcpm1", 32,
{ 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
/* --reserved-- */
{
- MEP_INSN_RI_24, "ri-24", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
- },
-/* --reserved-- */
- {
- MEP_INSN_RI_25, "ri-25", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
- },
-/* --reserved-- */
- {
MEP_INSN_RI_26, "ri-26", "--reserved--", 16,
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
-/* --reserved-- */
- {
- MEP_INSN_RI_16, "ri-16", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
- },
-/* --reserved-- */
- {
- MEP_INSN_RI_18, "ri-18", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
- },
-/* --reserved-- */
- {
- MEP_INSN_RI_19, "ri-19", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
- },
};
#undef OP
#define CGEN_INT_INSN_P 1
/* Maximum number of syntax elements in an instruction. */
-#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 17
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 18
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
- MACH_BASE, MACH_MEP, MACH_H1, MACH_MAX
+ MACH_BASE, MACH_MEP, MACH_H1, MACH_C5
+ , MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
typedef enum ifield_type {
MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN
, MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2
- , MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_CRN
- , MEP_F_CSRN_HI, MEP_F_CSRN_LO, MEP_F_CSRN, MEP_F_CRNX_HI
- , MEP_F_CRNX_LO, MEP_F_CRNX, MEP_F_0, MEP_F_1
- , MEP_F_2, MEP_F_3, MEP_F_4, MEP_F_5
- , MEP_F_6, MEP_F_7, MEP_F_8, MEP_F_9
- , MEP_F_10, MEP_F_11, MEP_F_12, MEP_F_13
- , MEP_F_14, MEP_F_15, MEP_F_16, MEP_F_17
- , MEP_F_18, MEP_F_19, MEP_F_20, MEP_F_21
- , MEP_F_22, MEP_F_23, MEP_F_24, MEP_F_25
- , MEP_F_26, MEP_F_27, MEP_F_28, MEP_F_29
- , MEP_F_30, MEP_F_31, MEP_F_8S8A2, MEP_F_12S4A2
- , MEP_F_17S16A2, MEP_F_24S5A2N_HI, MEP_F_24S5A2N_LO, MEP_F_24S5A2N
- , MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO, MEP_F_24U5A2N, MEP_F_2U6
- , MEP_F_7U9, MEP_F_7U9A2, MEP_F_7U9A4, MEP_F_16S16
- , MEP_F_2U10, MEP_F_3U5, MEP_F_4U8, MEP_F_5U8
- , MEP_F_5U24, MEP_F_6S8, MEP_F_8S8, MEP_F_16U16
- , MEP_F_12U16, MEP_F_3U29, MEP_F_8S24, MEP_F_8S24A2
- , MEP_F_8S24A4, MEP_F_8S24A8, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO
- , MEP_F_24U8A4N, MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N
- , MEP_F_24U4N_HI, MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM
- , MEP_F_CCRN_HI, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_MAX
+ , MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_EXT4
+ , MEP_F_EXT62, MEP_F_CRN, MEP_F_CSRN_HI, MEP_F_CSRN_LO
+ , MEP_F_CSRN, MEP_F_CRNX_HI, MEP_F_CRNX_LO, MEP_F_CRNX
+ , MEP_F_0, MEP_F_1, MEP_F_2, MEP_F_3
+ , MEP_F_4, MEP_F_5, MEP_F_6, MEP_F_7
+ , MEP_F_8, MEP_F_9, MEP_F_10, MEP_F_11
+ , MEP_F_12, MEP_F_13, MEP_F_14, MEP_F_15
+ , MEP_F_16, MEP_F_17, MEP_F_18, MEP_F_19
+ , MEP_F_20, MEP_F_21, MEP_F_22, MEP_F_23
+ , MEP_F_24, MEP_F_25, MEP_F_26, MEP_F_27
+ , MEP_F_28, MEP_F_29, MEP_F_30, MEP_F_31
+ , MEP_F_8S8A2, MEP_F_12S4A2, MEP_F_17S16A2, MEP_F_24S5A2N_HI
+ , MEP_F_24S5A2N_LO, MEP_F_24S5A2N, MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO
+ , MEP_F_24U5A2N, MEP_F_2U6, MEP_F_7U9, MEP_F_7U9A2
+ , MEP_F_7U9A4, MEP_F_16S16, MEP_F_2U10, MEP_F_3U5
+ , MEP_F_4U8, MEP_F_5U8, MEP_F_5U24, MEP_F_6S8
+ , MEP_F_8S8, MEP_F_16U16, MEP_F_12U16, MEP_F_3U29
+ , MEP_F_CDISP10, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO, MEP_F_24U8A4N
+ , MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N, MEP_F_24U4N_HI
+ , MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM, MEP_F_CCRN_HI
+ , MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_C5N4, MEP_F_C5N5
+ , MEP_F_C5N6, MEP_F_C5N7, MEP_F_RL5, MEP_F_12S20
+ , MEP_F_C5_RNM, MEP_F_C5_RM, MEP_F_C5_16U16, MEP_F_C5_RMUIMM20
+ , MEP_F_C5_RNMUIMM24, MEP_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) MEP_F_MAX)
, MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3
, MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2
, MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4
- , MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4
- , MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_MAX
+ , MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP10, MEP_OPERAND_CDISP10A2, MEP_OPERAND_CDISP10A4
+ , MEP_OPERAND_CDISP10A8, MEP_OPERAND_ZERO, MEP_OPERAND_RL5, MEP_OPERAND_CDISP12
+ , MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
-#define MAX_OPERANDS 79
+#define MAX_OPERANDS 83
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
case MEP_OPERAND_ADDR24A4 :
print_normal (cd, info, fields->f_24u8a4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
+ case MEP_OPERAND_C5RMUIMM20 :
+ print_normal (cd, info, fields->f_c5_rmuimm20, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case MEP_OPERAND_C5RNMUIMM24 :
+ print_normal (cd, info, fields->f_c5_rnmuimm24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
case MEP_OPERAND_CALLNUM :
print_normal (cd, info, fields->f_callnum, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
case MEP_OPERAND_CCRN :
print_keyword (cd, info, & mep_cgen_opval_h_ccr, fields->f_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
break;
- case MEP_OPERAND_CDISP8 :
- print_normal (cd, info, fields->f_8s24, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ case MEP_OPERAND_CDISP10 :
+ print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
- case MEP_OPERAND_CDISP8A2 :
- print_normal (cd, info, fields->f_8s24a2, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ case MEP_OPERAND_CDISP10A2 :
+ print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
- case MEP_OPERAND_CDISP8A4 :
- print_normal (cd, info, fields->f_8s24a4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ case MEP_OPERAND_CDISP10A4 :
+ print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
- case MEP_OPERAND_CDISP8A8 :
- print_normal (cd, info, fields->f_8s24a8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ case MEP_OPERAND_CDISP10A8 :
+ print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case MEP_OPERAND_CDISP12 :
+ print_normal (cd, info, fields->f_12s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case MEP_OPERAND_CIMM4 :
print_normal (cd, info, fields->f_rn, 0, pc, length);
case MEP_OPERAND_RL :
print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl, 0);
break;
+ case MEP_OPERAND_RL5 :
+ print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl5, 0);
+ break;
case MEP_OPERAND_RM :
print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0);
break;
break;
}
break;
+ case MEP_OPERAND_C5RMUIMM20 :
+ {
+{
+ FLD (f_c5_rm) = ((unsigned int) (FLD (f_c5_rmuimm20)) >> (16));
+ FLD (f_c5_16u16) = ((FLD (f_c5_rmuimm20)) & (65535));
+}
+ errmsg = insert_normal (cd, fields->f_c5_rm, 0, 0, 8, 4, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_c5_16u16, 0, 0, 16, 16, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case MEP_OPERAND_C5RNMUIMM24 :
+ {
+{
+ FLD (f_c5_rnm) = ((unsigned int) (FLD (f_c5_rnmuimm24)) >> (16));
+ FLD (f_c5_16u16) = ((FLD (f_c5_rnmuimm24)) & (65535));
+}
+ errmsg = insert_normal (cd, fields->f_c5_rnm, 0, 0, 4, 8, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_c5_16u16, 0, 0, 16, 16, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
case MEP_OPERAND_CALLNUM :
{
{
break;
}
break;
- case MEP_OPERAND_CDISP8 :
- errmsg = insert_normal (cd, fields->f_8s24, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 8, 32, total_length, buffer);
+ case MEP_OPERAND_CDISP10 :
+ {
+ long value = fields->f_cdisp10;
+ value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+ errmsg = insert_normal (cd, value, 0, 0, 22, 10, 32, total_length, buffer);
+ }
break;
- case MEP_OPERAND_CDISP8A2 :
+ case MEP_OPERAND_CDISP10A2 :
{
- long value = fields->f_8s24a2;
- value = ((int) (value) >> (1));
- errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 7, 32, total_length, buffer);
+ long value = fields->f_cdisp10;
+ value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+ errmsg = insert_normal (cd, value, 0, 0, 22, 10, 32, total_length, buffer);
}
break;
- case MEP_OPERAND_CDISP8A4 :
+ case MEP_OPERAND_CDISP10A4 :
{
- long value = fields->f_8s24a4;
- value = ((int) (value) >> (2));
- errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 6, 32, total_length, buffer);
+ long value = fields->f_cdisp10;
+ value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+ errmsg = insert_normal (cd, value, 0, 0, 22, 10, 32, total_length, buffer);
}
break;
- case MEP_OPERAND_CDISP8A8 :
+ case MEP_OPERAND_CDISP10A8 :
{
- long value = fields->f_8s24a8;
- value = ((int) (value) >> (3));
- errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 5, 32, total_length, buffer);
+ long value = fields->f_cdisp10;
+ value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+ errmsg = insert_normal (cd, value, 0, 0, 22, 10, 32, total_length, buffer);
}
break;
+ case MEP_OPERAND_CDISP12 :
+ errmsg = insert_normal (cd, fields->f_12s20, 0, 0, 20, 12, 32, total_length, buffer);
+ break;
case MEP_OPERAND_CIMM4 :
errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer);
break;
case MEP_OPERAND_RL :
errmsg = insert_normal (cd, fields->f_rl, 0, 0, 12, 4, 32, total_length, buffer);
break;
+ case MEP_OPERAND_RL5 :
+ errmsg = insert_normal (cd, fields->f_rl5, 0, 0, 20, 4, 32, total_length, buffer);
+ break;
case MEP_OPERAND_RM :
errmsg = insert_normal (cd, fields->f_rm, 0, 0, 8, 4, 32, total_length, buffer);
break;
FLD (f_24u8a4n) = ((((FLD (f_24u8a4n_hi)) << (8))) | (((FLD (f_24u8a4n_lo)) << (2))));
}
break;
+ case MEP_OPERAND_C5RMUIMM20 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_c5_rm);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_c5_16u16);
+ if (length <= 0) break;
+{
+ FLD (f_c5_rmuimm20) = ((FLD (f_c5_16u16)) | (((FLD (f_c5_rm)) << (16))));
+}
+ }
+ break;
+ case MEP_OPERAND_C5RNMUIMM24 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 32, total_length, pc, & fields->f_c5_rnm);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_c5_16u16);
+ if (length <= 0) break;
+{
+ FLD (f_c5_rnmuimm24) = ((FLD (f_c5_16u16)) | (((FLD (f_c5_rnm)) << (16))));
+}
+ }
+ break;
case MEP_OPERAND_CALLNUM :
{
length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_5);
FLD (f_ccrn) = ((((FLD (f_ccrn_hi)) << (4))) | (FLD (f_ccrn_lo)));
}
break;
- case MEP_OPERAND_CDISP8 :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 8, 32, total_length, pc, & fields->f_8s24);
+ case MEP_OPERAND_CDISP10 :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 10, 32, total_length, pc, & value);
+ value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+ fields->f_cdisp10 = value;
+ }
break;
- case MEP_OPERAND_CDISP8A2 :
+ case MEP_OPERAND_CDISP10A2 :
{
long value;
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 7, 32, total_length, pc, & value);
- value = ((value) << (1));
- fields->f_8s24a2 = value;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 10, 32, total_length, pc, & value);
+ value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+ fields->f_cdisp10 = value;
}
break;
- case MEP_OPERAND_CDISP8A4 :
+ case MEP_OPERAND_CDISP10A4 :
{
long value;
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 6, 32, total_length, pc, & value);
- value = ((value) << (2));
- fields->f_8s24a4 = value;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 10, 32, total_length, pc, & value);
+ value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+ fields->f_cdisp10 = value;
}
break;
- case MEP_OPERAND_CDISP8A8 :
+ case MEP_OPERAND_CDISP10A8 :
{
long value;
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 5, 32, total_length, pc, & value);
- value = ((value) << (3));
- fields->f_8s24a8 = value;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 10, 32, total_length, pc, & value);
+ value = ((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value));
+ fields->f_cdisp10 = value;
}
break;
+ case MEP_OPERAND_CDISP12 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 12, 32, total_length, pc, & fields->f_12s20);
+ break;
case MEP_OPERAND_CIMM4 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn);
break;
case MEP_OPERAND_RL :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_rl);
break;
+ case MEP_OPERAND_RL5 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 4, 32, total_length, pc, & fields->f_rl5);
+ break;
case MEP_OPERAND_RM :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_rm);
break;
case MEP_OPERAND_ADDR24A4 :
value = fields->f_24u8a4n;
break;
+ case MEP_OPERAND_C5RMUIMM20 :
+ value = fields->f_c5_rmuimm20;
+ break;
+ case MEP_OPERAND_C5RNMUIMM24 :
+ value = fields->f_c5_rnmuimm24;
+ break;
case MEP_OPERAND_CALLNUM :
value = fields->f_callnum;
break;
case MEP_OPERAND_CCRN :
value = fields->f_ccrn;
break;
- case MEP_OPERAND_CDISP8 :
- value = fields->f_8s24;
+ case MEP_OPERAND_CDISP10 :
+ value = fields->f_cdisp10;
break;
- case MEP_OPERAND_CDISP8A2 :
- value = fields->f_8s24a2;
+ case MEP_OPERAND_CDISP10A2 :
+ value = fields->f_cdisp10;
break;
- case MEP_OPERAND_CDISP8A4 :
- value = fields->f_8s24a4;
+ case MEP_OPERAND_CDISP10A4 :
+ value = fields->f_cdisp10;
break;
- case MEP_OPERAND_CDISP8A8 :
- value = fields->f_8s24a8;
+ case MEP_OPERAND_CDISP10A8 :
+ value = fields->f_cdisp10;
+ break;
+ case MEP_OPERAND_CDISP12 :
+ value = fields->f_12s20;
break;
case MEP_OPERAND_CIMM4 :
value = fields->f_rn;
case MEP_OPERAND_RL :
value = fields->f_rl;
break;
+ case MEP_OPERAND_RL5 :
+ value = fields->f_rl5;
+ break;
case MEP_OPERAND_RM :
value = fields->f_rm;
break;
case MEP_OPERAND_ADDR24A4 :
value = fields->f_24u8a4n;
break;
+ case MEP_OPERAND_C5RMUIMM20 :
+ value = fields->f_c5_rmuimm20;
+ break;
+ case MEP_OPERAND_C5RNMUIMM24 :
+ value = fields->f_c5_rnmuimm24;
+ break;
case MEP_OPERAND_CALLNUM :
value = fields->f_callnum;
break;
case MEP_OPERAND_CCRN :
value = fields->f_ccrn;
break;
- case MEP_OPERAND_CDISP8 :
- value = fields->f_8s24;
+ case MEP_OPERAND_CDISP10 :
+ value = fields->f_cdisp10;
break;
- case MEP_OPERAND_CDISP8A2 :
- value = fields->f_8s24a2;
+ case MEP_OPERAND_CDISP10A2 :
+ value = fields->f_cdisp10;
break;
- case MEP_OPERAND_CDISP8A4 :
- value = fields->f_8s24a4;
+ case MEP_OPERAND_CDISP10A4 :
+ value = fields->f_cdisp10;
break;
- case MEP_OPERAND_CDISP8A8 :
- value = fields->f_8s24a8;
+ case MEP_OPERAND_CDISP10A8 :
+ value = fields->f_cdisp10;
+ break;
+ case MEP_OPERAND_CDISP12 :
+ value = fields->f_12s20;
break;
case MEP_OPERAND_CIMM4 :
value = fields->f_rn;
case MEP_OPERAND_RL :
value = fields->f_rl;
break;
+ case MEP_OPERAND_RL5 :
+ value = fields->f_rl5;
+ break;
case MEP_OPERAND_RM :
value = fields->f_rm;
break;
case MEP_OPERAND_ADDR24A4 :
fields->f_24u8a4n = value;
break;
+ case MEP_OPERAND_C5RMUIMM20 :
+ fields->f_c5_rmuimm20 = value;
+ break;
+ case MEP_OPERAND_C5RNMUIMM24 :
+ fields->f_c5_rnmuimm24 = value;
+ break;
case MEP_OPERAND_CALLNUM :
fields->f_callnum = value;
break;
case MEP_OPERAND_CCRN :
fields->f_ccrn = value;
break;
- case MEP_OPERAND_CDISP8 :
- fields->f_8s24 = value;
+ case MEP_OPERAND_CDISP10 :
+ fields->f_cdisp10 = value;
+ break;
+ case MEP_OPERAND_CDISP10A2 :
+ fields->f_cdisp10 = value;
break;
- case MEP_OPERAND_CDISP8A2 :
- fields->f_8s24a2 = value;
+ case MEP_OPERAND_CDISP10A4 :
+ fields->f_cdisp10 = value;
break;
- case MEP_OPERAND_CDISP8A4 :
- fields->f_8s24a4 = value;
+ case MEP_OPERAND_CDISP10A8 :
+ fields->f_cdisp10 = value;
break;
- case MEP_OPERAND_CDISP8A8 :
- fields->f_8s24a8 = value;
+ case MEP_OPERAND_CDISP12 :
+ fields->f_12s20 = value;
break;
case MEP_OPERAND_CIMM4 :
fields->f_rn = value;
case MEP_OPERAND_RL :
fields->f_rl = value;
break;
+ case MEP_OPERAND_RL5 :
+ fields->f_rl5 = value;
+ break;
case MEP_OPERAND_RM :
fields->f_rm = value;
break;
case MEP_OPERAND_ADDR24A4 :
fields->f_24u8a4n = value;
break;
+ case MEP_OPERAND_C5RMUIMM20 :
+ fields->f_c5_rmuimm20 = value;
+ break;
+ case MEP_OPERAND_C5RNMUIMM24 :
+ fields->f_c5_rnmuimm24 = value;
+ break;
case MEP_OPERAND_CALLNUM :
fields->f_callnum = value;
break;
case MEP_OPERAND_CCRN :
fields->f_ccrn = value;
break;
- case MEP_OPERAND_CDISP8 :
- fields->f_8s24 = value;
+ case MEP_OPERAND_CDISP10 :
+ fields->f_cdisp10 = value;
+ break;
+ case MEP_OPERAND_CDISP10A2 :
+ fields->f_cdisp10 = value;
break;
- case MEP_OPERAND_CDISP8A2 :
- fields->f_8s24a2 = value;
+ case MEP_OPERAND_CDISP10A4 :
+ fields->f_cdisp10 = value;
break;
- case MEP_OPERAND_CDISP8A4 :
- fields->f_8s24a4 = value;
+ case MEP_OPERAND_CDISP10A8 :
+ fields->f_cdisp10 = value;
break;
- case MEP_OPERAND_CDISP8A8 :
- fields->f_8s24a8 = value;
+ case MEP_OPERAND_CDISP12 :
+ fields->f_12s20 = value;
break;
case MEP_OPERAND_CIMM4 :
fields->f_rn = value;
case MEP_OPERAND_RL :
fields->f_rl = value;
break;
+ case MEP_OPERAND_RL5 :
+ fields->f_rl5 = value;
+ break;
case MEP_OPERAND_RM :
fields->f_rm = value;
break;
{
/* config-map-start */
/* Default entry: mep core only, all options enabled. */
- { "", 0, EF_MEP_CPU_C4, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
- { "default", CONFIG_DEFAULT, EF_MEP_CPU_C4, 0, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
+ { "", 0, EF_MEP_CPU_C5, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
+ { "default", CONFIG_DEFAULT, EF_MEP_CPU_C5, 0, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
0
| (1 << CGEN_INSN_OPTIONAL_MUL_INSN)
| (1 << CGEN_INSN_OPTIONAL_DIV_INSN)
case EF_MEP_CPU_H1:
mach |= (1 << MACH_H1);
break;
+ case EF_MEP_CPU_C5:
+ mach |= (1 << MACH_MEP);
+ mach |= (1 << MACH_C5);
+ break;
default:
break;
}
0, 0, 0x0, { { 0 } }
};
+static const CGEN_IFMT ifmt_stcb_r ATTRIBUTE_UNUSED = {
+ 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_pref ATTRIBUTE_UNUSED = {
+ 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_prefd ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_casb3 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf00ff0ff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_C5N4) }, { F (F_RL5) }, { F (F_C5N6) }, { F (F_C5N7) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_sbcp ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf00ff000, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_12S20) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lbucpa ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_EXT62) }, { F (F_CDISP10) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lhucpa ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_EXT62) }, { F (F_CDISP10) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_uci ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_dsp ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } }
+};
+
static const CGEN_IFMT ifmt_sb ATTRIBUTE_UNUSED = {
16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
};
16, 16, 0xf007, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_5U8) }, { F (F_SUB3) }, { 0 } }
};
-static const CGEN_IFMT ifmt_add3x ATTRIBUTE_UNUSED = {
- 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_sltu3x ATTRIBUTE_UNUSED = {
- 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } }
-};
-
static const CGEN_IFMT ifmt_bra ATTRIBUTE_UNUSED = {
16, 16, 0xf001, { { F (F_MAJOR) }, { F (F_12S4A2) }, { F (F_15) }, { 0 } }
};
16, 16, 0xf80f, { { F (F_MAJOR) }, { F (F_4) }, { F (F_3U5) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
};
-static const CGEN_IFMT ifmt_tas ATTRIBUTE_UNUSED = {
- 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_cache ATTRIBUTE_UNUSED = {
- 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
-};
-
static const CGEN_IFMT ifmt_madd ATTRIBUTE_UNUSED = {
32, 32, 0xf00fffff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } }
};
32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } }
};
-static const CGEN_IFMT ifmt_sbcpa ATTRIBUTE_UNUSED = {
- 32, 32, 0xf00fff00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_8S24) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_shcpa ATTRIBUTE_UNUSED = {
- 32, 32, 0xf00fff01, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_8S24A2) }, { F (F_31) }, { 0 } }
-};
-
static const CGEN_IFMT ifmt_swcpa ATTRIBUTE_UNUSED = {
- 32, 32, 0xf00fff03, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_8S24A4) }, { F (F_30) }, { F (F_31) }, { 0 } }
+ 32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_EXT62) }, { F (F_CDISP10) }, { 0 } }
};
static const CGEN_IFMT ifmt_smcpa ATTRIBUTE_UNUSED = {
- 32, 32, 0xf00fff07, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_8S24A8) }, { F (F_29) }, { F (F_30) }, { F (F_31) }, { 0 } }
+ 32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_EXT62) }, { F (F_CDISP10) }, { 0 } }
};
static const CGEN_IFMT ifmt_bcpeq ATTRIBUTE_UNUSED = {
A `num' value of zero is thus invalid.
Also, the special `invalid' insn resides here. */
{ { 0, 0, 0, 0 }, {{0}}, 0, {0}},
+/* stcb $rn,($rma) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RN), ',', '(', OP (RMA), ')', 0 } },
+ & ifmt_stcb_r, { 0x700c }
+ },
+/* ldcb $rn,($rma) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RN), ',', '(', OP (RMA), ')', 0 } },
+ & ifmt_stcb_r, { 0x700d }
+ },
+/* pref $cimm4,($rma) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CIMM4), ',', '(', OP (RMA), ')', 0 } },
+ & ifmt_pref, { 0x7005 }
+ },
+/* pref $cimm4,$sdisp16($rma) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CIMM4), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } },
+ & ifmt_prefd, { 0xf0030000 }
+ },
+/* casb3 $rl5,$rn,($rm) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RL5), ',', OP (RN), ',', '(', OP (RM), ')', 0 } },
+ & ifmt_casb3, { 0xf0012000 }
+ },
+/* cash3 $rl5,$rn,($rm) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RL5), ',', OP (RN), ',', '(', OP (RM), ')', 0 } },
+ & ifmt_casb3, { 0xf0012001 }
+ },
+/* casw3 $rl5,$rn,($rm) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RL5), ',', OP (RN), ',', '(', OP (RM), ')', 0 } },
+ & ifmt_casb3, { 0xf0012002 }
+ },
+/* sbcp $crn,$cdisp12($rma) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } },
+ & ifmt_sbcp, { 0xf0060000 }
+ },
+/* lbcp $crn,$cdisp12($rma) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } },
+ & ifmt_sbcp, { 0xf0064000 }
+ },
+/* lbucp $crn,$cdisp12($rma) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } },
+ & ifmt_sbcp, { 0xf006c000 }
+ },
+/* shcp $crn,$cdisp12($rma) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } },
+ & ifmt_sbcp, { 0xf0061000 }
+ },
+/* lhcp $crn,$cdisp12($rma) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } },
+ & ifmt_sbcp, { 0xf0065000 }
+ },
+/* lhucp $crn,$cdisp12($rma) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } },
+ & ifmt_sbcp, { 0xf006d000 }
+ },
+/* lbucpa $crn,($rma+),$cdisp10 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+ & ifmt_lbucpa, { 0xf005c000 }
+ },
+/* lhucpa $crn,($rma+),$cdisp10a2 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+ & ifmt_lhucpa, { 0xf005d000 }
+ },
+/* lbucpm0 $crn,($rma+),$cdisp10 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+ & ifmt_lbucpa, { 0xf005c800 }
+ },
+/* lhucpm0 $crn,($rma+),$cdisp10a2 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+ & ifmt_lhucpa, { 0xf005d800 }
+ },
+/* lbucpm1 $crn,($rma+),$cdisp10 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+ & ifmt_lbucpa, { 0xf005cc00 }
+ },
+/* lhucpm1 $crn,($rma+),$cdisp10a2 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+ & ifmt_lhucpa, { 0xf005dc00 }
+ },
+/* uci $rn,$rm,$uimm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } },
+ & ifmt_uci, { 0xf0020000 }
+ },
+/* dsp $rn,$rm,$uimm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } },
+ & ifmt_dsp, { 0xf0000000 }
+ },
/* sb $rnc,($rma) */
{
{ 0, 0, 0, 0 },
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (SIMM16), 0 } },
- & ifmt_add3x, { 0xc0000000 }
+ & ifmt_uci, { 0xc0000000 }
},
/* slt3 $rn,$rm,$simm16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (SIMM16), 0 } },
- & ifmt_add3x, { 0xc0020000 }
+ & ifmt_uci, { 0xc0020000 }
},
/* sltu3 $rn,$rm,$uimm16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } },
- & ifmt_sltu3x, { 0xc0030000 }
+ & ifmt_dsp, { 0xc0030000 }
},
/* or $rn,$rm */
{
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } },
- & ifmt_sltu3x, { 0xc0040000 }
+ & ifmt_dsp, { 0xc0040000 }
},
/* and3 $rn,$rm,$uimm16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } },
- & ifmt_sltu3x, { 0xc0050000 }
+ & ifmt_dsp, { 0xc0050000 }
},
/* xor3 $rn,$rm,$uimm16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } },
- & ifmt_sltu3x, { 0xc0060000 }
+ & ifmt_dsp, { 0xc0060000 }
},
/* sra $rn,$rm */
{
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RN), ',', '(', OP (RMA), ')', 0 } },
- & ifmt_tas, { 0x2004 }
+ & ifmt_stcb_r, { 0x2004 }
},
/* cache $cimm4,($rma) */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (CIMM4), ',', '(', OP (RMA), ')', 0 } },
- & ifmt_cache, { 0x7004 }
+ & ifmt_pref, { 0x7004 }
},
/* mul $rn,$rm */
{
{ { MNEM, ' ', OP (CRN64), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } },
& ifmt_smcp16, { 0xf00f0000 }
},
-/* sbcpa $crn,($rma+),$cdisp8 */
+/* sbcpa $crn,($rma+),$cdisp10 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } },
- & ifmt_sbcpa, { 0xf0050000 }
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+ & ifmt_lbucpa, { 0xf0050000 }
},
-/* lbcpa $crn,($rma+),$cdisp8 */
+/* lbcpa $crn,($rma+),$cdisp10 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } },
- & ifmt_sbcpa, { 0xf0054000 }
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+ & ifmt_lbucpa, { 0xf0054000 }
},
-/* shcpa $crn,($rma+),$cdisp8a2 */
+/* shcpa $crn,($rma+),$cdisp10a2 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } },
- & ifmt_shcpa, { 0xf0051000 }
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+ & ifmt_lhucpa, { 0xf0051000 }
},
-/* lhcpa $crn,($rma+),$cdisp8a2 */
+/* lhcpa $crn,($rma+),$cdisp10a2 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } },
- & ifmt_shcpa, { 0xf0055000 }
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+ & ifmt_lhucpa, { 0xf0055000 }
},
-/* swcpa $crn,($rma+),$cdisp8a4 */
+/* swcpa $crn,($rma+),$cdisp10a4 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } },
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } },
& ifmt_swcpa, { 0xf0052000 }
},
-/* lwcpa $crn,($rma+),$cdisp8a4 */
+/* lwcpa $crn,($rma+),$cdisp10a4 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } },
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } },
& ifmt_swcpa, { 0xf0056000 }
},
-/* smcpa $crn64,($rma+),$cdisp8a8 */
+/* smcpa $crn64,($rma+),$cdisp10a8 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } },
+ { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } },
& ifmt_smcpa, { 0xf0053000 }
},
-/* lmcpa $crn64,($rma+),$cdisp8a8 */
+/* lmcpa $crn64,($rma+),$cdisp10a8 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } },
+ { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } },
& ifmt_smcpa, { 0xf0057000 }
},
-/* sbcpm0 $crn,($rma+),$cdisp8 */
+/* sbcpm0 $crn,($rma+),$cdisp10 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } },
- & ifmt_sbcpa, { 0xf0050800 }
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+ & ifmt_lbucpa, { 0xf0050800 }
},
-/* lbcpm0 $crn,($rma+),$cdisp8 */
+/* lbcpm0 $crn,($rma+),$cdisp10 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } },
- & ifmt_sbcpa, { 0xf0054800 }
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+ & ifmt_lbucpa, { 0xf0054800 }
},
-/* shcpm0 $crn,($rma+),$cdisp8a2 */
+/* shcpm0 $crn,($rma+),$cdisp10a2 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } },
- & ifmt_shcpa, { 0xf0051800 }
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+ & ifmt_lhucpa, { 0xf0051800 }
},
-/* lhcpm0 $crn,($rma+),$cdisp8a2 */
+/* lhcpm0 $crn,($rma+),$cdisp10a2 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } },
- & ifmt_shcpa, { 0xf0055800 }
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+ & ifmt_lhucpa, { 0xf0055800 }
},
-/* swcpm0 $crn,($rma+),$cdisp8a4 */
+/* swcpm0 $crn,($rma+),$cdisp10a4 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } },
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } },
& ifmt_swcpa, { 0xf0052800 }
},
-/* lwcpm0 $crn,($rma+),$cdisp8a4 */
+/* lwcpm0 $crn,($rma+),$cdisp10a4 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } },
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } },
& ifmt_swcpa, { 0xf0056800 }
},
-/* smcpm0 $crn64,($rma+),$cdisp8a8 */
+/* smcpm0 $crn64,($rma+),$cdisp10a8 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } },
+ { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } },
& ifmt_smcpa, { 0xf0053800 }
},
-/* lmcpm0 $crn64,($rma+),$cdisp8a8 */
+/* lmcpm0 $crn64,($rma+),$cdisp10a8 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } },
+ { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } },
& ifmt_smcpa, { 0xf0057800 }
},
-/* sbcpm1 $crn,($rma+),$cdisp8 */
+/* sbcpm1 $crn,($rma+),$cdisp10 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } },
- & ifmt_sbcpa, { 0xf0050c00 }
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+ & ifmt_lbucpa, { 0xf0050c00 }
},
-/* lbcpm1 $crn,($rma+),$cdisp8 */
+/* lbcpm1 $crn,($rma+),$cdisp10 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } },
- & ifmt_sbcpa, { 0xf0054c00 }
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } },
+ & ifmt_lbucpa, { 0xf0054c00 }
},
-/* shcpm1 $crn,($rma+),$cdisp8a2 */
+/* shcpm1 $crn,($rma+),$cdisp10a2 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } },
- & ifmt_shcpa, { 0xf0051c00 }
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+ & ifmt_lhucpa, { 0xf0051c00 }
},
-/* lhcpm1 $crn,($rma+),$cdisp8a2 */
+/* lhcpm1 $crn,($rma+),$cdisp10a2 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } },
- & ifmt_shcpa, { 0xf0055c00 }
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } },
+ & ifmt_lhucpa, { 0xf0055c00 }
},
-/* swcpm1 $crn,($rma+),$cdisp8a4 */
+/* swcpm1 $crn,($rma+),$cdisp10a4 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } },
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } },
& ifmt_swcpa, { 0xf0052c00 }
},
-/* lwcpm1 $crn,($rma+),$cdisp8a4 */
+/* lwcpm1 $crn,($rma+),$cdisp10a4 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } },
+ { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } },
& ifmt_swcpa, { 0xf0056c00 }
},
-/* smcpm1 $crn64,($rma+),$cdisp8a8 */
+/* smcpm1 $crn64,($rma+),$cdisp10a8 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } },
+ { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } },
& ifmt_smcpa, { 0xf0053c00 }
},
-/* lmcpm1 $crn64,($rma+),$cdisp8a8 */
+/* lmcpm1 $crn64,($rma+),$cdisp10a8 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } },
+ { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } },
& ifmt_smcpa, { 0xf0057c00 }
},
/* bcpeq $cccc,$pcrel17a2 */
{
{ 0, 0, 0, 0 },
{ { MNEM, 0 } },
- & ifmt_mov, { 0xf003 }
- },
-/* --reserved-- */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_mov, { 0xf006 }
- },
-/* --reserved-- */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
& ifmt_mov, { 0xf008 }
},
-/* --reserved-- */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_mov, { 0x7005 }
- },
-/* --reserved-- */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_mov, { 0x700c }
- },
-/* --reserved-- */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_mov, { 0x700d }
- },
};
#undef A
#else
#define F(f) & mep_cgen_ifld_table[MEP_/**/f]
#endif
+static const CGEN_IFMT ifmt_dsp0 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_dsp1 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } }
+};
+
static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = {
16, 16, 0xffff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } }
};
static const CGEN_IBASE mep_cgen_macro_insn_table[] =
{
+/* dsp0 $c5rnmuimm24 */
+ {
+ -1, "dsp0", "dsp0", 32,
+ { 0|A(VOLATILE)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
+/* dsp1 $rn,$c5rmuimm20 */
+ {
+ -1, "dsp1", "dsp1", 32,
+ { 0|A(VOLATILE)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
+ },
/* nop */
{
-1, "nop", "nop", 16,
static const CGEN_OPCODE mep_cgen_macro_insn_opcode_table[] =
{
+/* dsp0 $c5rnmuimm24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (C5RNMUIMM24), 0 } },
+ & ifmt_dsp0, { 0xf0000000 }
+ },
+/* dsp1 $rn,$c5rmuimm20 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RN), ',', OP (C5RMUIMM20), 0 } },
+ & ifmt_dsp1, { 0xf0000000 }
+ },
/* nop */
{
{ 0, 0, 0, 0 },
/* -- asm.c */
/* Enum declaration for mep instruction types. */
typedef enum cgen_insn_type {
- MEP_INSN_INVALID, MEP_INSN_SB, MEP_INSN_SH, MEP_INSN_SW
- , MEP_INSN_LB, MEP_INSN_LH, MEP_INSN_LW, MEP_INSN_LBU
- , MEP_INSN_LHU, MEP_INSN_SW_SP, MEP_INSN_LW_SP, MEP_INSN_SB_TP
- , MEP_INSN_SH_TP, MEP_INSN_SW_TP, MEP_INSN_LB_TP, MEP_INSN_LH_TP
- , MEP_INSN_LW_TP, MEP_INSN_LBU_TP, MEP_INSN_LHU_TP, MEP_INSN_SB16
- , MEP_INSN_SH16, MEP_INSN_SW16, MEP_INSN_LB16, MEP_INSN_LH16
- , MEP_INSN_LW16, MEP_INSN_LBU16, MEP_INSN_LHU16, MEP_INSN_SW24
- , MEP_INSN_LW24, MEP_INSN_EXTB, MEP_INSN_EXTH, MEP_INSN_EXTUB
- , MEP_INSN_EXTUH, MEP_INSN_SSARB, MEP_INSN_MOV, MEP_INSN_MOVI8
- , MEP_INSN_MOVI16, MEP_INSN_MOVU24, MEP_INSN_MOVU16, MEP_INSN_MOVH
- , MEP_INSN_ADD3, MEP_INSN_ADD, MEP_INSN_ADD3I, MEP_INSN_ADVCK3
- , MEP_INSN_SUB, MEP_INSN_SBVCK3, MEP_INSN_NEG, MEP_INSN_SLT3
- , MEP_INSN_SLTU3, MEP_INSN_SLT3I, MEP_INSN_SLTU3I, MEP_INSN_SL1AD3
- , MEP_INSN_SL2AD3, MEP_INSN_ADD3X, MEP_INSN_SLT3X, MEP_INSN_SLTU3X
- , MEP_INSN_OR, MEP_INSN_AND, MEP_INSN_XOR, MEP_INSN_NOR
- , MEP_INSN_OR3, MEP_INSN_AND3, MEP_INSN_XOR3, MEP_INSN_SRA
- , MEP_INSN_SRL, MEP_INSN_SLL, MEP_INSN_SRAI, MEP_INSN_SRLI
- , MEP_INSN_SLLI, MEP_INSN_SLL3, MEP_INSN_FSFT, MEP_INSN_BRA
- , MEP_INSN_BEQZ, MEP_INSN_BNEZ, MEP_INSN_BEQI, MEP_INSN_BNEI
- , MEP_INSN_BLTI, MEP_INSN_BGEI, MEP_INSN_BEQ, MEP_INSN_BNE
- , MEP_INSN_BSR12, MEP_INSN_BSR24, MEP_INSN_JMP, MEP_INSN_JMP24
- , MEP_INSN_JSR, MEP_INSN_RET, MEP_INSN_REPEAT, MEP_INSN_EREPEAT
- , MEP_INSN_STC_LP, MEP_INSN_STC_HI, MEP_INSN_STC_LO, MEP_INSN_STC
- , MEP_INSN_LDC_LP, MEP_INSN_LDC_HI, MEP_INSN_LDC_LO, MEP_INSN_LDC
- , MEP_INSN_DI, MEP_INSN_EI, MEP_INSN_RETI, MEP_INSN_HALT
- , MEP_INSN_SLEEP, MEP_INSN_SWI, MEP_INSN_BREAK, MEP_INSN_SYNCM
- , MEP_INSN_STCB, MEP_INSN_LDCB, MEP_INSN_BSETM, MEP_INSN_BCLRM
- , MEP_INSN_BNOTM, MEP_INSN_BTSTM, MEP_INSN_TAS, MEP_INSN_CACHE
- , MEP_INSN_MUL, MEP_INSN_MULU, MEP_INSN_MULR, MEP_INSN_MULRU
- , MEP_INSN_MADD, MEP_INSN_MADDU, MEP_INSN_MADDR, MEP_INSN_MADDRU
- , MEP_INSN_DIV, MEP_INSN_DIVU, MEP_INSN_DRET, MEP_INSN_DBREAK
- , MEP_INSN_LDZ, MEP_INSN_ABS, MEP_INSN_AVE, MEP_INSN_MIN
- , MEP_INSN_MAX, MEP_INSN_MINU, MEP_INSN_MAXU, MEP_INSN_CLIP
- , MEP_INSN_CLIPU, MEP_INSN_SADD, MEP_INSN_SSUB, MEP_INSN_SADDU
- , MEP_INSN_SSUBU, MEP_INSN_SWCP, MEP_INSN_LWCP, MEP_INSN_SMCP
- , MEP_INSN_LMCP, MEP_INSN_SWCPI, MEP_INSN_LWCPI, MEP_INSN_SMCPI
- , MEP_INSN_LMCPI, MEP_INSN_SWCP16, MEP_INSN_LWCP16, MEP_INSN_SMCP16
- , MEP_INSN_LMCP16, MEP_INSN_SBCPA, MEP_INSN_LBCPA, MEP_INSN_SHCPA
- , MEP_INSN_LHCPA, MEP_INSN_SWCPA, MEP_INSN_LWCPA, MEP_INSN_SMCPA
- , MEP_INSN_LMCPA, MEP_INSN_SBCPM0, MEP_INSN_LBCPM0, MEP_INSN_SHCPM0
- , MEP_INSN_LHCPM0, MEP_INSN_SWCPM0, MEP_INSN_LWCPM0, MEP_INSN_SMCPM0
- , MEP_INSN_LMCPM0, MEP_INSN_SBCPM1, MEP_INSN_LBCPM1, MEP_INSN_SHCPM1
- , MEP_INSN_LHCPM1, MEP_INSN_SWCPM1, MEP_INSN_LWCPM1, MEP_INSN_SMCPM1
- , MEP_INSN_LMCPM1, MEP_INSN_BCPEQ, MEP_INSN_BCPNE, MEP_INSN_BCPAT
- , MEP_INSN_BCPAF, MEP_INSN_SYNCCP, MEP_INSN_JSRV, MEP_INSN_BSRV
- , MEP_INSN_SIM_SYSCALL, MEP_INSN_RI_0, MEP_INSN_RI_1, MEP_INSN_RI_2
- , MEP_INSN_RI_3, MEP_INSN_RI_4, MEP_INSN_RI_5, MEP_INSN_RI_6
- , MEP_INSN_RI_7, MEP_INSN_RI_8, MEP_INSN_RI_9, MEP_INSN_RI_10
- , MEP_INSN_RI_11, MEP_INSN_RI_12, MEP_INSN_RI_13, MEP_INSN_RI_14
- , MEP_INSN_RI_15, MEP_INSN_RI_17, MEP_INSN_RI_20, MEP_INSN_RI_21
- , MEP_INSN_RI_22, MEP_INSN_RI_23, MEP_INSN_RI_24, MEP_INSN_RI_25
- , MEP_INSN_RI_26, MEP_INSN_RI_16, MEP_INSN_RI_18, MEP_INSN_RI_19
+ MEP_INSN_INVALID, MEP_INSN_STCB_R, MEP_INSN_LDCB_R, MEP_INSN_PREF
+ , MEP_INSN_PREFD, MEP_INSN_CASB3, MEP_INSN_CASH3, MEP_INSN_CASW3
+ , MEP_INSN_SBCP, MEP_INSN_LBCP, MEP_INSN_LBUCP, MEP_INSN_SHCP
+ , MEP_INSN_LHCP, MEP_INSN_LHUCP, MEP_INSN_LBUCPA, MEP_INSN_LHUCPA
+ , MEP_INSN_LBUCPM0, MEP_INSN_LHUCPM0, MEP_INSN_LBUCPM1, MEP_INSN_LHUCPM1
+ , MEP_INSN_UCI, MEP_INSN_DSP, MEP_INSN_SB, MEP_INSN_SH
+ , MEP_INSN_SW, MEP_INSN_LB, MEP_INSN_LH, MEP_INSN_LW
+ , MEP_INSN_LBU, MEP_INSN_LHU, MEP_INSN_SW_SP, MEP_INSN_LW_SP
+ , MEP_INSN_SB_TP, MEP_INSN_SH_TP, MEP_INSN_SW_TP, MEP_INSN_LB_TP
+ , MEP_INSN_LH_TP, MEP_INSN_LW_TP, MEP_INSN_LBU_TP, MEP_INSN_LHU_TP
+ , MEP_INSN_SB16, MEP_INSN_SH16, MEP_INSN_SW16, MEP_INSN_LB16
+ , MEP_INSN_LH16, MEP_INSN_LW16, MEP_INSN_LBU16, MEP_INSN_LHU16
+ , MEP_INSN_SW24, MEP_INSN_LW24, MEP_INSN_EXTB, MEP_INSN_EXTH
+ , MEP_INSN_EXTUB, MEP_INSN_EXTUH, MEP_INSN_SSARB, MEP_INSN_MOV
+ , MEP_INSN_MOVI8, MEP_INSN_MOVI16, MEP_INSN_MOVU24, MEP_INSN_MOVU16
+ , MEP_INSN_MOVH, MEP_INSN_ADD3, MEP_INSN_ADD, MEP_INSN_ADD3I
+ , MEP_INSN_ADVCK3, MEP_INSN_SUB, MEP_INSN_SBVCK3, MEP_INSN_NEG
+ , MEP_INSN_SLT3, MEP_INSN_SLTU3, MEP_INSN_SLT3I, MEP_INSN_SLTU3I
+ , MEP_INSN_SL1AD3, MEP_INSN_SL2AD3, MEP_INSN_ADD3X, MEP_INSN_SLT3X
+ , MEP_INSN_SLTU3X, MEP_INSN_OR, MEP_INSN_AND, MEP_INSN_XOR
+ , MEP_INSN_NOR, MEP_INSN_OR3, MEP_INSN_AND3, MEP_INSN_XOR3
+ , MEP_INSN_SRA, MEP_INSN_SRL, MEP_INSN_SLL, MEP_INSN_SRAI
+ , MEP_INSN_SRLI, MEP_INSN_SLLI, MEP_INSN_SLL3, MEP_INSN_FSFT
+ , MEP_INSN_BRA, MEP_INSN_BEQZ, MEP_INSN_BNEZ, MEP_INSN_BEQI
+ , MEP_INSN_BNEI, MEP_INSN_BLTI, MEP_INSN_BGEI, MEP_INSN_BEQ
+ , MEP_INSN_BNE, MEP_INSN_BSR12, MEP_INSN_BSR24, MEP_INSN_JMP
+ , MEP_INSN_JMP24, MEP_INSN_JSR, MEP_INSN_RET, MEP_INSN_REPEAT
+ , MEP_INSN_EREPEAT, MEP_INSN_STC_LP, MEP_INSN_STC_HI, MEP_INSN_STC_LO
+ , MEP_INSN_STC, MEP_INSN_LDC_LP, MEP_INSN_LDC_HI, MEP_INSN_LDC_LO
+ , MEP_INSN_LDC, MEP_INSN_DI, MEP_INSN_EI, MEP_INSN_RETI
+ , MEP_INSN_HALT, MEP_INSN_SLEEP, MEP_INSN_SWI, MEP_INSN_BREAK
+ , MEP_INSN_SYNCM, MEP_INSN_STCB, MEP_INSN_LDCB, MEP_INSN_BSETM
+ , MEP_INSN_BCLRM, MEP_INSN_BNOTM, MEP_INSN_BTSTM, MEP_INSN_TAS
+ , MEP_INSN_CACHE, MEP_INSN_MUL, MEP_INSN_MULU, MEP_INSN_MULR
+ , MEP_INSN_MULRU, MEP_INSN_MADD, MEP_INSN_MADDU, MEP_INSN_MADDR
+ , MEP_INSN_MADDRU, MEP_INSN_DIV, MEP_INSN_DIVU, MEP_INSN_DRET
+ , MEP_INSN_DBREAK, MEP_INSN_LDZ, MEP_INSN_ABS, MEP_INSN_AVE
+ , MEP_INSN_MIN, MEP_INSN_MAX, MEP_INSN_MINU, MEP_INSN_MAXU
+ , MEP_INSN_CLIP, MEP_INSN_CLIPU, MEP_INSN_SADD, MEP_INSN_SSUB
+ , MEP_INSN_SADDU, MEP_INSN_SSUBU, MEP_INSN_SWCP, MEP_INSN_LWCP
+ , MEP_INSN_SMCP, MEP_INSN_LMCP, MEP_INSN_SWCPI, MEP_INSN_LWCPI
+ , MEP_INSN_SMCPI, MEP_INSN_LMCPI, MEP_INSN_SWCP16, MEP_INSN_LWCP16
+ , MEP_INSN_SMCP16, MEP_INSN_LMCP16, MEP_INSN_SBCPA, MEP_INSN_LBCPA
+ , MEP_INSN_SHCPA, MEP_INSN_LHCPA, MEP_INSN_SWCPA, MEP_INSN_LWCPA
+ , MEP_INSN_SMCPA, MEP_INSN_LMCPA, MEP_INSN_SBCPM0, MEP_INSN_LBCPM0
+ , MEP_INSN_SHCPM0, MEP_INSN_LHCPM0, MEP_INSN_SWCPM0, MEP_INSN_LWCPM0
+ , MEP_INSN_SMCPM0, MEP_INSN_LMCPM0, MEP_INSN_SBCPM1, MEP_INSN_LBCPM1
+ , MEP_INSN_SHCPM1, MEP_INSN_LHCPM1, MEP_INSN_SWCPM1, MEP_INSN_LWCPM1
+ , MEP_INSN_SMCPM1, MEP_INSN_LMCPM1, MEP_INSN_BCPEQ, MEP_INSN_BCPNE
+ , MEP_INSN_BCPAT, MEP_INSN_BCPAF, MEP_INSN_SYNCCP, MEP_INSN_JSRV
+ , MEP_INSN_BSRV, MEP_INSN_SIM_SYSCALL, MEP_INSN_RI_0, MEP_INSN_RI_1
+ , MEP_INSN_RI_2, MEP_INSN_RI_3, MEP_INSN_RI_4, MEP_INSN_RI_5
+ , MEP_INSN_RI_6, MEP_INSN_RI_7, MEP_INSN_RI_8, MEP_INSN_RI_9
+ , MEP_INSN_RI_10, MEP_INSN_RI_11, MEP_INSN_RI_12, MEP_INSN_RI_13
+ , MEP_INSN_RI_14, MEP_INSN_RI_15, MEP_INSN_RI_17, MEP_INSN_RI_20
+ , MEP_INSN_RI_21, MEP_INSN_RI_22, MEP_INSN_RI_23, MEP_INSN_RI_26
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
#define CGEN_INSN_INVALID MEP_INSN_INVALID
/* Total number of insns in table. */
-#define MAX_INSNS ((int) MEP_INSN_RI_19 + 1)
+#define MAX_INSNS ((int) MEP_INSN_RI_26 + 1)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
long f_sub3;
long f_sub4;
long f_ext;
+ long f_ext4;
+ long f_ext62;
long f_crn;
long f_csrn_hi;
long f_csrn_lo;
long f_16u16;
long f_12u16;
long f_3u29;
- long f_8s24;
- long f_8s24a2;
- long f_8s24a4;
- long f_8s24a8;
+ long f_cdisp10;
long f_24u8a4n_hi;
long f_24u8a4n_lo;
long f_24u8a4n;
long f_ccrn_hi;
long f_ccrn_lo;
long f_ccrn;
+ long f_c5n4;
+ long f_c5n5;
+ long f_c5n6;
+ long f_c5n7;
+ long f_rl5;
+ long f_12s20;
+ long f_c5_rnm;
+ long f_c5_rm;
+ long f_c5_16u16;
+ long f_c5_rmuimm20;
+ long f_c5_rnmuimm24;
};
#define CGEN_INIT_PARSE(od) \
invalidate_set_pin (this, &cache_component::invalidate_set),
flush_and_invalidate_pin (this, &cache_component::flush_and_invalidate_line),
prefetch_pin (this, &cache_component::prefetch_line),
+ write_hint_pin (this, &cache_component::write_hint),
lock_pin (this, &cache_component::lock_line),
unlock_pin (this, &cache_component::unlock_line),
write_allocate_p (false),
add_pin ("invalidate", &invalidate_pin);
add_pin ("flush-and-invalidate", &flush_and_invalidate_pin);
add_pin ("prefetch", &prefetch_pin);
+ add_pin ("write-hint", &write_hint_pin);
add_pin ("lock", &lock_pin);
add_pin ("unlock", &unlock_pin);
add_pin ("operation-status", &operation_status_pin);
return st;
}
+// Prepare a line for writing. This means we are expecting to write
+// to all the bytes in the line, so we set it up to *not* read the
+// line from the cache on the first write to it, by making the line
+// valid if needed. As a side effect, if you don't write to all the
+// bytes in the line, unwritten bytes are undefined when written to
+// memory.
+void
+cache_component::write_hint (host_int_4 addr)
+{
+ bus::status st, read_status;
+
+ if (UNLIKELY (downstream == 0))
+ return;
+
+ if (LIKELY (collect_p))
+ stats.reads++;
+
+ cache_tag tag = acache.addr_to_tag (addr);
+ cache_line* line = acache.find (tag);
+ if (LIKELY (line))
+ {
+ // Line already exists in cache, nothing to do.
+ }
+ else
+ {
+ // miss!
+ if (acache.vacancy_p (addr))
+ {
+ if (LIKELY (collect_p))
+ stats.replacements++;
+
+ cache_line *expelled_line = acache.expell_line (tag);
+ assert (expelled_line);
+ if (expelled_line->valid_p () && expelled_line->dirty_p ())
+ {
+ // flush a dirty line being replaced
+ if ((st = write_line (*expelled_line)) != bus::ok)
+ return;
+ }
+ expelled_line->set_tag (tag);
+ // We don't actually read the line, though.
+ expelled_line->validate ();
+ }
+ else
+ {
+ // No room in the cache, so our hint must go uneeded.
+ }
+ }
+
+ st = bus::ok;
+ if (line)
+ st.latency += hit_latency;
+ else
+ st.latency = miss_latency;
+ report_status (st);
+ return;
+}
+
bus::status
cache_component::read_line (cache_line& line)
{
callback_pin<cache_component> prefetch_pin;
virtual void prefetch_line (host_int_4 addr);
+ callback_pin<cache_component> write_hint_pin;
+ virtual void write_hint (host_int_4 addr);
+
callback_pin<cache_component> lock_pin;
virtual void lock_line (host_int_4 addr);
libmep_la_LDFLAGS =
libmep_la_LIBADD = mep-asm.lo mep-dis.lo mep-opc.lo mep-ibld.lo mep-desc.lo
-CGEN_MACH = mep
+CGEN_MACH = c5
OPCODES_COMPILE_FLAGS = -DHAVE_CONFIG_H \
-I../../../../opcodes \
libmep_la_SOURCES = mep.cxx common_model.cxx mep-decode.cxx mep-sem.cxx mep-model.cxx $(CPU_SOURCES)
libmep_la_LDFLAGS =
libmep_la_LIBADD = mep-asm.lo mep-dis.lo mep-opc.lo mep-ibld.lo mep-desc.lo
-CGEN_MACH = mep
+CGEN_MACH = c5
OPCODES_COMPILE_FLAGS = -DHAVE_CONFIG_H \
-I../../../../opcodes \
-I../../../../bfd \
// The instruction descriptor array.
-mepcore1_idesc mepcore1_idesc::idesc_table[MEPCORE1_INSN_RI_19 + 1] =
+mepcore1_idesc mepcore1_idesc::idesc_table[MEPCORE1_INSN_RI_26 + 1] =
{
{ mepcore1_sem_x_invalid, "X_INVALID", MEPCORE1_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x40" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_stcb_r, "STCB_R", MEPCORE1_INSN_STCB_R, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_ldcb_r, "LDCB_R", MEPCORE1_INSN_LDCB_R, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 3, CONFIG_NONE } },
+ { mepcore1_sem_pref, "PREF", MEPCORE1_INSN_PREF, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_prefd, "PREFD", MEPCORE1_INSN_PREFD, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_casb3, "CASB3", MEPCORE1_INSN_CASB3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_cash3, "CASH3", MEPCORE1_INSN_CASH3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_casw3, "CASW3", MEPCORE1_INSN_CASW3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_sbcp, "SBCP", MEPCORE1_INSN_SBCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_lbcp, "LBCP", MEPCORE1_INSN_LBCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_lbucp, "LBUCP", MEPCORE1_INSN_LBUCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_shcp, "SHCP", MEPCORE1_INSN_SHCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_lhcp, "LHCP", MEPCORE1_INSN_LHCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_lhucp, "LHUCP", MEPCORE1_INSN_LHUCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_lbucpa, "LBUCPA", MEPCORE1_INSN_LBUCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_lhucpa, "LHUCPA", MEPCORE1_INSN_LHUCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_lbucpm0, "LBUCPM0", MEPCORE1_INSN_LBUCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_lhucpm0, "LHUCPM0", MEPCORE1_INSN_LHUCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_lbucpm1, "LBUCPM1", MEPCORE1_INSN_LBUCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_lhucpm1, "LHUCPM1", MEPCORE1_INSN_LHUCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_uci, "UCI", MEPCORE1_INSN_UCI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mepcore1_sem_dsp, "DSP", MEPCORE1_INSN_DSP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mepcore1_sem_sb, "SB", MEPCORE1_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mepcore1_sem_sh, "SH", MEPCORE1_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mepcore1_sem_sw, "SW", MEPCORE1_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mepcore1_sem_ri_21, "RI_21", MEPCORE1_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mepcore1_sem_ri_22, "RI_22", MEPCORE1_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mepcore1_sem_ri_23, "RI_23", MEPCORE1_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
- { mepcore1_sem_ri_24, "RI_24", MEPCORE1_INSN_RI_24, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
- { mepcore1_sem_ri_25, "RI_25", MEPCORE1_INSN_RI_25, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mepcore1_sem_ri_26, "RI_26", MEPCORE1_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
- { mepcore1_sem_ri_16, "RI_16", MEPCORE1_INSN_RI_16, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
- { mepcore1_sem_ri_18, "RI_18", MEPCORE1_INSN_RI_18, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
- { mepcore1_sem_ri_19, "RI_19", MEPCORE1_INSN_RI_19, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
};
static void
mepcore1_extract_sfmt_empty (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
+mepcore1_extract_sfmt_stcb_r (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_ldcb_r (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_pref (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_prefd (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_casb3 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_sbcp (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_lbcp (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_shcp (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_lhcp (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_lbucpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_lhucpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_lbucpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_lhucpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_lbucpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_lhucpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
+mepcore1_extract_sfmt_uci (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
+static void
mepcore1_extract_sfmt_sb (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
mepcore1_extract_sfmt_sh (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
mepcore1_extract_sfmt_tas (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
-mepcore1_extract_sfmt_cache (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
-static void
mepcore1_extract_sfmt_mul (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
mepcore1_extract_sfmt_mulr (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
mepcore1_extract_sfmt_sbcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
-mepcore1_extract_sfmt_lbcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
-static void
mepcore1_extract_sfmt_shcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
-mepcore1_extract_sfmt_lhcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
-static void
mepcore1_extract_sfmt_swcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
mepcore1_extract_sfmt_lwcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
mepcore1_extract_sfmt_sbcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
-mepcore1_extract_sfmt_lbcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
-static void
mepcore1_extract_sfmt_shcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
-mepcore1_extract_sfmt_lhcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
-static void
mepcore1_extract_sfmt_swcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
mepcore1_extract_sfmt_lwcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
mepcore1_extract_sfmt_sbcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
-mepcore1_extract_sfmt_lbcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
-static void
mepcore1_extract_sfmt_shcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
-mepcore1_extract_sfmt_lhcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
-static void
mepcore1_extract_sfmt_swcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
static void
mepcore1_extract_sfmt_lwcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn);
case 116 :
entire_insn = entire_insn >> 16;
if ((entire_insn & 0xf00f) == 0x7004)
- { itype = MEPCORE1_INSN_CACHE; mepcore1_extract_sfmt_cache (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCORE1_INSN_CACHE; mepcore1_extract_sfmt_pref (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 117 :
entire_insn = entire_insn >> 16;
if ((entire_insn & 0xf00f) == 0x7005)
- { itype = MEPCORE1_INSN_RI_16; mepcore1_extract_sfmt_break (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCORE1_INSN_PREF; mepcore1_extract_sfmt_pref (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 118 :
entire_insn = entire_insn >> 16;
case 124 :
entire_insn = entire_insn >> 16;
if ((entire_insn & 0xf00f) == 0x700c)
- { itype = MEPCORE1_INSN_RI_18; mepcore1_extract_sfmt_break (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCORE1_INSN_STCB_R; mepcore1_extract_sfmt_stcb_r (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 125 :
entire_insn = entire_insn >> 16;
if ((entire_insn & 0xf00f) == 0x700d)
- { itype = MEPCORE1_INSN_RI_19; mepcore1_extract_sfmt_break (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCORE1_INSN_LDCB_R; mepcore1_extract_sfmt_ldcb_r (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 126 :
entire_insn = entire_insn >> 16;
if ((entire_insn & 0xf00f) == 0xe00d)
{ itype = MEPCORE1_INSN_RI_23; mepcore1_extract_sfmt_break (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 240 :
+ if ((entire_insn & 0xf00f0000) == 0xf0000000)
+ { itype = MEPCORE1_INSN_DSP; mepcore1_extract_sfmt_uci (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 241 :
{
unsigned int val = (((insn >> 8) & (3 << 4)) | ((insn >> 0) & (15 << 0)));
if ((entire_insn & 0xf0ffff07) == 0xf0011001)
{ itype = MEPCORE1_INSN_CLIPU; mepcore1_extract_sfmt_clipu (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 32 :
+ if ((entire_insn & 0xf00ff0ff) == 0xf0012000)
+ { itype = MEPCORE1_INSN_CASB3; mepcore1_extract_sfmt_casb3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 33 :
+ if ((entire_insn & 0xf00ff0ff) == 0xf0012001)
+ { itype = MEPCORE1_INSN_CASH3; mepcore1_extract_sfmt_casb3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 34 :
+ if ((entire_insn & 0xf00ff0ff) == 0xf0012002)
+ { itype = MEPCORE1_INSN_CASW3; mepcore1_extract_sfmt_casb3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 52 :
if ((entire_insn & 0xf00fffff) == 0xf0013004)
{ itype = MEPCORE1_INSN_MADD; mepcore1_extract_sfmt_madd (this, current_cpu, pc, base_insn, entire_insn); goto done; }
default : itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
+ case 242 :
+ if ((entire_insn & 0xf00f0000) == 0xf0020000)
+ { itype = MEPCORE1_INSN_UCI; mepcore1_extract_sfmt_uci (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 243 :
- entire_insn = entire_insn >> 16;
- if ((entire_insn & 0xf00f) == 0xf003)
- { itype = MEPCORE1_INSN_RI_24; mepcore1_extract_sfmt_break (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00f0000) == 0xf0030000)
+ { itype = MEPCORE1_INSN_PREFD; mepcore1_extract_sfmt_prefd (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 244 :
{
}
case 245 :
{
- unsigned int val = (((insn >> 10) & (31 << 0)));
+ unsigned int val = (((insn >> 10) & (63 << 0)));
switch (val)
{
case 0 :
- if ((entire_insn & 0xf00fff00) == 0xf0050000)
+ if ((entire_insn & 0xf00ffc00) == 0xf0050000)
{ itype = MEPCORE1_INSN_SBCPA; mepcore1_extract_sfmt_sbcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
- if ((entire_insn & 0xf00fff00) == 0xf0050800)
+ if ((entire_insn & 0xf00ffc00) == 0xf0050800)
{ itype = MEPCORE1_INSN_SBCPM0; mepcore1_extract_sfmt_sbcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
- if ((entire_insn & 0xf00fff00) == 0xf0050c00)
+ if ((entire_insn & 0xf00ffc00) == 0xf0050c00)
{ itype = MEPCORE1_INSN_SBCPM1; mepcore1_extract_sfmt_sbcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
- if ((entire_insn & 0xf00fff01) == 0xf0051000)
+ if ((entire_insn & 0xf00ffc00) == 0xf0051000)
{ itype = MEPCORE1_INSN_SHCPA; mepcore1_extract_sfmt_shcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
- if ((entire_insn & 0xf00fff01) == 0xf0051800)
+ if ((entire_insn & 0xf00ffc00) == 0xf0051800)
{ itype = MEPCORE1_INSN_SHCPM0; mepcore1_extract_sfmt_shcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
- if ((entire_insn & 0xf00fff01) == 0xf0051c00)
+ if ((entire_insn & 0xf00ffc00) == 0xf0051c00)
{ itype = MEPCORE1_INSN_SHCPM1; mepcore1_extract_sfmt_shcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 8 :
- if ((entire_insn & 0xf00fff03) == 0xf0052000)
+ if ((entire_insn & 0xf00ffc00) == 0xf0052000)
{ itype = MEPCORE1_INSN_SWCPA; mepcore1_extract_sfmt_swcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 10 :
- if ((entire_insn & 0xf00fff03) == 0xf0052800)
+ if ((entire_insn & 0xf00ffc00) == 0xf0052800)
{ itype = MEPCORE1_INSN_SWCPM0; mepcore1_extract_sfmt_swcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 11 :
- if ((entire_insn & 0xf00fff03) == 0xf0052c00)
+ if ((entire_insn & 0xf00ffc00) == 0xf0052c00)
{ itype = MEPCORE1_INSN_SWCPM1; mepcore1_extract_sfmt_swcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 12 :
- if ((entire_insn & 0xf00fff07) == 0xf0053000)
+ if ((entire_insn & 0xf00ffc00) == 0xf0053000)
{ itype = MEPCORE1_INSN_SMCPA; mepcore1_extract_sfmt_smcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 14 :
- if ((entire_insn & 0xf00fff07) == 0xf0053800)
+ if ((entire_insn & 0xf00ffc00) == 0xf0053800)
{ itype = MEPCORE1_INSN_SMCPM0; mepcore1_extract_sfmt_smcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 15 :
- if ((entire_insn & 0xf00fff07) == 0xf0053c00)
+ if ((entire_insn & 0xf00ffc00) == 0xf0053c00)
{ itype = MEPCORE1_INSN_SMCPM1; mepcore1_extract_sfmt_smcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 16 :
- if ((entire_insn & 0xf00fff00) == 0xf0054000)
- { itype = MEPCORE1_INSN_LBCPA; mepcore1_extract_sfmt_lbcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00ffc00) == 0xf0054000)
+ { itype = MEPCORE1_INSN_LBCPA; mepcore1_extract_sfmt_lbucpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 18 :
- if ((entire_insn & 0xf00fff00) == 0xf0054800)
- { itype = MEPCORE1_INSN_LBCPM0; mepcore1_extract_sfmt_lbcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00ffc00) == 0xf0054800)
+ { itype = MEPCORE1_INSN_LBCPM0; mepcore1_extract_sfmt_lbucpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 19 :
- if ((entire_insn & 0xf00fff00) == 0xf0054c00)
- { itype = MEPCORE1_INSN_LBCPM1; mepcore1_extract_sfmt_lbcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00ffc00) == 0xf0054c00)
+ { itype = MEPCORE1_INSN_LBCPM1; mepcore1_extract_sfmt_lbucpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 20 :
- if ((entire_insn & 0xf00fff01) == 0xf0055000)
- { itype = MEPCORE1_INSN_LHCPA; mepcore1_extract_sfmt_lhcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00ffc00) == 0xf0055000)
+ { itype = MEPCORE1_INSN_LHCPA; mepcore1_extract_sfmt_lhucpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 22 :
- if ((entire_insn & 0xf00fff01) == 0xf0055800)
- { itype = MEPCORE1_INSN_LHCPM0; mepcore1_extract_sfmt_lhcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00ffc00) == 0xf0055800)
+ { itype = MEPCORE1_INSN_LHCPM0; mepcore1_extract_sfmt_lhucpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 23 :
- if ((entire_insn & 0xf00fff01) == 0xf0055c00)
- { itype = MEPCORE1_INSN_LHCPM1; mepcore1_extract_sfmt_lhcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00ffc00) == 0xf0055c00)
+ { itype = MEPCORE1_INSN_LHCPM1; mepcore1_extract_sfmt_lhucpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 24 :
- if ((entire_insn & 0xf00fff03) == 0xf0056000)
+ if ((entire_insn & 0xf00ffc00) == 0xf0056000)
{ itype = MEPCORE1_INSN_LWCPA; mepcore1_extract_sfmt_lwcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 26 :
- if ((entire_insn & 0xf00fff03) == 0xf0056800)
+ if ((entire_insn & 0xf00ffc00) == 0xf0056800)
{ itype = MEPCORE1_INSN_LWCPM0; mepcore1_extract_sfmt_lwcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 27 :
- if ((entire_insn & 0xf00fff03) == 0xf0056c00)
+ if ((entire_insn & 0xf00ffc00) == 0xf0056c00)
{ itype = MEPCORE1_INSN_LWCPM1; mepcore1_extract_sfmt_lwcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 28 :
- if ((entire_insn & 0xf00fff07) == 0xf0057000)
+ if ((entire_insn & 0xf00ffc00) == 0xf0057000)
{ itype = MEPCORE1_INSN_LMCPA; mepcore1_extract_sfmt_lmcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 30 :
- if ((entire_insn & 0xf00fff07) == 0xf0057800)
+ if ((entire_insn & 0xf00ffc00) == 0xf0057800)
{ itype = MEPCORE1_INSN_LMCPM0; mepcore1_extract_sfmt_lmcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 31 :
- if ((entire_insn & 0xf00fff07) == 0xf0057c00)
+ if ((entire_insn & 0xf00ffc00) == 0xf0057c00)
{ itype = MEPCORE1_INSN_LMCPM1; mepcore1_extract_sfmt_lmcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 48 :
+ if ((entire_insn & 0xf00ffc00) == 0xf005c000)
+ { itype = MEPCORE1_INSN_LBUCPA; mepcore1_extract_sfmt_lbucpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 50 :
+ if ((entire_insn & 0xf00ffc00) == 0xf005c800)
+ { itype = MEPCORE1_INSN_LBUCPM0; mepcore1_extract_sfmt_lbucpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 51 :
+ if ((entire_insn & 0xf00ffc00) == 0xf005cc00)
+ { itype = MEPCORE1_INSN_LBUCPM1; mepcore1_extract_sfmt_lbucpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 52 :
+ if ((entire_insn & 0xf00ffc00) == 0xf005d000)
+ { itype = MEPCORE1_INSN_LHUCPA; mepcore1_extract_sfmt_lhucpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 54 :
+ if ((entire_insn & 0xf00ffc00) == 0xf005d800)
+ { itype = MEPCORE1_INSN_LHUCPM0; mepcore1_extract_sfmt_lhucpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 55 :
+ if ((entire_insn & 0xf00ffc00) == 0xf005dc00)
+ { itype = MEPCORE1_INSN_LHUCPM1; mepcore1_extract_sfmt_lhucpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
case 246 :
- entire_insn = entire_insn >> 16;
- if ((entire_insn & 0xf00f) == 0xf006)
- { itype = MEPCORE1_INSN_RI_25; mepcore1_extract_sfmt_break (this, current_cpu, pc, base_insn, entire_insn); goto done; }
- itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ {
+ unsigned int val = (((insn >> 13) & (3 << 1)) | ((insn >> 12) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf00ff000) == 0xf0060000)
+ { itype = MEPCORE1_INSN_SBCP; mepcore1_extract_sfmt_sbcp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 1 :
+ if ((entire_insn & 0xf00ff000) == 0xf0061000)
+ { itype = MEPCORE1_INSN_SHCP; mepcore1_extract_sfmt_shcp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 2 :
+ if ((entire_insn & 0xf00ff000) == 0xf0064000)
+ { itype = MEPCORE1_INSN_LBCP; mepcore1_extract_sfmt_lbcp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 3 :
+ if ((entire_insn & 0xf00ff000) == 0xf0065000)
+ { itype = MEPCORE1_INSN_LHCP; mepcore1_extract_sfmt_lhcp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 6 :
+ if ((entire_insn & 0xf00ff000) == 0xf006c000)
+ { itype = MEPCORE1_INSN_LBUCP; mepcore1_extract_sfmt_lbcp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 7 :
+ if ((entire_insn & 0xf00ff000) == 0xf006d000)
+ { itype = MEPCORE1_INSN_LHUCP; mepcore1_extract_sfmt_lhcp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ default : itype = MEPCORE1_INSN_X_INVALID; mepcore1_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ }
+ }
case 248 :
entire_insn = entire_insn >> 16;
if ((entire_insn & 0xf00f) == 0xf008)
}
}
- }
-
- /* The instruction has been decoded and fields extracted. */
- done:
-
- this->addr = pc;
- // FIXME: To be redone (to handle ISA variants).
- this->idesc = & mepcore1_idesc::idesc_table[itype];
- // ??? record semantic handler?
- assert(this->idesc->sem_index == itype);
+ }
+
+ /* The instruction has been decoded and fields extracted. */
+ done:
+
+ this->addr = pc;
+ // FIXME: To be redone (to handle ISA variants).
+ this->idesc = & mepcore1_idesc::idesc_table[itype];
+ // ??? record semantic handler?
+ assert(this->idesc->sem_index == itype);
+}
+
+void
+mepcore1_extract_sfmt_empty (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_empty)\t"
+ << endl;
+ }
+
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_stcb_r (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stcb_r.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ FLD (i_rn) = & current_cpu->hardware.h_gpr[f_rn];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_stcb_r)\t"
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_rn:0x" << hex << f_rn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ FLD (in_rn) = f_rn;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_ldcb_r (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ FLD (i_rn) = & current_cpu->hardware.h_gpr[f_rn];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_ldcb_r)\t"
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_rn:0x" << hex << f_rn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ FLD (out_rn) = f_rn;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_pref (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ FLD (f_rm) = f_rm;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_pref)\t"
+ << " f_rn:0x" << hex << f_rn << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_prefd (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lhu16.f
+ UINT f_rn;
+ UINT f_rm;
+ INT f_16s16;
+
+ f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_16s16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ FLD (f_rm) = f_rm;
+ FLD (f_16s16) = f_16s16;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_prefd)\t"
+ << " f_rn:0x" << hex << f_rn << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_16s16:0x" << hex << f_16s16 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_casb3 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ UINT f_rn;
+ UINT f_rm;
+ UINT f_rl5;
+
+ f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_rl5 = EXTRACT_MSB0_UINT (insn, 32, 20, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rl5) = f_rl5;
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ FLD (i_rl5) = & current_cpu->hardware.h_gpr[f_rl5];
+ FLD (i_rm) = & current_cpu->hardware.h_gpr[f_rm];
+ FLD (i_rn) = & current_cpu->hardware.h_gpr[f_rn];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_casb3)\t"
+ << " f_rl5:0x" << hex << f_rl5 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_rn:0x" << hex << f_rn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rl5) = f_rl5;
+ FLD (in_rm) = f_rm;
+ FLD (in_rn) = f_rn;
+ FLD (out_rl5) = f_rl5;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_sbcp (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ UINT f_crn;
+ UINT f_rm;
+ UINT f_12s20;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_12s20 = EXTRACT_MSB0_UINT (insn, 32, 20, 12);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_12s20) = f_12s20;
+ FLD (f_crn) = f_crn;
+ FLD (f_rm) = f_rm;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_sbcp)\t"
+ << " f_12s20:0x" << hex << f_12s20 << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_lbcp (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ UINT f_crn;
+ UINT f_rm;
+ UINT f_12s20;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_12s20 = EXTRACT_MSB0_UINT (insn, 32, 20, 12);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_12s20) = f_12s20;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lbcp)\t"
+ << " f_12s20:0x" << hex << f_12s20 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_shcp (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ UINT f_crn;
+ UINT f_rm;
+ UINT f_12s20;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_12s20 = EXTRACT_MSB0_UINT (insn, 32, 20, 12);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_12s20) = f_12s20;
+ FLD (f_crn) = f_crn;
+ FLD (f_rm) = f_rm;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_shcp)\t"
+ << " f_12s20:0x" << hex << f_12s20 << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_lhcp (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ UINT f_crn;
+ UINT f_rm;
+ UINT f_12s20;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_12s20 = EXTRACT_MSB0_UINT (insn, 32, 20, 12);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_12s20) = f_12s20;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lhcp)\t"
+ << " f_12s20:0x" << hex << f_12s20 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_lbucpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ UINT f_crn;
+ UINT f_rm;
+ SI f_cdisp10;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cdisp10) = f_cdisp10;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lbucpa)\t"
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ FLD (out_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_lhucpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ UINT f_crn;
+ UINT f_rm;
+ SI f_cdisp10;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cdisp10) = f_cdisp10;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lhucpa)\t"
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ FLD (out_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_lbucpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ UINT f_crn;
+ UINT f_rm;
+ SI f_cdisp10;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cdisp10) = f_cdisp10;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lbucpm0)\t"
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_mb0) = 12;
+ FLD (in_me0) = 13;
+ FLD (in_rma) = f_rm;
+ FLD (out_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_lhucpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ UINT f_crn;
+ UINT f_rm;
+ SI f_cdisp10;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cdisp10) = f_cdisp10;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lhucpm0)\t"
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_mb0) = 12;
+ FLD (in_me0) = 13;
+ FLD (in_rma) = f_rm;
+ FLD (out_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_lbucpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ UINT f_crn;
+ UINT f_rm;
+ SI f_cdisp10;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cdisp10) = f_cdisp10;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lbucpm1)\t"
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_mb1) = 14;
+ FLD (in_me1) = 15;
+ FLD (in_rma) = f_rm;
+ FLD (out_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mepcore1_extract_sfmt_lhucpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+ mepcore1_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ UINT f_crn;
+ UINT f_rm;
+ SI f_cdisp10;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cdisp10) = f_cdisp10;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lhucpm1)\t"
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_mb1) = 14;
+ FLD (in_me1) = 15;
+ FLD (in_rma) = f_rm;
+ FLD (out_rma) = f_rm;
+ }
+#undef FLD
}
void
-mepcore1_extract_sfmt_empty (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
+mepcore1_extract_sfmt_uci (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_uci.f
+ UINT f_rn;
+ UINT f_rm;
+ UINT f_16u16;
+ f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_16u16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
/* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ FLD (f_16u16) = f_16u16;
+ FLD (i_rm) = & current_cpu->hardware.h_gpr[f_rm];
+ FLD (i_rn) = & current_cpu->hardware.h_gpr[f_rn];
if (UNLIKELY(current_cpu->trace_extract_p))
{
current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_empty)\t"
+ << "0x" << hex << pc << dec << " (sfmt_uci)\t"
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_rn:0x" << hex << f_rn << dec
+ << " f_16u16:0x" << hex << f_16u16 << dec
<< endl;
}
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rm) = f_rm;
+ FLD (in_rn) = f_rn;
+ FLD (out_rn) = f_rn;
+ }
#undef FLD
}
void
mepcore1_extract_sfmt_mov (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
UINT f_rn;
UINT f_rm;
void
mepcore1_extract_sfmt_movu16 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
UINT f_rn;
UINT f_16u16;
void
mepcore1_extract_sfmt_sltu3x (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
UINT f_rn;
UINT f_rm;
UINT f_16u16;
void
mepcore1_extract_sfmt_or3 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
UINT f_rn;
UINT f_rm;
UINT f_16u16;
void
mepcore1_extract_sfmt_stcb (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_stcb.f
+#define FLD(f) abuf->fields.sfmt_uci.f
UINT f_rn;
UINT f_16u16;
void
mepcore1_extract_sfmt_tas (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
UINT f_rn;
UINT f_rm;
}
void
-mepcore1_extract_sfmt_cache (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
- mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_tas.f
- UINT f_rn;
- UINT f_rm;
-
- f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
-
- /* Record the fields for the semantic handler. */
- FLD (f_rn) = f_rn;
- FLD (f_rm) = f_rm;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_cache)\t"
- << " f_rn:0x" << hex << f_rn << dec
- << " f_rm:0x" << hex << f_rm << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mepcore1_extract_sfmt_mul (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_maddr.f
void
mepcore1_extract_sfmt_ldz (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
UINT f_rn;
UINT f_rm;
void
mepcore1_extract_sfmt_swcpi (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
void
mepcore1_extract_sfmt_lwcpi (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
void
mepcore1_extract_sfmt_smcpi (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
void
mepcore1_extract_sfmt_lmcpi (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
void
mepcore1_extract_sfmt_sbcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- INT f_8s24;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24 = EXTRACT_MSB0_INT (insn, 32, 24, 8);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24) = f_8s24;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_sbcpa)\t"
- << " f_8s24:0x" << hex << f_8s24 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
}
void
-mepcore1_extract_sfmt_lbcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
- mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
- UINT f_crn;
- UINT f_rm;
- INT f_8s24;
-
- f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24 = EXTRACT_MSB0_INT (insn, 32, 24, 8);
-
- /* Record the fields for the semantic handler. */
- FLD (f_8s24) = f_8s24;
- FLD (f_rm) = f_rm;
- FLD (f_crn) = f_crn;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_lbcpa)\t"
- << " f_8s24:0x" << hex << f_8s24 << dec
- << " f_rm:0x" << hex << f_rm << dec
- << " f_crn:0x" << hex << f_crn << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_rma) = f_rm;
- FLD (out_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mepcore1_extract_sfmt_shcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a2;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a2 = ((EXTRACT_MSB0_INT (insn, 32, 24, 7)) << (1));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a2) = f_8s24a2;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_shcpa)\t"
- << " f_8s24a2:0x" << hex << f_8s24a2 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
}
void
-mepcore1_extract_sfmt_lhcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
- mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
- UINT f_crn;
- UINT f_rm;
- SI f_8s24a2;
-
- f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a2 = ((EXTRACT_MSB0_INT (insn, 32, 24, 7)) << (1));
-
- /* Record the fields for the semantic handler. */
- FLD (f_8s24a2) = f_8s24a2;
- FLD (f_rm) = f_rm;
- FLD (f_crn) = f_crn;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_lhcpa)\t"
- << " f_8s24a2:0x" << hex << f_8s24a2 << dec
- << " f_rm:0x" << hex << f_rm << dec
- << " f_crn:0x" << hex << f_crn << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_rma) = f_rm;
- FLD (out_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mepcore1_extract_sfmt_swcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a4;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a4 = ((EXTRACT_MSB0_INT (insn, 32, 24, 6)) << (2));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a4) = f_8s24a4;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_swcpa)\t"
- << " f_8s24a4:0x" << hex << f_8s24a4 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
void
mepcore1_extract_sfmt_lwcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a4;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a4 = ((EXTRACT_MSB0_INT (insn, 32, 24, 6)) << (2));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a4) = f_8s24a4;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_rm) = f_rm;
FLD (f_crn) = f_crn;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_lwcpa)\t"
- << " f_8s24a4:0x" << hex << f_8s24a4 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_rm:0x" << hex << f_rm << dec
<< " f_crn:0x" << hex << f_crn << dec
<< endl;
void
mepcore1_extract_sfmt_smcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a8;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a8 = ((EXTRACT_MSB0_INT (insn, 32, 24, 5)) << (3));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a8) = f_8s24a8;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_smcpa)\t"
- << " f_8s24a8:0x" << hex << f_8s24a8 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
void
mepcore1_extract_sfmt_lmcpa (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a8;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a8 = ((EXTRACT_MSB0_INT (insn, 32, 24, 5)) << (3));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a8) = f_8s24a8;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_rm) = f_rm;
FLD (f_crn) = f_crn;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_lmcpa)\t"
- << " f_8s24a8:0x" << hex << f_8s24a8 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_rm:0x" << hex << f_rm << dec
<< " f_crn:0x" << hex << f_crn << dec
<< endl;
void
mepcore1_extract_sfmt_sbcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
UINT f_crn;
UINT f_rm;
- INT f_8s24;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24 = EXTRACT_MSB0_INT (insn, 32, 24, 8);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24) = f_8s24;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_sbcpm0)\t"
- << " f_8s24:0x" << hex << f_8s24 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
}
void
-mepcore1_extract_sfmt_lbcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
- mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
- UINT f_crn;
- UINT f_rm;
- INT f_8s24;
-
- f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24 = EXTRACT_MSB0_INT (insn, 32, 24, 8);
-
- /* Record the fields for the semantic handler. */
- FLD (f_8s24) = f_8s24;
- FLD (f_rm) = f_rm;
- FLD (f_crn) = f_crn;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_lbcpm0)\t"
- << " f_8s24:0x" << hex << f_8s24 << dec
- << " f_rm:0x" << hex << f_rm << dec
- << " f_crn:0x" << hex << f_crn << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_mb0) = 12;
- FLD (in_me0) = 13;
- FLD (in_rma) = f_rm;
- FLD (out_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mepcore1_extract_sfmt_shcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a2;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a2 = ((EXTRACT_MSB0_INT (insn, 32, 24, 7)) << (1));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a2) = f_8s24a2;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_shcpm0)\t"
- << " f_8s24a2:0x" << hex << f_8s24a2 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
}
void
-mepcore1_extract_sfmt_lhcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
- mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
- UINT f_crn;
- UINT f_rm;
- SI f_8s24a2;
-
- f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a2 = ((EXTRACT_MSB0_INT (insn, 32, 24, 7)) << (1));
-
- /* Record the fields for the semantic handler. */
- FLD (f_8s24a2) = f_8s24a2;
- FLD (f_rm) = f_rm;
- FLD (f_crn) = f_crn;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_lhcpm0)\t"
- << " f_8s24a2:0x" << hex << f_8s24a2 << dec
- << " f_rm:0x" << hex << f_rm << dec
- << " f_crn:0x" << hex << f_crn << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_mb0) = 12;
- FLD (in_me0) = 13;
- FLD (in_rma) = f_rm;
- FLD (out_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mepcore1_extract_sfmt_swcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a4;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a4 = ((EXTRACT_MSB0_INT (insn, 32, 24, 6)) << (2));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a4) = f_8s24a4;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_swcpm0)\t"
- << " f_8s24a4:0x" << hex << f_8s24a4 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
void
mepcore1_extract_sfmt_lwcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a4;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a4 = ((EXTRACT_MSB0_INT (insn, 32, 24, 6)) << (2));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a4) = f_8s24a4;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_rm) = f_rm;
FLD (f_crn) = f_crn;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_lwcpm0)\t"
- << " f_8s24a4:0x" << hex << f_8s24a4 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_rm:0x" << hex << f_rm << dec
<< " f_crn:0x" << hex << f_crn << dec
<< endl;
void
mepcore1_extract_sfmt_smcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a8;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a8 = ((EXTRACT_MSB0_INT (insn, 32, 24, 5)) << (3));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a8) = f_8s24a8;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_smcpm0)\t"
- << " f_8s24a8:0x" << hex << f_8s24a8 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
void
mepcore1_extract_sfmt_lmcpm0 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a8;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a8 = ((EXTRACT_MSB0_INT (insn, 32, 24, 5)) << (3));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a8) = f_8s24a8;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_rm) = f_rm;
FLD (f_crn) = f_crn;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_lmcpm0)\t"
- << " f_8s24a8:0x" << hex << f_8s24a8 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_rm:0x" << hex << f_rm << dec
<< " f_crn:0x" << hex << f_crn << dec
<< endl;
void
mepcore1_extract_sfmt_sbcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- INT f_8s24;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24 = EXTRACT_MSB0_INT (insn, 32, 24, 8);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24) = f_8s24;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_sbcpm1)\t"
- << " f_8s24:0x" << hex << f_8s24 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
}
void
-mepcore1_extract_sfmt_lbcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
- mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
- UINT f_crn;
- UINT f_rm;
- INT f_8s24;
-
- f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24 = EXTRACT_MSB0_INT (insn, 32, 24, 8);
-
- /* Record the fields for the semantic handler. */
- FLD (f_8s24) = f_8s24;
- FLD (f_rm) = f_rm;
- FLD (f_crn) = f_crn;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_lbcpm1)\t"
- << " f_8s24:0x" << hex << f_8s24 << dec
- << " f_rm:0x" << hex << f_rm << dec
- << " f_crn:0x" << hex << f_crn << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_mb1) = 14;
- FLD (in_me1) = 15;
- FLD (in_rma) = f_rm;
- FLD (out_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mepcore1_extract_sfmt_shcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a2;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a2 = ((EXTRACT_MSB0_INT (insn, 32, 24, 7)) << (1));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a2) = f_8s24a2;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_shcpm1)\t"
- << " f_8s24a2:0x" << hex << f_8s24a2 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
}
void
-mepcore1_extract_sfmt_lhcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
- mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
- UINT f_crn;
- UINT f_rm;
- SI f_8s24a2;
-
- f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a2 = ((EXTRACT_MSB0_INT (insn, 32, 24, 7)) << (1));
-
- /* Record the fields for the semantic handler. */
- FLD (f_8s24a2) = f_8s24a2;
- FLD (f_rm) = f_rm;
- FLD (f_crn) = f_crn;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_lhcpm1)\t"
- << " f_8s24a2:0x" << hex << f_8s24a2 << dec
- << " f_rm:0x" << hex << f_rm << dec
- << " f_crn:0x" << hex << f_crn << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_mb1) = 14;
- FLD (in_me1) = 15;
- FLD (in_rma) = f_rm;
- FLD (out_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mepcore1_extract_sfmt_swcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a4;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a4 = ((EXTRACT_MSB0_INT (insn, 32, 24, 6)) << (2));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a4) = f_8s24a4;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_swcpm1)\t"
- << " f_8s24a4:0x" << hex << f_8s24a4 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
void
mepcore1_extract_sfmt_lwcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a4;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a4 = ((EXTRACT_MSB0_INT (insn, 32, 24, 6)) << (2));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a4) = f_8s24a4;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_rm) = f_rm;
FLD (f_crn) = f_crn;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_lwcpm1)\t"
- << " f_8s24a4:0x" << hex << f_8s24a4 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_rm:0x" << hex << f_rm << dec
<< " f_crn:0x" << hex << f_crn << dec
<< endl;
void
mepcore1_extract_sfmt_smcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a8;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a8 = ((EXTRACT_MSB0_INT (insn, 32, 24, 5)) << (3));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a8) = f_8s24a8;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_smcpm1)\t"
- << " f_8s24a8:0x" << hex << f_8s24a8 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
void
mepcore1_extract_sfmt_lmcpm1 (mepcore1_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcore1_insn_word base_insn, mepcore1_insn_word entire_insn){
mepcore1_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a8;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a8 = ((EXTRACT_MSB0_INT (insn, 32, 24, 5)) << (3));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a8) = f_8s24a8;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_rm) = f_rm;
FLD (f_crn) = f_crn;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_lmcpm1)\t"
- << " f_8s24a8:0x" << hex << f_8s24a8 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_rm:0x" << hex << f_rm << dec
<< " f_crn:0x" << hex << f_crn << dec
<< endl;
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
This file is part of the Red Hat simulators.
/* Enum declaration for instructions in cpu family mepcore1. */
typedef enum mepcore1_insn_type {
- MEPCORE1_INSN_X_INVALID, MEPCORE1_INSN_SB, MEPCORE1_INSN_SH, MEPCORE1_INSN_SW
- , MEPCORE1_INSN_LB, MEPCORE1_INSN_LH, MEPCORE1_INSN_LW, MEPCORE1_INSN_LBU
- , MEPCORE1_INSN_LHU, MEPCORE1_INSN_SW_SP, MEPCORE1_INSN_LW_SP, MEPCORE1_INSN_SB_TP
- , MEPCORE1_INSN_SH_TP, MEPCORE1_INSN_SW_TP, MEPCORE1_INSN_LB_TP, MEPCORE1_INSN_LH_TP
- , MEPCORE1_INSN_LW_TP, MEPCORE1_INSN_LBU_TP, MEPCORE1_INSN_LHU_TP, MEPCORE1_INSN_SB16
- , MEPCORE1_INSN_SH16, MEPCORE1_INSN_SW16, MEPCORE1_INSN_LB16, MEPCORE1_INSN_LH16
- , MEPCORE1_INSN_LW16, MEPCORE1_INSN_LBU16, MEPCORE1_INSN_LHU16, MEPCORE1_INSN_SW24
- , MEPCORE1_INSN_LW24, MEPCORE1_INSN_EXTB, MEPCORE1_INSN_EXTH, MEPCORE1_INSN_EXTUB
- , MEPCORE1_INSN_EXTUH, MEPCORE1_INSN_SSARB, MEPCORE1_INSN_MOV, MEPCORE1_INSN_MOVI8
- , MEPCORE1_INSN_MOVI16, MEPCORE1_INSN_MOVU24, MEPCORE1_INSN_MOVU16, MEPCORE1_INSN_MOVH
- , MEPCORE1_INSN_ADD3, MEPCORE1_INSN_ADD, MEPCORE1_INSN_ADD3I, MEPCORE1_INSN_ADVCK3
- , MEPCORE1_INSN_SUB, MEPCORE1_INSN_SBVCK3, MEPCORE1_INSN_NEG, MEPCORE1_INSN_SLT3
- , MEPCORE1_INSN_SLTU3, MEPCORE1_INSN_SLT3I, MEPCORE1_INSN_SLTU3I, MEPCORE1_INSN_SL1AD3
- , MEPCORE1_INSN_SL2AD3, MEPCORE1_INSN_ADD3X, MEPCORE1_INSN_SLT3X, MEPCORE1_INSN_SLTU3X
- , MEPCORE1_INSN_OR, MEPCORE1_INSN_AND, MEPCORE1_INSN_XOR, MEPCORE1_INSN_NOR
- , MEPCORE1_INSN_OR3, MEPCORE1_INSN_AND3, MEPCORE1_INSN_XOR3, MEPCORE1_INSN_SRA
- , MEPCORE1_INSN_SRL, MEPCORE1_INSN_SLL, MEPCORE1_INSN_SRAI, MEPCORE1_INSN_SRLI
- , MEPCORE1_INSN_SLLI, MEPCORE1_INSN_SLL3, MEPCORE1_INSN_FSFT, MEPCORE1_INSN_BRA
- , MEPCORE1_INSN_BEQZ, MEPCORE1_INSN_BNEZ, MEPCORE1_INSN_BEQI, MEPCORE1_INSN_BNEI
- , MEPCORE1_INSN_BLTI, MEPCORE1_INSN_BGEI, MEPCORE1_INSN_BEQ, MEPCORE1_INSN_BNE
- , MEPCORE1_INSN_BSR12, MEPCORE1_INSN_BSR24, MEPCORE1_INSN_JMP, MEPCORE1_INSN_JMP24
- , MEPCORE1_INSN_JSR, MEPCORE1_INSN_RET, MEPCORE1_INSN_REPEAT, MEPCORE1_INSN_EREPEAT
- , MEPCORE1_INSN_STC_LP, MEPCORE1_INSN_STC_HI, MEPCORE1_INSN_STC_LO, MEPCORE1_INSN_STC
- , MEPCORE1_INSN_LDC_LP, MEPCORE1_INSN_LDC_HI, MEPCORE1_INSN_LDC_LO, MEPCORE1_INSN_LDC
- , MEPCORE1_INSN_DI, MEPCORE1_INSN_EI, MEPCORE1_INSN_RETI, MEPCORE1_INSN_HALT
- , MEPCORE1_INSN_SLEEP, MEPCORE1_INSN_SWI, MEPCORE1_INSN_BREAK, MEPCORE1_INSN_SYNCM
- , MEPCORE1_INSN_STCB, MEPCORE1_INSN_LDCB, MEPCORE1_INSN_BSETM, MEPCORE1_INSN_BCLRM
- , MEPCORE1_INSN_BNOTM, MEPCORE1_INSN_BTSTM, MEPCORE1_INSN_TAS, MEPCORE1_INSN_CACHE
- , MEPCORE1_INSN_MUL, MEPCORE1_INSN_MULU, MEPCORE1_INSN_MULR, MEPCORE1_INSN_MULRU
- , MEPCORE1_INSN_MADD, MEPCORE1_INSN_MADDU, MEPCORE1_INSN_MADDR, MEPCORE1_INSN_MADDRU
- , MEPCORE1_INSN_DIV, MEPCORE1_INSN_DIVU, MEPCORE1_INSN_DRET, MEPCORE1_INSN_DBREAK
- , MEPCORE1_INSN_LDZ, MEPCORE1_INSN_ABS, MEPCORE1_INSN_AVE, MEPCORE1_INSN_MIN
- , MEPCORE1_INSN_MAX, MEPCORE1_INSN_MINU, MEPCORE1_INSN_MAXU, MEPCORE1_INSN_CLIP
- , MEPCORE1_INSN_CLIPU, MEPCORE1_INSN_SADD, MEPCORE1_INSN_SSUB, MEPCORE1_INSN_SADDU
- , MEPCORE1_INSN_SSUBU, MEPCORE1_INSN_SWCP, MEPCORE1_INSN_LWCP, MEPCORE1_INSN_SMCP
- , MEPCORE1_INSN_LMCP, MEPCORE1_INSN_SWCPI, MEPCORE1_INSN_LWCPI, MEPCORE1_INSN_SMCPI
- , MEPCORE1_INSN_LMCPI, MEPCORE1_INSN_SWCP16, MEPCORE1_INSN_LWCP16, MEPCORE1_INSN_SMCP16
- , MEPCORE1_INSN_LMCP16, MEPCORE1_INSN_SBCPA, MEPCORE1_INSN_LBCPA, MEPCORE1_INSN_SHCPA
- , MEPCORE1_INSN_LHCPA, MEPCORE1_INSN_SWCPA, MEPCORE1_INSN_LWCPA, MEPCORE1_INSN_SMCPA
- , MEPCORE1_INSN_LMCPA, MEPCORE1_INSN_SBCPM0, MEPCORE1_INSN_LBCPM0, MEPCORE1_INSN_SHCPM0
- , MEPCORE1_INSN_LHCPM0, MEPCORE1_INSN_SWCPM0, MEPCORE1_INSN_LWCPM0, MEPCORE1_INSN_SMCPM0
- , MEPCORE1_INSN_LMCPM0, MEPCORE1_INSN_SBCPM1, MEPCORE1_INSN_LBCPM1, MEPCORE1_INSN_SHCPM1
- , MEPCORE1_INSN_LHCPM1, MEPCORE1_INSN_SWCPM1, MEPCORE1_INSN_LWCPM1, MEPCORE1_INSN_SMCPM1
- , MEPCORE1_INSN_LMCPM1, MEPCORE1_INSN_BCPEQ, MEPCORE1_INSN_BCPNE, MEPCORE1_INSN_BCPAT
- , MEPCORE1_INSN_BCPAF, MEPCORE1_INSN_SYNCCP, MEPCORE1_INSN_JSRV, MEPCORE1_INSN_BSRV
- , MEPCORE1_INSN_SIM_SYSCALL, MEPCORE1_INSN_RI_0, MEPCORE1_INSN_RI_1, MEPCORE1_INSN_RI_2
- , MEPCORE1_INSN_RI_3, MEPCORE1_INSN_RI_4, MEPCORE1_INSN_RI_5, MEPCORE1_INSN_RI_6
- , MEPCORE1_INSN_RI_7, MEPCORE1_INSN_RI_8, MEPCORE1_INSN_RI_9, MEPCORE1_INSN_RI_10
- , MEPCORE1_INSN_RI_11, MEPCORE1_INSN_RI_12, MEPCORE1_INSN_RI_13, MEPCORE1_INSN_RI_14
- , MEPCORE1_INSN_RI_15, MEPCORE1_INSN_RI_17, MEPCORE1_INSN_RI_20, MEPCORE1_INSN_RI_21
- , MEPCORE1_INSN_RI_22, MEPCORE1_INSN_RI_23, MEPCORE1_INSN_RI_24, MEPCORE1_INSN_RI_25
- , MEPCORE1_INSN_RI_26, MEPCORE1_INSN_RI_16, MEPCORE1_INSN_RI_18, MEPCORE1_INSN_RI_19
+ MEPCORE1_INSN_X_INVALID, MEPCORE1_INSN_STCB_R, MEPCORE1_INSN_LDCB_R, MEPCORE1_INSN_PREF
+ , MEPCORE1_INSN_PREFD, MEPCORE1_INSN_CASB3, MEPCORE1_INSN_CASH3, MEPCORE1_INSN_CASW3
+ , MEPCORE1_INSN_SBCP, MEPCORE1_INSN_LBCP, MEPCORE1_INSN_LBUCP, MEPCORE1_INSN_SHCP
+ , MEPCORE1_INSN_LHCP, MEPCORE1_INSN_LHUCP, MEPCORE1_INSN_LBUCPA, MEPCORE1_INSN_LHUCPA
+ , MEPCORE1_INSN_LBUCPM0, MEPCORE1_INSN_LHUCPM0, MEPCORE1_INSN_LBUCPM1, MEPCORE1_INSN_LHUCPM1
+ , MEPCORE1_INSN_UCI, MEPCORE1_INSN_DSP, MEPCORE1_INSN_SB, MEPCORE1_INSN_SH
+ , MEPCORE1_INSN_SW, MEPCORE1_INSN_LB, MEPCORE1_INSN_LH, MEPCORE1_INSN_LW
+ , MEPCORE1_INSN_LBU, MEPCORE1_INSN_LHU, MEPCORE1_INSN_SW_SP, MEPCORE1_INSN_LW_SP
+ , MEPCORE1_INSN_SB_TP, MEPCORE1_INSN_SH_TP, MEPCORE1_INSN_SW_TP, MEPCORE1_INSN_LB_TP
+ , MEPCORE1_INSN_LH_TP, MEPCORE1_INSN_LW_TP, MEPCORE1_INSN_LBU_TP, MEPCORE1_INSN_LHU_TP
+ , MEPCORE1_INSN_SB16, MEPCORE1_INSN_SH16, MEPCORE1_INSN_SW16, MEPCORE1_INSN_LB16
+ , MEPCORE1_INSN_LH16, MEPCORE1_INSN_LW16, MEPCORE1_INSN_LBU16, MEPCORE1_INSN_LHU16
+ , MEPCORE1_INSN_SW24, MEPCORE1_INSN_LW24, MEPCORE1_INSN_EXTB, MEPCORE1_INSN_EXTH
+ , MEPCORE1_INSN_EXTUB, MEPCORE1_INSN_EXTUH, MEPCORE1_INSN_SSARB, MEPCORE1_INSN_MOV
+ , MEPCORE1_INSN_MOVI8, MEPCORE1_INSN_MOVI16, MEPCORE1_INSN_MOVU24, MEPCORE1_INSN_MOVU16
+ , MEPCORE1_INSN_MOVH, MEPCORE1_INSN_ADD3, MEPCORE1_INSN_ADD, MEPCORE1_INSN_ADD3I
+ , MEPCORE1_INSN_ADVCK3, MEPCORE1_INSN_SUB, MEPCORE1_INSN_SBVCK3, MEPCORE1_INSN_NEG
+ , MEPCORE1_INSN_SLT3, MEPCORE1_INSN_SLTU3, MEPCORE1_INSN_SLT3I, MEPCORE1_INSN_SLTU3I
+ , MEPCORE1_INSN_SL1AD3, MEPCORE1_INSN_SL2AD3, MEPCORE1_INSN_ADD3X, MEPCORE1_INSN_SLT3X
+ , MEPCORE1_INSN_SLTU3X, MEPCORE1_INSN_OR, MEPCORE1_INSN_AND, MEPCORE1_INSN_XOR
+ , MEPCORE1_INSN_NOR, MEPCORE1_INSN_OR3, MEPCORE1_INSN_AND3, MEPCORE1_INSN_XOR3
+ , MEPCORE1_INSN_SRA, MEPCORE1_INSN_SRL, MEPCORE1_INSN_SLL, MEPCORE1_INSN_SRAI
+ , MEPCORE1_INSN_SRLI, MEPCORE1_INSN_SLLI, MEPCORE1_INSN_SLL3, MEPCORE1_INSN_FSFT
+ , MEPCORE1_INSN_BRA, MEPCORE1_INSN_BEQZ, MEPCORE1_INSN_BNEZ, MEPCORE1_INSN_BEQI
+ , MEPCORE1_INSN_BNEI, MEPCORE1_INSN_BLTI, MEPCORE1_INSN_BGEI, MEPCORE1_INSN_BEQ
+ , MEPCORE1_INSN_BNE, MEPCORE1_INSN_BSR12, MEPCORE1_INSN_BSR24, MEPCORE1_INSN_JMP
+ , MEPCORE1_INSN_JMP24, MEPCORE1_INSN_JSR, MEPCORE1_INSN_RET, MEPCORE1_INSN_REPEAT
+ , MEPCORE1_INSN_EREPEAT, MEPCORE1_INSN_STC_LP, MEPCORE1_INSN_STC_HI, MEPCORE1_INSN_STC_LO
+ , MEPCORE1_INSN_STC, MEPCORE1_INSN_LDC_LP, MEPCORE1_INSN_LDC_HI, MEPCORE1_INSN_LDC_LO
+ , MEPCORE1_INSN_LDC, MEPCORE1_INSN_DI, MEPCORE1_INSN_EI, MEPCORE1_INSN_RETI
+ , MEPCORE1_INSN_HALT, MEPCORE1_INSN_SLEEP, MEPCORE1_INSN_SWI, MEPCORE1_INSN_BREAK
+ , MEPCORE1_INSN_SYNCM, MEPCORE1_INSN_STCB, MEPCORE1_INSN_LDCB, MEPCORE1_INSN_BSETM
+ , MEPCORE1_INSN_BCLRM, MEPCORE1_INSN_BNOTM, MEPCORE1_INSN_BTSTM, MEPCORE1_INSN_TAS
+ , MEPCORE1_INSN_CACHE, MEPCORE1_INSN_MUL, MEPCORE1_INSN_MULU, MEPCORE1_INSN_MULR
+ , MEPCORE1_INSN_MULRU, MEPCORE1_INSN_MADD, MEPCORE1_INSN_MADDU, MEPCORE1_INSN_MADDR
+ , MEPCORE1_INSN_MADDRU, MEPCORE1_INSN_DIV, MEPCORE1_INSN_DIVU, MEPCORE1_INSN_DRET
+ , MEPCORE1_INSN_DBREAK, MEPCORE1_INSN_LDZ, MEPCORE1_INSN_ABS, MEPCORE1_INSN_AVE
+ , MEPCORE1_INSN_MIN, MEPCORE1_INSN_MAX, MEPCORE1_INSN_MINU, MEPCORE1_INSN_MAXU
+ , MEPCORE1_INSN_CLIP, MEPCORE1_INSN_CLIPU, MEPCORE1_INSN_SADD, MEPCORE1_INSN_SSUB
+ , MEPCORE1_INSN_SADDU, MEPCORE1_INSN_SSUBU, MEPCORE1_INSN_SWCP, MEPCORE1_INSN_LWCP
+ , MEPCORE1_INSN_SMCP, MEPCORE1_INSN_LMCP, MEPCORE1_INSN_SWCPI, MEPCORE1_INSN_LWCPI
+ , MEPCORE1_INSN_SMCPI, MEPCORE1_INSN_LMCPI, MEPCORE1_INSN_SWCP16, MEPCORE1_INSN_LWCP16
+ , MEPCORE1_INSN_SMCP16, MEPCORE1_INSN_LMCP16, MEPCORE1_INSN_SBCPA, MEPCORE1_INSN_LBCPA
+ , MEPCORE1_INSN_SHCPA, MEPCORE1_INSN_LHCPA, MEPCORE1_INSN_SWCPA, MEPCORE1_INSN_LWCPA
+ , MEPCORE1_INSN_SMCPA, MEPCORE1_INSN_LMCPA, MEPCORE1_INSN_SBCPM0, MEPCORE1_INSN_LBCPM0
+ , MEPCORE1_INSN_SHCPM0, MEPCORE1_INSN_LHCPM0, MEPCORE1_INSN_SWCPM0, MEPCORE1_INSN_LWCPM0
+ , MEPCORE1_INSN_SMCPM0, MEPCORE1_INSN_LMCPM0, MEPCORE1_INSN_SBCPM1, MEPCORE1_INSN_LBCPM1
+ , MEPCORE1_INSN_SHCPM1, MEPCORE1_INSN_LHCPM1, MEPCORE1_INSN_SWCPM1, MEPCORE1_INSN_LWCPM1
+ , MEPCORE1_INSN_SMCPM1, MEPCORE1_INSN_LMCPM1, MEPCORE1_INSN_BCPEQ, MEPCORE1_INSN_BCPNE
+ , MEPCORE1_INSN_BCPAT, MEPCORE1_INSN_BCPAF, MEPCORE1_INSN_SYNCCP, MEPCORE1_INSN_JSRV
+ , MEPCORE1_INSN_BSRV, MEPCORE1_INSN_SIM_SYSCALL, MEPCORE1_INSN_RI_0, MEPCORE1_INSN_RI_1
+ , MEPCORE1_INSN_RI_2, MEPCORE1_INSN_RI_3, MEPCORE1_INSN_RI_4, MEPCORE1_INSN_RI_5
+ , MEPCORE1_INSN_RI_6, MEPCORE1_INSN_RI_7, MEPCORE1_INSN_RI_8, MEPCORE1_INSN_RI_9
+ , MEPCORE1_INSN_RI_10, MEPCORE1_INSN_RI_11, MEPCORE1_INSN_RI_12, MEPCORE1_INSN_RI_13
+ , MEPCORE1_INSN_RI_14, MEPCORE1_INSN_RI_15, MEPCORE1_INSN_RI_17, MEPCORE1_INSN_RI_20
+ , MEPCORE1_INSN_RI_21, MEPCORE1_INSN_RI_22, MEPCORE1_INSN_RI_23, MEPCORE1_INSN_RI_26
} MEPCORE1_INSN_TYPE;
unsigned char in_psw;
} sfmt_jmp24;
struct { /* */
- SI* i_rn;
- UINT f_16u16;
- UINT f_rn;
- unsigned char in_rn;
- } sfmt_stcb;
- struct { /* */
unsigned char in_epc;
unsigned char in_npc;
unsigned char in_opt;
} sfmt_sw_sp;
struct { /* */
SI* i_rma;
- SI* i_rn;
+ UINT f_12s20;
+ UINT f_crn;
UINT f_rm;
- UINT f_rn;
unsigned char in_rma;
- unsigned char out_rn;
- } sfmt_tas;
+ } sfmt_sbcp;
struct { /* */
SI* i_rm;
UINT f_rm;
unsigned char in_rn;
} sfmt_beqz;
struct { /* */
+ SI* i_rma;
+ SI* i_rn;
+ UINT f_rm;
+ UINT f_rn;
+ unsigned char in_rma;
+ unsigned char out_rn;
+ } sfmt_ldcb_r;
+ struct { /* */
+ SI* i_rma;
+ SI* i_rn;
+ UINT f_rm;
+ UINT f_rn;
+ unsigned char in_rma;
+ unsigned char in_rn;
+ } sfmt_stcb_r;
+ struct { /* */
SI* i_rn;
UINT f_csrn;
UINT f_rn;
struct { /* */
SI* i_rm;
SI* i_rn;
- UINT f_16u16;
- UINT f_rm;
- UINT f_rn;
- unsigned char in_rm;
- unsigned char out_rn;
- } sfmt_sltu3x;
- struct { /* */
- SI* i_rm;
- SI* i_rn;
INT f_16s16;
UINT f_rm;
UINT f_rn;
unsigned char in_rnc;
} sfmt_sb16;
struct { /* */
- SI* i_rma;
- SI f_8s24a8;
- UINT f_crn;
- UINT f_rm;
- unsigned char in_mb1;
- unsigned char in_me1;
- unsigned char in_rma;
- unsigned char out_rma;
- } sfmt_smcpm1;
- struct { /* */
- SI* i_rma;
- SI f_8s24a4;
- UINT f_crn;
+ SI* i_rm;
+ SI* i_rn;
UINT f_rm;
- unsigned char in_mb1;
- unsigned char in_me1;
- unsigned char in_rma;
- unsigned char out_rma;
- } sfmt_swcpm1;
+ UINT f_rn;
+ unsigned char in_rm;
+ unsigned char in_rn;
+ unsigned char in_sar;
+ unsigned char out_rn;
+ } sfmt_fsft;
struct { /* */
- SI* i_rma;
- SI f_8s24a2;
- UINT f_crn;
+ SI* i_rm;
+ SI* i_rn;
+ UINT f_16u16;
UINT f_rm;
- unsigned char in_mb1;
- unsigned char in_me1;
- unsigned char in_rma;
- unsigned char out_rma;
- } sfmt_shcpm1;
+ UINT f_rn;
+ unsigned char in_rm;
+ unsigned char in_rn;
+ unsigned char out_rn;
+ } sfmt_uci;
struct { /* */
SI* i_rma;
- INT f_8s24;
+ SI f_cdisp10;
UINT f_crn;
UINT f_rm;
unsigned char in_mb1;
unsigned char in_me1;
unsigned char in_rma;
unsigned char out_rma;
- } sfmt_sbcpm1;
+ } sfmt_lbucpm1;
struct { /* */
SI* i_rma;
- SI f_8s24a8;
+ SI f_cdisp10;
UINT f_crn;
UINT f_rm;
unsigned char in_mb0;
unsigned char in_me0;
unsigned char in_rma;
unsigned char out_rma;
- } sfmt_smcpm0;
- struct { /* */
- SI* i_rma;
- SI f_8s24a4;
- UINT f_crn;
- UINT f_rm;
- unsigned char in_mb0;
- unsigned char in_me0;
- unsigned char in_rma;
- unsigned char out_rma;
- } sfmt_swcpm0;
- struct { /* */
- SI* i_rma;
- SI f_8s24a2;
- UINT f_crn;
- UINT f_rm;
- unsigned char in_mb0;
- unsigned char in_me0;
- unsigned char in_rma;
- unsigned char out_rma;
- } sfmt_shcpm0;
- struct { /* */
- SI* i_rma;
- INT f_8s24;
- UINT f_crn;
- UINT f_rm;
- unsigned char in_mb0;
- unsigned char in_me0;
- unsigned char in_rma;
- unsigned char out_rma;
- } sfmt_sbcpm0;
- struct { /* */
- SI* i_rm;
- SI* i_rn;
- UINT f_rm;
- UINT f_rn;
- unsigned char in_rm;
- unsigned char in_rn;
- unsigned char in_sar;
- unsigned char out_rn;
- } sfmt_fsft;
+ } sfmt_lbucpm0;
struct { /* */
SI* i_rn;
SI f_17s16a2;
unsigned char out_rl;
} sfmt_add3;
struct { /* */
+ SI* i_rl5;
+ SI* i_rm;
+ SI* i_rn;
+ UINT f_rl5;
+ UINT f_rm;
+ UINT f_rn;
+ unsigned char in_rl5;
+ unsigned char in_rm;
+ unsigned char in_rn;
+ unsigned char out_rl5;
+ } sfmt_casb3;
+ struct { /* */
SI* i_rm;
SI* i_rn;
UINT f_rm;
using mep_ext1::mepcore1_sem_fn;
extern mepcore1_sem_fn mepcore1_sem_x_invalid;
+extern mepcore1_sem_fn mepcore1_sem_stcb_r;
+extern mepcore1_sem_fn mepcore1_sem_ldcb_r;
+extern mepcore1_sem_fn mepcore1_sem_pref;
+extern mepcore1_sem_fn mepcore1_sem_prefd;
+extern mepcore1_sem_fn mepcore1_sem_casb3;
+extern mepcore1_sem_fn mepcore1_sem_cash3;
+extern mepcore1_sem_fn mepcore1_sem_casw3;
+extern mepcore1_sem_fn mepcore1_sem_sbcp;
+extern mepcore1_sem_fn mepcore1_sem_lbcp;
+extern mepcore1_sem_fn mepcore1_sem_lbucp;
+extern mepcore1_sem_fn mepcore1_sem_shcp;
+extern mepcore1_sem_fn mepcore1_sem_lhcp;
+extern mepcore1_sem_fn mepcore1_sem_lhucp;
+extern mepcore1_sem_fn mepcore1_sem_lbucpa;
+extern mepcore1_sem_fn mepcore1_sem_lhucpa;
+extern mepcore1_sem_fn mepcore1_sem_lbucpm0;
+extern mepcore1_sem_fn mepcore1_sem_lhucpm0;
+extern mepcore1_sem_fn mepcore1_sem_lbucpm1;
+extern mepcore1_sem_fn mepcore1_sem_lhucpm1;
+extern mepcore1_sem_fn mepcore1_sem_uci;
+extern mepcore1_sem_fn mepcore1_sem_dsp;
extern mepcore1_sem_fn mepcore1_sem_sb;
extern mepcore1_sem_fn mepcore1_sem_sh;
extern mepcore1_sem_fn mepcore1_sem_sw;
extern mepcore1_sem_fn mepcore1_sem_ri_21;
extern mepcore1_sem_fn mepcore1_sem_ri_22;
extern mepcore1_sem_fn mepcore1_sem_ri_23;
-extern mepcore1_sem_fn mepcore1_sem_ri_24;
-extern mepcore1_sem_fn mepcore1_sem_ri_25;
extern mepcore1_sem_fn mepcore1_sem_ri_26;
-extern mepcore1_sem_fn mepcore1_sem_ri_16;
-extern mepcore1_sem_fn mepcore1_sem_ri_18;
-extern mepcore1_sem_fn mepcore1_sem_ri_19;
#endif /* MEPCORE1_DECODE_H */
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
This file is part of the Red Hat simulators.
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
This file is part of the Red Hat simulators.
}
UINT
+mepcore1_mep_model::model_stcb_r_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_stcb_r.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rn);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 1, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ {
+ cycles += model_u_stcb_before (current_cpu, idesc, 3);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_stcb_r_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_stcb_r.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rn);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 1, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_stcb_after (current_cpu, idesc, 3, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_ldcb_r_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_ldcb_before (current_cpu, idesc, 1);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ {
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rn);
+ cycles += model_u_ldcb_gpr_before (current_cpu, idesc, 3, out_loadreg);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_ldcb_r_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_ldcb_after (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rn);
+ cycles += model_u_ldcb_gpr_after (current_cpu, idesc, 3, referenced, out_loadreg);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_pref_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_pref_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_prefd_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lhu16.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_prefd_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lhu16.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_casb3_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rl5);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rl5);
+ cycles += model_u_load_gpr_before (current_cpu, idesc, 1, out_loadreg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_casb3_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rl5);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rl5);
+ cycles += model_u_load_gpr_after (current_cpu, idesc, 1, referenced, out_loadreg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_cash3_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rl5);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rl5);
+ cycles += model_u_load_gpr_before (current_cpu, idesc, 1, out_loadreg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_cash3_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rl5);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rl5);
+ cycles += model_u_load_gpr_after (current_cpu, idesc, 1, referenced, out_loadreg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_casw3_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rl5);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rl5);
+ cycles += model_u_load_gpr_before (current_cpu, idesc, 1, out_loadreg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_casw3_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rl5);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rl5);
+ cycles += model_u_load_gpr_after (current_cpu, idesc, 1, referenced, out_loadreg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_sbcp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_sbcp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lbcp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lbcp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lbucp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lbucp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_shcp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_shcp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lhcp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lhcp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lhucp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lhucp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lbucpa_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lbucpa_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lhucpa_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lhucpa_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lbucpm0_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lbucpm0_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lhucpm0_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lhucpm0_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lbucpm1_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lbucpm1_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lhucpm1_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_lhucpm1_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_uci_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_uci.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rm);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rn);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 1, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_uci_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_uci.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rm);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rn);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 1, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_dsp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_uci.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rm);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rn);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 1, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mepcore1_mep_model::model_dsp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_uci.f
+ const mepcore1_scache* abuf = sem;
+ const mepcore1_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rm);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rn);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 1, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
mepcore1_mep_model::model_sb_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
#define FLD(f) abuf->fields.sfmt_sb16.f
UINT
mepcore1_mep_model::model_mov_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_mov_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_movu16_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_movu16_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_movh_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_movh_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_neg_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_neg_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_sltu3x_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_sltu3x_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_or3_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_or3_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_and3_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_and3_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_xor3_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_xor3_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_stcb_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_stcb.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_stcb_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_stcb.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_ldcb_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_ldcb_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_tas_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_tas_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_cache_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_cache_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_ldz_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_ldz_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_swcpi_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_swcpi_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lwcpi_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lwcpi_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_smcpi_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_smcpi_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lmcpi_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lmcpi_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_sbcpa_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_sbcpa_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lbcpa_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lbcpa_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_shcpa_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_shcpa_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lhcpa_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lhcpa_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_swcpa_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_swcpa_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lwcpa_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lwcpa_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_smcpa_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_smcpa_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lmcpa_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lmcpa_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_sbcpm0_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_sbcpm0_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lbcpm0_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lbcpm0_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_shcpm0_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_shcpm0_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lhcpm0_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lhcpm0_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_swcpm0_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_swcpm0_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lwcpm0_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lwcpm0_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_smcpm0_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_smcpm0_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lmcpm0_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lmcpm0_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_sbcpm1_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_sbcpm1_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lbcpm1_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lbcpm1_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_shcpm1_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_shcpm1_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lhcpm1_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lhcpm1_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_swcpm1_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_swcpm1_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lwcpm1_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lwcpm1_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_smcpm1_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_smcpm1_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lmcpm1_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mepcore1_mep_model::model_lmcpm1_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mepcore1_scache* abuf = sem;
const mepcore1_idesc* idesc = abuf->idesc;
int cycles = 0;
}
UINT
-mepcore1_mep_model::model_ri_24_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mepcore1_scache* abuf = sem;
- const mepcore1_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- cycles += model_u_exec_before (current_cpu, idesc, 0);
- }
- {
- cycles += model_u_branch_before (current_cpu, idesc, 1);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mepcore1_mep_model::model_ri_24_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mepcore1_scache* abuf = sem;
- const mepcore1_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- cycles += model_u_exec_after (current_cpu, idesc, 0, referenced);
- }
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- referenced |= 1 << 0;
- cycles += model_u_branch_after (current_cpu, idesc, 1, referenced);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mepcore1_mep_model::model_ri_25_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mepcore1_scache* abuf = sem;
- const mepcore1_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- cycles += model_u_exec_before (current_cpu, idesc, 0);
- }
- {
- cycles += model_u_branch_before (current_cpu, idesc, 1);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mepcore1_mep_model::model_ri_25_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mepcore1_scache* abuf = sem;
- const mepcore1_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- cycles += model_u_exec_after (current_cpu, idesc, 0, referenced);
- }
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- referenced |= 1 << 0;
- cycles += model_u_branch_after (current_cpu, idesc, 1, referenced);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
mepcore1_mep_model::model_ri_26_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
{
#define FLD(f) abuf->fields.fmt_empty.f
#undef FLD
}
-UINT
-mepcore1_mep_model::model_ri_16_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mepcore1_scache* abuf = sem;
- const mepcore1_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- cycles += model_u_exec_before (current_cpu, idesc, 0);
- }
- {
- cycles += model_u_branch_before (current_cpu, idesc, 1);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mepcore1_mep_model::model_ri_16_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mepcore1_scache* abuf = sem;
- const mepcore1_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- cycles += model_u_exec_after (current_cpu, idesc, 0, referenced);
- }
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- referenced |= 1 << 0;
- cycles += model_u_branch_after (current_cpu, idesc, 1, referenced);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mepcore1_mep_model::model_ri_18_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mepcore1_scache* abuf = sem;
- const mepcore1_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- cycles += model_u_exec_before (current_cpu, idesc, 0);
- }
- {
- cycles += model_u_branch_before (current_cpu, idesc, 1);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mepcore1_mep_model::model_ri_18_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mepcore1_scache* abuf = sem;
- const mepcore1_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- cycles += model_u_exec_after (current_cpu, idesc, 0, referenced);
- }
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- referenced |= 1 << 0;
- cycles += model_u_branch_after (current_cpu, idesc, 1, referenced);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mepcore1_mep_model::model_ri_19_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mepcore1_scache* abuf = sem;
- const mepcore1_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- cycles += model_u_exec_before (current_cpu, idesc, 0);
- }
- {
- cycles += model_u_branch_before (current_cpu, idesc, 1);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mepcore1_mep_model::model_ri_19_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mepcore1_scache* abuf = sem;
- const mepcore1_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- cycles += model_u_exec_after (current_cpu, idesc, 0, referenced);
- }
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- referenced |= 1 << 0;
- cycles += model_u_branch_after (current_cpu, idesc, 1, referenced);
- }
- return cycles;
-#undef FLD
-}
-
/* We assume UNIT_NONE == 0 because the tables don't always terminate
entries with it. */
const mepcore1_mep_model::insn_timing mepcore1_mep_model::timing[] = {
{ MEPCORE1_INSN_X_INVALID, 0, 0, { { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_STCB_R, & mepcore1_mep_model::model_stcb_r_before, & mepcore1_mep_model::model_stcb_r_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 }, { mepcore1_mep_model::UNIT_U_STCB, 0, 0 } } },
+ { MEPCORE1_INSN_LDCB_R, & mepcore1_mep_model::model_ldcb_r_before, & mepcore1_mep_model::model_ldcb_r_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_LDCB, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 }, { mepcore1_mep_model::UNIT_U_LDCB_GPR, 0, 0 } } },
+ { MEPCORE1_INSN_PREF, & mepcore1_mep_model::model_pref_before, & mepcore1_mep_model::model_pref_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_PREFD, & mepcore1_mep_model::model_prefd_before, & mepcore1_mep_model::model_prefd_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_CASB3, & mepcore1_mep_model::model_casb3_before, & mepcore1_mep_model::model_casb3_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_LOAD_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_CASH3, & mepcore1_mep_model::model_cash3_before, & mepcore1_mep_model::model_cash3_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_LOAD_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_CASW3, & mepcore1_mep_model::model_casw3_before, & mepcore1_mep_model::model_casw3_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_LOAD_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_SBCP, & mepcore1_mep_model::model_sbcp_before, & mepcore1_mep_model::model_sbcp_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_LBCP, & mepcore1_mep_model::model_lbcp_before, & mepcore1_mep_model::model_lbcp_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_LBUCP, & mepcore1_mep_model::model_lbucp_before, & mepcore1_mep_model::model_lbucp_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_SHCP, & mepcore1_mep_model::model_shcp_before, & mepcore1_mep_model::model_shcp_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_LHCP, & mepcore1_mep_model::model_lhcp_before, & mepcore1_mep_model::model_lhcp_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_LHUCP, & mepcore1_mep_model::model_lhucp_before, & mepcore1_mep_model::model_lhucp_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_LBUCPA, & mepcore1_mep_model::model_lbucpa_before, & mepcore1_mep_model::model_lbucpa_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_LHUCPA, & mepcore1_mep_model::model_lhucpa_before, & mepcore1_mep_model::model_lhucpa_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_LBUCPM0, & mepcore1_mep_model::model_lbucpm0_before, & mepcore1_mep_model::model_lbucpm0_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_LHUCPM0, & mepcore1_mep_model::model_lhucpm0_before, & mepcore1_mep_model::model_lhucpm0_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_LBUCPM1, & mepcore1_mep_model::model_lbucpm1_before, & mepcore1_mep_model::model_lbucpm1_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_LHUCPM1, & mepcore1_mep_model::model_lhucpm1_before, & mepcore1_mep_model::model_lhucpm1_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_UCI, & mepcore1_mep_model::model_uci_before, & mepcore1_mep_model::model_uci_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEPCORE1_INSN_DSP, & mepcore1_mep_model::model_dsp_before, & mepcore1_mep_model::model_dsp_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
{ MEPCORE1_INSN_SB, & mepcore1_mep_model::model_sb_before, & mepcore1_mep_model::model_sb_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
{ MEPCORE1_INSN_SH, & mepcore1_mep_model::model_sh_before, & mepcore1_mep_model::model_sh_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
{ MEPCORE1_INSN_SW, & mepcore1_mep_model::model_sw_before, & mepcore1_mep_model::model_sw_after, { { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 } } },
{ MEPCORE1_INSN_RI_21, & mepcore1_mep_model::model_ri_21_before, & mepcore1_mep_model::model_ri_21_after, { { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 }, { mepcore1_mep_model::UNIT_U_BRANCH, 0, 0 } } },
{ MEPCORE1_INSN_RI_22, & mepcore1_mep_model::model_ri_22_before, & mepcore1_mep_model::model_ri_22_after, { { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 }, { mepcore1_mep_model::UNIT_U_BRANCH, 0, 0 } } },
{ MEPCORE1_INSN_RI_23, & mepcore1_mep_model::model_ri_23_before, & mepcore1_mep_model::model_ri_23_after, { { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 }, { mepcore1_mep_model::UNIT_U_BRANCH, 0, 0 } } },
- { MEPCORE1_INSN_RI_24, & mepcore1_mep_model::model_ri_24_before, & mepcore1_mep_model::model_ri_24_after, { { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 }, { mepcore1_mep_model::UNIT_U_BRANCH, 0, 0 } } },
- { MEPCORE1_INSN_RI_25, & mepcore1_mep_model::model_ri_25_before, & mepcore1_mep_model::model_ri_25_after, { { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 }, { mepcore1_mep_model::UNIT_U_BRANCH, 0, 0 } } },
{ MEPCORE1_INSN_RI_26, & mepcore1_mep_model::model_ri_26_before, & mepcore1_mep_model::model_ri_26_after, { { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 }, { mepcore1_mep_model::UNIT_U_BRANCH, 0, 0 } } },
- { MEPCORE1_INSN_RI_16, & mepcore1_mep_model::model_ri_16_before, & mepcore1_mep_model::model_ri_16_after, { { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 }, { mepcore1_mep_model::UNIT_U_BRANCH, 0, 0 } } },
- { MEPCORE1_INSN_RI_18, & mepcore1_mep_model::model_ri_18_before, & mepcore1_mep_model::model_ri_18_after, { { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 }, { mepcore1_mep_model::UNIT_U_BRANCH, 0, 0 } } },
- { MEPCORE1_INSN_RI_19, & mepcore1_mep_model::model_ri_19_before, & mepcore1_mep_model::model_ri_19_after, { { mepcore1_mep_model::UNIT_U_EXEC, 1, 1 }, { mepcore1_mep_model::UNIT_U_BRANCH, 0, 0 } } },
};
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
This file is part of the Red Hat simulators.
protected:
// These methods call the appropriate unit modeller(s) for each insn.
+ UINT model_stcb_r_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_stcb_r_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_ldcb_r_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_ldcb_r_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_pref_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_pref_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_prefd_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_prefd_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_casb3_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_casb3_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_cash3_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_cash3_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_casw3_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_casw3_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_sbcp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_sbcp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lbcp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lbcp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lbucp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lbucp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_shcp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_shcp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lhcp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lhcp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lhucp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lhucp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lbucpa_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lbucpa_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lhucpa_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lhucpa_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lbucpm0_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lbucpm0_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lhucpm0_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lhucpm0_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lbucpm1_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lbucpm1_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lhucpm1_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_lhucpm1_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_uci_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_uci_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_dsp_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
+ UINT model_dsp_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
UINT model_sb_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
UINT model_sb_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
UINT model_sh_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
UINT model_ri_22_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
UINT model_ri_23_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
UINT model_ri_23_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
- UINT model_ri_24_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
- UINT model_ri_24_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
- UINT model_ri_25_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
- UINT model_ri_25_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
UINT model_ri_26_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
UINT model_ri_26_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
- UINT model_ri_16_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
- UINT model_ri_16_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
- UINT model_ri_18_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
- UINT model_ri_18_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
- UINT model_ri_19_before (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
- UINT model_ri_19_after (mep_ext1_cpu *current_cpu, mepcore1_scache *sem);
/* Enum declaration for unit types. */
typedef enum unit_number {
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
This file is part of the Red Hat simulators.
#undef FLD
}
+// ********** stcb_r: stcb $rn,($rma)
+
+sem_status
+mepcore1_sem_stcb_r (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_stcb_r.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 2;
+
+current_cpu->do_stcb (* FLD (i_rn), ANDSI (* FLD (i_rma), 65535));
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** ldcb_r: ldcb $rn,($rma)
+
+sem_status
+mepcore1_sem_ldcb_r (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 2;
+
+ {
+ SI opval = current_cpu->do_ldcb (ANDSI (* FLD (i_rma), 65535));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rn) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rn) = opval;
+ }
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** pref: pref $cimm4,($rma)
+
+sem_status
+mepcore1_sem_pref (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 2;
+
+{
+current_cpu->check_option_dcache (pc);
+current_cpu->do_cache_prefetch (FLD (f_rn), * FLD (i_rma), pc);
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** prefd: pref $cimm4,$sdisp16($rma)
+
+sem_status
+mepcore1_sem_prefd (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lhu16.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_dcache (pc);
+current_cpu->do_cache_prefetch (FLD (f_rn), ADDSI (* FLD (i_rma), EXTSISI (FLD (f_16s16))), pc);
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** casb3: casb3 $rl5,$rn,($rm)
+
+sem_status
+mepcore1_sem_casb3 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->do_casb3 (FLD (f_rl5), * FLD (i_rn), * FLD (i_rm), pc);
+ {
+ SI opval = * FLD (i_rl5);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rl5) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rl5) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** cash3: cash3 $rl5,$rn,($rm)
+
+sem_status
+mepcore1_sem_cash3 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->do_cash3 (FLD (f_rl5), * FLD (i_rn), * FLD (i_rm), pc);
+ {
+ SI opval = * FLD (i_rl5);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rl5) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rl5) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** casw3: casw3 $rl5,$rn,($rm)
+
+sem_status
+mepcore1_sem_casw3 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->do_casw3 (FLD (f_rl5), * FLD (i_rn), * FLD (i_rm), pc);
+ {
+ SI opval = * FLD (i_rl5);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rl5) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rl5) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** sbcp: sbcp $crn,$cdisp12($rma)
+
+sem_status
+mepcore1_sem_sbcp (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+current_cpu->check_write_to_text (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20))));
+ {
+ QI opval = ANDSI (current_cpu->h_cr_get (FLD (f_crn)), 255);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "memory" << '[' << "0x" << hex << (UDI) ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20))) << dec << ']' << ":=0x" << hex << (SI) opval << dec << " ";
+ current_cpu->SETMEMQI (pc, ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20))), opval);
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lbcp: lbcp $crn,$cdisp12($rma)
+
+sem_status
+mepcore1_sem_lbcp (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = EXTQISI (current_cpu->GETMEMQI (pc, ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20)))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lbucp: lbucp $crn,$cdisp12($rma)
+
+sem_status
+mepcore1_sem_lbucp (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTQISI (current_cpu->GETMEMQI (pc, ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20)))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** shcp: shcp $crn,$cdisp12($rma)
+
+sem_status
+mepcore1_sem_shcp (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+current_cpu->check_write_to_text (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20))));
+ {
+ HI opval = ANDSI (current_cpu->h_cr_get (FLD (f_crn)), 65535);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "memory" << '[' << "0x" << hex << (UDI) ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20))) << dec << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->SETMEMHI (pc, ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20))), opval);
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lhcp: lhcp $crn,$cdisp12($rma)
+
+sem_status
+mepcore1_sem_lhcp (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = EXTHISI (current_cpu->GETMEMHI (pc, ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20)))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lhucp: lhucp $crn,$cdisp12($rma)
+
+sem_status
+mepcore1_sem_lhucp (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTHISI (current_cpu->GETMEMHI (pc, ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20)))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lbucpa: lbucpa $crn,($rma+),$cdisp10
+
+sem_status
+mepcore1_sem_lbucpa (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTQISI (current_cpu->GETMEMQI (pc, * FLD (i_rma)));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+ {
+ SI opval = ADDSI (* FLD (i_rma), FLD (f_cdisp10));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rma) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lhucpa: lhucpa $crn,($rma+),$cdisp10a2
+
+sem_status
+mepcore1_sem_lhucpa (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTHISI (current_cpu->GETMEMHI (pc, ANDSI (* FLD (i_rma), INVSI (1))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+ {
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rma) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lbucpm0: lbucpm0 $crn,($rma+),$cdisp10
+
+sem_status
+mepcore1_sem_lbucpm0 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTQISI (current_cpu->GETMEMQI (pc, * FLD (i_rma)));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+ {
+ SI opval = ({ SI tmp_modulo_mask;
+ tmp_modulo_mask = ({ SI tmp_temp;
+ tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
+; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rma) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lhucpm0: lhucpm0 $crn,($rma+),$cdisp10a2
+
+sem_status
+mepcore1_sem_lhucpm0 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTHISI (current_cpu->GETMEMHI (pc, ANDSI (* FLD (i_rma), INVSI (1))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+ {
+ SI opval = ({ SI tmp_modulo_mask;
+ tmp_modulo_mask = ({ SI tmp_temp;
+ tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
+; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rma) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lbucpm1: lbucpm1 $crn,($rma+),$cdisp10
+
+sem_status
+mepcore1_sem_lbucpm1 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTQISI (current_cpu->GETMEMQI (pc, * FLD (i_rma)));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+ {
+ SI opval = ({ SI tmp_modulo_mask;
+ tmp_modulo_mask = ({ SI tmp_temp;
+ tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
+; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rma) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lhucpm1: lhucpm1 $crn,($rma+),$cdisp10a2
+
+sem_status
+mepcore1_sem_lhucpm1 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTHISI (current_cpu->GETMEMHI (pc, ANDSI (* FLD (i_rma), INVSI (1))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+ {
+ SI opval = ({ SI tmp_modulo_mask;
+ tmp_modulo_mask = ({ SI tmp_temp;
+ tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
+; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rma) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** uci: uci $rn,$rm,$uimm16
+
+sem_status
+mepcore1_sem_uci (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_uci.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+ {
+ SI opval = current_cpu->do_UCI (* FLD (i_rn), * FLD (i_rm), ZEXTSISI (FLD (f_16u16)), pc);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rn) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rn) = opval;
+ }
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** dsp: dsp $rn,$rm,$uimm16
+
+sem_status
+mepcore1_sem_dsp (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_uci.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcore1_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+ {
+ SI opval = current_cpu->do_DSP (* FLD (i_rn), * FLD (i_rm), ZEXTSISI (FLD (f_16u16)), pc);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rn) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rn) = opval;
+ }
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
// ********** sb: sb $rnc,($rma)
sem_status
sem_status
mepcore1_sem_mov (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_movu16 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_movh (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_neg (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_sltu3x (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_or3 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_and3 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_xor3 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_stcb (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_stcb.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_ldcb (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_tas (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_cache (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_ldz (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_swcpi (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_lwcpi (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_smcpi (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mepcore1_sem_lmcpi (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
#undef FLD
}
-// ********** sbcpa: sbcpa $crn,($rma+),$cdisp8
+// ********** sbcpa: sbcpa $crn,($rma+),$cdisp10
sem_status
mepcore1_sem_sbcpa (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->SETMEMQI (pc, * FLD (i_rma), opval);
}
{
- SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24)));
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lbcpa: lbcpa $crn,($rma+),$cdisp8
+// ********** lbcpa: lbcpa $crn,($rma+),$cdisp10
sem_status
mepcore1_sem_lbcpa (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->h_cr_set (FLD (f_crn), opval);
}
{
- SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24)));
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** shcpa: shcpa $crn,($rma+),$cdisp8a2
+// ********** shcpa: shcpa $crn,($rma+),$cdisp10a2
sem_status
mepcore1_sem_shcpa (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->SETMEMHI (pc, ANDSI (* FLD (i_rma), INVSI (1)), opval);
}
{
- SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a2)));
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lhcpa: lhcpa $crn,($rma+),$cdisp8a2
+// ********** lhcpa: lhcpa $crn,($rma+),$cdisp10a2
sem_status
mepcore1_sem_lhcpa (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->h_cr_set (FLD (f_crn), opval);
}
{
- SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a2)));
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** swcpa: swcpa $crn,($rma+),$cdisp8a4
+// ********** swcpa: swcpa $crn,($rma+),$cdisp10a4
sem_status
mepcore1_sem_swcpa (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->SETMEMSI (pc, ANDSI (* FLD (i_rma), INVSI (3)), opval);
}
{
- SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a4)));
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lwcpa: lwcpa $crn,($rma+),$cdisp8a4
+// ********** lwcpa: lwcpa $crn,($rma+),$cdisp10a4
sem_status
mepcore1_sem_lwcpa (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->h_cr_set (FLD (f_crn), opval);
}
{
- SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a4)));
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** smcpa: smcpa $crn64,($rma+),$cdisp8a8
+// ********** smcpa: smcpa $crn64,($rma+),$cdisp10a8
sem_status
mepcore1_sem_smcpa (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->check_option_cp (pc);
current_cpu->check_option_cp64 (pc);
current_cpu->check_write_to_text (* FLD (i_rma));
-current_cpu->do_smcpa (FLD (f_rm), FLD (f_8s24a8), current_cpu->hardware.h_cr64[FLD (f_crn)], pc);
+current_cpu->do_smcpa (FLD (f_rm), FLD (f_cdisp10), current_cpu->hardware.h_cr64[FLD (f_crn)], pc);
{
SI opval = * FLD (i_rma);
if (UNLIKELY(current_cpu->trace_result_p))
#undef FLD
}
-// ********** lmcpa: lmcpa $crn64,($rma+),$cdisp8a8
+// ********** lmcpa: lmcpa $crn64,($rma+),$cdisp10a8
sem_status
mepcore1_sem_lmcpa (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->check_option_cp (pc);
current_cpu->check_option_cp64 (pc);
{
- DI opval = current_cpu->do_lmcpa (FLD (f_rm), FLD (f_8s24a8), pc);
+ DI opval = current_cpu->do_lmcpa (FLD (f_rm), FLD (f_cdisp10), pc);
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "cr64" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
current_cpu->hardware.h_cr64[FLD (f_crn)] = opval;
#undef FLD
}
-// ********** sbcpm0: sbcpm0 $crn,($rma+),$cdisp8
+// ********** sbcpm0: sbcpm0 $crn,($rma+),$cdisp10
sem_status
mepcore1_sem_sbcpm0 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lbcpm0: lbcpm0 $crn,($rma+),$cdisp8
+// ********** lbcpm0: lbcpm0 $crn,($rma+),$cdisp10
sem_status
mepcore1_sem_lbcpm0 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** shcpm0: shcpm0 $crn,($rma+),$cdisp8a2
+// ********** shcpm0: shcpm0 $crn,($rma+),$cdisp10a2
sem_status
mepcore1_sem_shcpm0 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a2))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lhcpm0: lhcpm0 $crn,($rma+),$cdisp8a2
+// ********** lhcpm0: lhcpm0 $crn,($rma+),$cdisp10a2
sem_status
mepcore1_sem_lhcpm0 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a2))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** swcpm0: swcpm0 $crn,($rma+),$cdisp8a4
+// ********** swcpm0: swcpm0 $crn,($rma+),$cdisp10a4
sem_status
mepcore1_sem_swcpm0 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a4))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lwcpm0: lwcpm0 $crn,($rma+),$cdisp8a4
+// ********** lwcpm0: lwcpm0 $crn,($rma+),$cdisp10a4
sem_status
mepcore1_sem_lwcpm0 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a4))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** smcpm0: smcpm0 $crn64,($rma+),$cdisp8a8
+// ********** smcpm0: smcpm0 $crn64,($rma+),$cdisp10a8
sem_status
mepcore1_sem_smcpm0 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a8))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lmcpm0: lmcpm0 $crn64,($rma+),$cdisp8a8
+// ********** lmcpm0: lmcpm0 $crn64,($rma+),$cdisp10a8
sem_status
mepcore1_sem_lmcpm0 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a8))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** sbcpm1: sbcpm1 $crn,($rma+),$cdisp8
+// ********** sbcpm1: sbcpm1 $crn,($rma+),$cdisp10
sem_status
mepcore1_sem_sbcpm1 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lbcpm1: lbcpm1 $crn,($rma+),$cdisp8
+// ********** lbcpm1: lbcpm1 $crn,($rma+),$cdisp10
sem_status
mepcore1_sem_lbcpm1 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** shcpm1: shcpm1 $crn,($rma+),$cdisp8a2
+// ********** shcpm1: shcpm1 $crn,($rma+),$cdisp10a2
sem_status
mepcore1_sem_shcpm1 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a2))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lhcpm1: lhcpm1 $crn,($rma+),$cdisp8a2
+// ********** lhcpm1: lhcpm1 $crn,($rma+),$cdisp10a2
sem_status
mepcore1_sem_lhcpm1 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a2))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** swcpm1: swcpm1 $crn,($rma+),$cdisp8a4
+// ********** swcpm1: swcpm1 $crn,($rma+),$cdisp10a4
sem_status
mepcore1_sem_swcpm1 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a4))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lwcpm1: lwcpm1 $crn,($rma+),$cdisp8a4
+// ********** lwcpm1: lwcpm1 $crn,($rma+),$cdisp10a4
sem_status
mepcore1_sem_lwcpm1 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a4))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** smcpm1: smcpm1 $crn64,($rma+),$cdisp8a8
+// ********** smcpm1: smcpm1 $crn64,($rma+),$cdisp10a8
sem_status
mepcore1_sem_smcpm1 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a8))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lmcpm1: lmcpm1 $crn64,($rma+),$cdisp8a8
+// ********** lmcpm1: lmcpm1 $crn64,($rma+),$cdisp10a8
sem_status
mepcore1_sem_lmcpm1 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mepcore1_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a8))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** ri-24: --reserved--
-
-sem_status
-mepcore1_sem_ri_24 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- sem_status status = SEM_STATUS_NORMAL;
- mepcore1_scache* abuf = sem;
- unsigned long long written = 0;
- PCADDR pc = abuf->addr;
- PCADDR npc = pc + 2;
-
- {
- USI opval = current_cpu->ri_exception (pc);
- if (UNLIKELY(current_cpu->trace_result_p))
- current_cpu->trace_stream << "pc" << ":=0x" << hex << opval << dec << " ";
- current_cpu->branch (opval, npc, status);
- }
-
- current_cpu->done_cti_insn (npc, status);
- return status;
-#undef FLD
-}
-
-// ********** ri-25: --reserved--
-
-sem_status
-mepcore1_sem_ri_25 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- sem_status status = SEM_STATUS_NORMAL;
- mepcore1_scache* abuf = sem;
- unsigned long long written = 0;
- PCADDR pc = abuf->addr;
- PCADDR npc = pc + 2;
-
- {
- USI opval = current_cpu->ri_exception (pc);
- if (UNLIKELY(current_cpu->trace_result_p))
- current_cpu->trace_stream << "pc" << ":=0x" << hex << opval << dec << " ";
- current_cpu->branch (opval, npc, status);
- }
-
- current_cpu->done_cti_insn (npc, status);
- return status;
-#undef FLD
-}
-
// ********** ri-26: --reserved--
sem_status
#undef FLD
}
-// ********** ri-16: --reserved--
-
-sem_status
-mepcore1_sem_ri_16 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- sem_status status = SEM_STATUS_NORMAL;
- mepcore1_scache* abuf = sem;
- unsigned long long written = 0;
- PCADDR pc = abuf->addr;
- PCADDR npc = pc + 2;
-
- {
- USI opval = current_cpu->ri_exception (pc);
- if (UNLIKELY(current_cpu->trace_result_p))
- current_cpu->trace_stream << "pc" << ":=0x" << hex << opval << dec << " ";
- current_cpu->branch (opval, npc, status);
- }
-
- current_cpu->done_cti_insn (npc, status);
- return status;
-#undef FLD
-}
-
-// ********** ri-18: --reserved--
-
-sem_status
-mepcore1_sem_ri_18 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- sem_status status = SEM_STATUS_NORMAL;
- mepcore1_scache* abuf = sem;
- unsigned long long written = 0;
- PCADDR pc = abuf->addr;
- PCADDR npc = pc + 2;
-
- {
- USI opval = current_cpu->ri_exception (pc);
- if (UNLIKELY(current_cpu->trace_result_p))
- current_cpu->trace_stream << "pc" << ":=0x" << hex << opval << dec << " ";
- current_cpu->branch (opval, npc, status);
- }
-
- current_cpu->done_cti_insn (npc, status);
- return status;
-#undef FLD
-}
-
-// ********** ri-19: --reserved--
-
-sem_status
-mepcore1_sem_ri_19 (mep_ext1_cpu* current_cpu, mepcore1_scache* sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- sem_status status = SEM_STATUS_NORMAL;
- mepcore1_scache* abuf = sem;
- unsigned long long written = 0;
- PCADDR pc = abuf->addr;
- PCADDR npc = pc + 2;
-
- {
- USI opval = current_cpu->ri_exception (pc);
- if (UNLIKELY(current_cpu->trace_result_p))
- current_cpu->trace_stream << "pc" << ":=0x" << hex << opval << dec << " ";
- current_cpu->branch (opval, npc, status);
- }
-
- current_cpu->done_cti_insn (npc, status);
- return status;
-#undef FLD
-}
-
// The instruction descriptor array.
-mep_idesc mep_idesc::idesc_table[MEP_INSN_RI_19 + 1] =
+mep_idesc mep_idesc::idesc_table[MEP_INSN_RI_26 + 1] =
{
{ mep_sem_x_invalid, "X_INVALID", MEP_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x80" }, 0, CONFIG_NONE } },
+ { mep_sem_stcb_r, "STCB_R", MEP_INSN_STCB_R, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_ldcb_r, "LDCB_R", MEP_INSN_LDCB_R, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 3, CONFIG_NONE } },
+ { mep_sem_pref, "PREF", MEP_INSN_PREF, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_prefd, "PREFD", MEP_INSN_PREFD, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_casb3, "CASB3", MEP_INSN_CASB3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_cash3, "CASH3", MEP_INSN_CASH3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_casw3, "CASW3", MEP_INSN_CASW3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_sbcp, "SBCP", MEP_INSN_SBCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_lbcp, "LBCP", MEP_INSN_LBCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_lbucp, "LBUCP", MEP_INSN_LBUCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_shcp, "SHCP", MEP_INSN_SHCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_lhcp, "LHCP", MEP_INSN_LHCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_lhucp, "LHUCP", MEP_INSN_LHUCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_lbucpa, "LBUCPA", MEP_INSN_LBUCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_lhucpa, "LHUCPA", MEP_INSN_LHUCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_lbucpm0, "LBUCPM0", MEP_INSN_LBUCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_lhucpm0, "LHUCPM0", MEP_INSN_LHUCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_lbucpm1, "LBUCPM1", MEP_INSN_LBUCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_lhucpm1, "LHUCPM1", MEP_INSN_LHUCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_uci, "UCI", MEP_INSN_UCI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
+ { mep_sem_dsp, "DSP", MEP_INSN_DSP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mep_sem_sb, "SB", MEP_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mep_sem_sh, "SH", MEP_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mep_sem_sw, "SW", MEP_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mep_sem_ri_21, "RI_21", MEP_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mep_sem_ri_22, "RI_22", MEP_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mep_sem_ri_23, "RI_23", MEP_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
- { mep_sem_ri_24, "RI_24", MEP_INSN_RI_24, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
- { mep_sem_ri_25, "RI_25", MEP_INSN_RI_25, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
{ mep_sem_ri_26, "RI_26", MEP_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
- { mep_sem_ri_16, "RI_16", MEP_INSN_RI_16, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
- { mep_sem_ri_18, "RI_18", MEP_INSN_RI_18, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
- { mep_sem_ri_19, "RI_19", MEP_INSN_RI_19, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
};
static void
mep_extract_sfmt_empty (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
+mep_extract_sfmt_stcb_r (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_ldcb_r (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_pref (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_prefd (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_casb3 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_sbcp (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_lbcp (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_shcp (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_lhcp (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_lbucpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_lhucpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_lbucpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_lhucpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_lbucpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_lhucpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
+mep_extract_sfmt_uci (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
+static void
mep_extract_sfmt_sb (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
mep_extract_sfmt_sh (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
mep_extract_sfmt_tas (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
-mep_extract_sfmt_cache (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
-static void
mep_extract_sfmt_mul (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
mep_extract_sfmt_mulr (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
mep_extract_sfmt_sbcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
-mep_extract_sfmt_lbcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
-static void
mep_extract_sfmt_shcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
-mep_extract_sfmt_lhcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
-static void
mep_extract_sfmt_swcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
mep_extract_sfmt_lwcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
mep_extract_sfmt_sbcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
-mep_extract_sfmt_lbcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
-static void
mep_extract_sfmt_shcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
-mep_extract_sfmt_lhcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
-static void
mep_extract_sfmt_swcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
mep_extract_sfmt_lwcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
mep_extract_sfmt_sbcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
-mep_extract_sfmt_lbcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
-static void
mep_extract_sfmt_shcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
-mep_extract_sfmt_lhcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
-static void
mep_extract_sfmt_swcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
static void
mep_extract_sfmt_lwcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn);
case 116 :
entire_insn = entire_insn >> 16;
if ((entire_insn & 0xf00f) == 0x7004)
- { itype = MEP_INSN_CACHE; mep_extract_sfmt_cache (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEP_INSN_CACHE; mep_extract_sfmt_pref (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 117 :
entire_insn = entire_insn >> 16;
if ((entire_insn & 0xf00f) == 0x7005)
- { itype = MEP_INSN_RI_16; mep_extract_sfmt_break (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEP_INSN_PREF; mep_extract_sfmt_pref (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 118 :
entire_insn = entire_insn >> 16;
case 124 :
entire_insn = entire_insn >> 16;
if ((entire_insn & 0xf00f) == 0x700c)
- { itype = MEP_INSN_RI_18; mep_extract_sfmt_break (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEP_INSN_STCB_R; mep_extract_sfmt_stcb_r (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 125 :
entire_insn = entire_insn >> 16;
if ((entire_insn & 0xf00f) == 0x700d)
- { itype = MEP_INSN_RI_19; mep_extract_sfmt_break (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEP_INSN_LDCB_R; mep_extract_sfmt_ldcb_r (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 126 :
entire_insn = entire_insn >> 16;
if ((entire_insn & 0xf00f) == 0xe00d)
{ itype = MEP_INSN_RI_23; mep_extract_sfmt_break (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 240 :
+ if ((entire_insn & 0xf00f0000) == 0xf0000000)
+ { itype = MEP_INSN_DSP; mep_extract_sfmt_uci (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 241 :
{
unsigned int val = (((insn >> 8) & (3 << 4)) | ((insn >> 0) & (15 << 0)));
if ((entire_insn & 0xf0ffff07) == 0xf0011001)
{ itype = MEP_INSN_CLIPU; mep_extract_sfmt_clipu (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 32 :
+ if ((entire_insn & 0xf00ff0ff) == 0xf0012000)
+ { itype = MEP_INSN_CASB3; mep_extract_sfmt_casb3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 33 :
+ if ((entire_insn & 0xf00ff0ff) == 0xf0012001)
+ { itype = MEP_INSN_CASH3; mep_extract_sfmt_casb3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 34 :
+ if ((entire_insn & 0xf00ff0ff) == 0xf0012002)
+ { itype = MEP_INSN_CASW3; mep_extract_sfmt_casb3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 52 :
if ((entire_insn & 0xf00fffff) == 0xf0013004)
{ itype = MEP_INSN_MADD; mep_extract_sfmt_madd (this, current_cpu, pc, base_insn, entire_insn); goto done; }
default : itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
+ case 242 :
+ if ((entire_insn & 0xf00f0000) == 0xf0020000)
+ { itype = MEP_INSN_UCI; mep_extract_sfmt_uci (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 243 :
- entire_insn = entire_insn >> 16;
- if ((entire_insn & 0xf00f) == 0xf003)
- { itype = MEP_INSN_RI_24; mep_extract_sfmt_break (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00f0000) == 0xf0030000)
+ { itype = MEP_INSN_PREFD; mep_extract_sfmt_prefd (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 244 :
{
}
case 245 :
{
- unsigned int val = (((insn >> 10) & (31 << 0)));
+ unsigned int val = (((insn >> 10) & (63 << 0)));
switch (val)
{
case 0 :
- if ((entire_insn & 0xf00fff00) == 0xf0050000)
+ if ((entire_insn & 0xf00ffc00) == 0xf0050000)
{ itype = MEP_INSN_SBCPA; mep_extract_sfmt_sbcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
- if ((entire_insn & 0xf00fff00) == 0xf0050800)
+ if ((entire_insn & 0xf00ffc00) == 0xf0050800)
{ itype = MEP_INSN_SBCPM0; mep_extract_sfmt_sbcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
- if ((entire_insn & 0xf00fff00) == 0xf0050c00)
+ if ((entire_insn & 0xf00ffc00) == 0xf0050c00)
{ itype = MEP_INSN_SBCPM1; mep_extract_sfmt_sbcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
- if ((entire_insn & 0xf00fff01) == 0xf0051000)
+ if ((entire_insn & 0xf00ffc00) == 0xf0051000)
{ itype = MEP_INSN_SHCPA; mep_extract_sfmt_shcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
- if ((entire_insn & 0xf00fff01) == 0xf0051800)
+ if ((entire_insn & 0xf00ffc00) == 0xf0051800)
{ itype = MEP_INSN_SHCPM0; mep_extract_sfmt_shcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
- if ((entire_insn & 0xf00fff01) == 0xf0051c00)
+ if ((entire_insn & 0xf00ffc00) == 0xf0051c00)
{ itype = MEP_INSN_SHCPM1; mep_extract_sfmt_shcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 8 :
- if ((entire_insn & 0xf00fff03) == 0xf0052000)
+ if ((entire_insn & 0xf00ffc00) == 0xf0052000)
{ itype = MEP_INSN_SWCPA; mep_extract_sfmt_swcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 10 :
- if ((entire_insn & 0xf00fff03) == 0xf0052800)
+ if ((entire_insn & 0xf00ffc00) == 0xf0052800)
{ itype = MEP_INSN_SWCPM0; mep_extract_sfmt_swcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 11 :
- if ((entire_insn & 0xf00fff03) == 0xf0052c00)
+ if ((entire_insn & 0xf00ffc00) == 0xf0052c00)
{ itype = MEP_INSN_SWCPM1; mep_extract_sfmt_swcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 12 :
- if ((entire_insn & 0xf00fff07) == 0xf0053000)
+ if ((entire_insn & 0xf00ffc00) == 0xf0053000)
{ itype = MEP_INSN_SMCPA; mep_extract_sfmt_smcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 14 :
- if ((entire_insn & 0xf00fff07) == 0xf0053800)
+ if ((entire_insn & 0xf00ffc00) == 0xf0053800)
{ itype = MEP_INSN_SMCPM0; mep_extract_sfmt_smcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 15 :
- if ((entire_insn & 0xf00fff07) == 0xf0053c00)
+ if ((entire_insn & 0xf00ffc00) == 0xf0053c00)
{ itype = MEP_INSN_SMCPM1; mep_extract_sfmt_smcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 16 :
- if ((entire_insn & 0xf00fff00) == 0xf0054000)
- { itype = MEP_INSN_LBCPA; mep_extract_sfmt_lbcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00ffc00) == 0xf0054000)
+ { itype = MEP_INSN_LBCPA; mep_extract_sfmt_lbucpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 18 :
- if ((entire_insn & 0xf00fff00) == 0xf0054800)
- { itype = MEP_INSN_LBCPM0; mep_extract_sfmt_lbcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00ffc00) == 0xf0054800)
+ { itype = MEP_INSN_LBCPM0; mep_extract_sfmt_lbucpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 19 :
- if ((entire_insn & 0xf00fff00) == 0xf0054c00)
- { itype = MEP_INSN_LBCPM1; mep_extract_sfmt_lbcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00ffc00) == 0xf0054c00)
+ { itype = MEP_INSN_LBCPM1; mep_extract_sfmt_lbucpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 20 :
- if ((entire_insn & 0xf00fff01) == 0xf0055000)
- { itype = MEP_INSN_LHCPA; mep_extract_sfmt_lhcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00ffc00) == 0xf0055000)
+ { itype = MEP_INSN_LHCPA; mep_extract_sfmt_lhucpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 22 :
- if ((entire_insn & 0xf00fff01) == 0xf0055800)
- { itype = MEP_INSN_LHCPM0; mep_extract_sfmt_lhcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00ffc00) == 0xf0055800)
+ { itype = MEP_INSN_LHCPM0; mep_extract_sfmt_lhucpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 23 :
- if ((entire_insn & 0xf00fff01) == 0xf0055c00)
- { itype = MEP_INSN_LHCPM1; mep_extract_sfmt_lhcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ if ((entire_insn & 0xf00ffc00) == 0xf0055c00)
+ { itype = MEP_INSN_LHCPM1; mep_extract_sfmt_lhucpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 24 :
- if ((entire_insn & 0xf00fff03) == 0xf0056000)
+ if ((entire_insn & 0xf00ffc00) == 0xf0056000)
{ itype = MEP_INSN_LWCPA; mep_extract_sfmt_lwcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 26 :
- if ((entire_insn & 0xf00fff03) == 0xf0056800)
+ if ((entire_insn & 0xf00ffc00) == 0xf0056800)
{ itype = MEP_INSN_LWCPM0; mep_extract_sfmt_lwcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 27 :
- if ((entire_insn & 0xf00fff03) == 0xf0056c00)
+ if ((entire_insn & 0xf00ffc00) == 0xf0056c00)
{ itype = MEP_INSN_LWCPM1; mep_extract_sfmt_lwcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 28 :
- if ((entire_insn & 0xf00fff07) == 0xf0057000)
+ if ((entire_insn & 0xf00ffc00) == 0xf0057000)
{ itype = MEP_INSN_LMCPA; mep_extract_sfmt_lmcpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 30 :
- if ((entire_insn & 0xf00fff07) == 0xf0057800)
+ if ((entire_insn & 0xf00ffc00) == 0xf0057800)
{ itype = MEP_INSN_LMCPM0; mep_extract_sfmt_lmcpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 31 :
- if ((entire_insn & 0xf00fff07) == 0xf0057c00)
+ if ((entire_insn & 0xf00ffc00) == 0xf0057c00)
{ itype = MEP_INSN_LMCPM1; mep_extract_sfmt_lmcpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 48 :
+ if ((entire_insn & 0xf00ffc00) == 0xf005c000)
+ { itype = MEP_INSN_LBUCPA; mep_extract_sfmt_lbucpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 50 :
+ if ((entire_insn & 0xf00ffc00) == 0xf005c800)
+ { itype = MEP_INSN_LBUCPM0; mep_extract_sfmt_lbucpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 51 :
+ if ((entire_insn & 0xf00ffc00) == 0xf005cc00)
+ { itype = MEP_INSN_LBUCPM1; mep_extract_sfmt_lbucpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 52 :
+ if ((entire_insn & 0xf00ffc00) == 0xf005d000)
+ { itype = MEP_INSN_LHUCPA; mep_extract_sfmt_lhucpa (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 54 :
+ if ((entire_insn & 0xf00ffc00) == 0xf005d800)
+ { itype = MEP_INSN_LHUCPM0; mep_extract_sfmt_lhucpm0 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 55 :
+ if ((entire_insn & 0xf00ffc00) == 0xf005dc00)
+ { itype = MEP_INSN_LHUCPM1; mep_extract_sfmt_lhucpm1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
case 246 :
- entire_insn = entire_insn >> 16;
- if ((entire_insn & 0xf00f) == 0xf006)
- { itype = MEP_INSN_RI_25; mep_extract_sfmt_break (this, current_cpu, pc, base_insn, entire_insn); goto done; }
- itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ {
+ unsigned int val = (((insn >> 13) & (3 << 1)) | ((insn >> 12) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xf00ff000) == 0xf0060000)
+ { itype = MEP_INSN_SBCP; mep_extract_sfmt_sbcp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 1 :
+ if ((entire_insn & 0xf00ff000) == 0xf0061000)
+ { itype = MEP_INSN_SHCP; mep_extract_sfmt_shcp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 2 :
+ if ((entire_insn & 0xf00ff000) == 0xf0064000)
+ { itype = MEP_INSN_LBCP; mep_extract_sfmt_lbcp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 3 :
+ if ((entire_insn & 0xf00ff000) == 0xf0065000)
+ { itype = MEP_INSN_LHCP; mep_extract_sfmt_lhcp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 6 :
+ if ((entire_insn & 0xf00ff000) == 0xf006c000)
+ { itype = MEP_INSN_LBUCP; mep_extract_sfmt_lbcp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ case 7 :
+ if ((entire_insn & 0xf00ff000) == 0xf006d000)
+ { itype = MEP_INSN_LHUCP; mep_extract_sfmt_lhcp (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ default : itype = MEP_INSN_X_INVALID; mep_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
+ }
+ }
case 248 :
entire_insn = entire_insn >> 16;
if ((entire_insn & 0xf00f) == 0xf008)
}
}
- }
-
- /* The instruction has been decoded and fields extracted. */
- done:
-
- this->addr = pc;
- // FIXME: To be redone (to handle ISA variants).
- this->idesc = & mep_idesc::idesc_table[itype];
- // ??? record semantic handler?
- assert(this->idesc->sem_index == itype);
+ }
+
+ /* The instruction has been decoded and fields extracted. */
+ done:
+
+ this->addr = pc;
+ // FIXME: To be redone (to handle ISA variants).
+ this->idesc = & mep_idesc::idesc_table[itype];
+ // ??? record semantic handler?
+ assert(this->idesc->sem_index == itype);
+}
+
+void
+mep_extract_sfmt_empty (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_empty)\t"
+ << endl;
+ }
+
+#undef FLD
+}
+
+void
+mep_extract_sfmt_stcb_r (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stcb_r.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ FLD (i_rn) = & current_cpu->hardware.h_gpr[f_rn];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_stcb_r)\t"
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_rn:0x" << hex << f_rn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ FLD (in_rn) = f_rn;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_ldcb_r (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ FLD (i_rn) = & current_cpu->hardware.h_gpr[f_rn];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_ldcb_r)\t"
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_rn:0x" << hex << f_rn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ FLD (out_rn) = f_rn;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_pref (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ FLD (f_rm) = f_rm;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_pref)\t"
+ << " f_rn:0x" << hex << f_rn << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_prefd (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lhu16.f
+ UINT f_rn;
+ UINT f_rm;
+ INT f_16s16;
+
+ f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_16s16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ FLD (f_rm) = f_rm;
+ FLD (f_16s16) = f_16s16;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_prefd)\t"
+ << " f_rn:0x" << hex << f_rn << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_16s16:0x" << hex << f_16s16 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_casb3 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ UINT f_rn;
+ UINT f_rm;
+ UINT f_rl5;
+
+ f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_rl5 = EXTRACT_MSB0_UINT (insn, 32, 20, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rl5) = f_rl5;
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ FLD (i_rl5) = & current_cpu->hardware.h_gpr[f_rl5];
+ FLD (i_rm) = & current_cpu->hardware.h_gpr[f_rm];
+ FLD (i_rn) = & current_cpu->hardware.h_gpr[f_rn];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_casb3)\t"
+ << " f_rl5:0x" << hex << f_rl5 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_rn:0x" << hex << f_rn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rl5) = f_rl5;
+ FLD (in_rm) = f_rm;
+ FLD (in_rn) = f_rn;
+ FLD (out_rl5) = f_rl5;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_sbcp (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ UINT f_crn;
+ UINT f_rm;
+ UINT f_12s20;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_12s20 = EXTRACT_MSB0_UINT (insn, 32, 20, 12);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_12s20) = f_12s20;
+ FLD (f_crn) = f_crn;
+ FLD (f_rm) = f_rm;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_sbcp)\t"
+ << " f_12s20:0x" << hex << f_12s20 << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_lbcp (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ UINT f_crn;
+ UINT f_rm;
+ UINT f_12s20;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_12s20 = EXTRACT_MSB0_UINT (insn, 32, 20, 12);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_12s20) = f_12s20;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lbcp)\t"
+ << " f_12s20:0x" << hex << f_12s20 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_shcp (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ UINT f_crn;
+ UINT f_rm;
+ UINT f_12s20;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_12s20 = EXTRACT_MSB0_UINT (insn, 32, 20, 12);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_12s20) = f_12s20;
+ FLD (f_crn) = f_crn;
+ FLD (f_rm) = f_rm;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_shcp)\t"
+ << " f_12s20:0x" << hex << f_12s20 << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_lhcp (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ UINT f_crn;
+ UINT f_rm;
+ UINT f_12s20;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_12s20 = EXTRACT_MSB0_UINT (insn, 32, 20, 12);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_12s20) = f_12s20;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lhcp)\t"
+ << " f_12s20:0x" << hex << f_12s20 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_lbucpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ UINT f_crn;
+ UINT f_rm;
+ SI f_cdisp10;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cdisp10) = f_cdisp10;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lbucpa)\t"
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ FLD (out_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_lhucpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ UINT f_crn;
+ UINT f_rm;
+ SI f_cdisp10;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cdisp10) = f_cdisp10;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lhucpa)\t"
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rma) = f_rm;
+ FLD (out_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_lbucpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ UINT f_crn;
+ UINT f_rm;
+ SI f_cdisp10;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cdisp10) = f_cdisp10;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lbucpm0)\t"
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_mb0) = 12;
+ FLD (in_me0) = 13;
+ FLD (in_rma) = f_rm;
+ FLD (out_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_lhucpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ UINT f_crn;
+ UINT f_rm;
+ SI f_cdisp10;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cdisp10) = f_cdisp10;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lhucpm0)\t"
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_mb0) = 12;
+ FLD (in_me0) = 13;
+ FLD (in_rma) = f_rm;
+ FLD (out_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_lbucpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ UINT f_crn;
+ UINT f_rm;
+ SI f_cdisp10;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cdisp10) = f_cdisp10;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lbucpm1)\t"
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_mb1) = 14;
+ FLD (in_me1) = 15;
+ FLD (in_rma) = f_rm;
+ FLD (out_rma) = f_rm;
+ }
+#undef FLD
+}
+
+void
+mep_extract_sfmt_lhucpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+ mep_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ UINT f_crn;
+ UINT f_rm;
+ SI f_cdisp10;
+
+ f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_cdisp10) = f_cdisp10;
+ FLD (f_rm) = f_rm;
+ FLD (f_crn) = f_crn;
+ FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_lhucpm1)\t"
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_crn:0x" << hex << f_crn << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_mb1) = 14;
+ FLD (in_me1) = 15;
+ FLD (in_rma) = f_rm;
+ FLD (out_rma) = f_rm;
+ }
+#undef FLD
}
void
-mep_extract_sfmt_empty (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
+mep_extract_sfmt_uci (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_uci.f
+ UINT f_rn;
+ UINT f_rm;
+ UINT f_16u16;
+ f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
+ f_16u16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
/* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ FLD (f_16u16) = f_16u16;
+ FLD (i_rm) = & current_cpu->hardware.h_gpr[f_rm];
+ FLD (i_rn) = & current_cpu->hardware.h_gpr[f_rn];
if (UNLIKELY(current_cpu->trace_extract_p))
{
current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_empty)\t"
+ << "0x" << hex << pc << dec << " (sfmt_uci)\t"
+ << " f_rm:0x" << hex << f_rm << dec
+ << " f_rn:0x" << hex << f_rn << dec
+ << " f_16u16:0x" << hex << f_16u16 << dec
<< endl;
}
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ FLD (in_rm) = f_rm;
+ FLD (in_rn) = f_rn;
+ FLD (out_rn) = f_rn;
+ }
#undef FLD
}
void
mep_extract_sfmt_mov (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
UINT f_rn;
UINT f_rm;
void
mep_extract_sfmt_movu16 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
UINT f_rn;
UINT f_16u16;
void
mep_extract_sfmt_sltu3x (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
UINT f_rn;
UINT f_rm;
UINT f_16u16;
void
mep_extract_sfmt_or3 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
UINT f_rn;
UINT f_rm;
UINT f_16u16;
void
mep_extract_sfmt_stcb (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_stcb.f
+#define FLD(f) abuf->fields.sfmt_uci.f
UINT f_rn;
UINT f_16u16;
void
mep_extract_sfmt_tas (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
UINT f_rn;
UINT f_rm;
}
void
-mep_extract_sfmt_cache (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
- mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_tas.f
- UINT f_rn;
- UINT f_rm;
-
- f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4);
-
- /* Record the fields for the semantic handler. */
- FLD (f_rn) = f_rn;
- FLD (f_rm) = f_rm;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_cache)\t"
- << " f_rn:0x" << hex << f_rn << dec
- << " f_rm:0x" << hex << f_rm << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mep_extract_sfmt_mul (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_maddr.f
void
mep_extract_sfmt_ldz (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
UINT f_rn;
UINT f_rm;
void
mep_extract_sfmt_swcpi (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
void
mep_extract_sfmt_lwcpi (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
void
mep_extract_sfmt_smcpi (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
void
mep_extract_sfmt_lmcpi (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
void
mep_extract_sfmt_sbcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- INT f_8s24;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24 = EXTRACT_MSB0_INT (insn, 32, 24, 8);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24) = f_8s24;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_sbcpa)\t"
- << " f_8s24:0x" << hex << f_8s24 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
}
void
-mep_extract_sfmt_lbcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
- mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
- UINT f_crn;
- UINT f_rm;
- INT f_8s24;
-
- f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24 = EXTRACT_MSB0_INT (insn, 32, 24, 8);
-
- /* Record the fields for the semantic handler. */
- FLD (f_8s24) = f_8s24;
- FLD (f_rm) = f_rm;
- FLD (f_crn) = f_crn;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_lbcpa)\t"
- << " f_8s24:0x" << hex << f_8s24 << dec
- << " f_rm:0x" << hex << f_rm << dec
- << " f_crn:0x" << hex << f_crn << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_rma) = f_rm;
- FLD (out_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mep_extract_sfmt_shcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a2;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a2 = ((EXTRACT_MSB0_INT (insn, 32, 24, 7)) << (1));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a2) = f_8s24a2;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_shcpa)\t"
- << " f_8s24a2:0x" << hex << f_8s24a2 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
}
void
-mep_extract_sfmt_lhcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
- mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
- UINT f_crn;
- UINT f_rm;
- SI f_8s24a2;
-
- f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a2 = ((EXTRACT_MSB0_INT (insn, 32, 24, 7)) << (1));
-
- /* Record the fields for the semantic handler. */
- FLD (f_8s24a2) = f_8s24a2;
- FLD (f_rm) = f_rm;
- FLD (f_crn) = f_crn;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_lhcpa)\t"
- << " f_8s24a2:0x" << hex << f_8s24a2 << dec
- << " f_rm:0x" << hex << f_rm << dec
- << " f_crn:0x" << hex << f_crn << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_rma) = f_rm;
- FLD (out_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mep_extract_sfmt_swcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a4;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a4 = ((EXTRACT_MSB0_INT (insn, 32, 24, 6)) << (2));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a4) = f_8s24a4;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_swcpa)\t"
- << " f_8s24a4:0x" << hex << f_8s24a4 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
void
mep_extract_sfmt_lwcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a4;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a4 = ((EXTRACT_MSB0_INT (insn, 32, 24, 6)) << (2));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a4) = f_8s24a4;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_rm) = f_rm;
FLD (f_crn) = f_crn;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_lwcpa)\t"
- << " f_8s24a4:0x" << hex << f_8s24a4 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_rm:0x" << hex << f_rm << dec
<< " f_crn:0x" << hex << f_crn << dec
<< endl;
void
mep_extract_sfmt_smcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a8;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a8 = ((EXTRACT_MSB0_INT (insn, 32, 24, 5)) << (3));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a8) = f_8s24a8;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_smcpa)\t"
- << " f_8s24a8:0x" << hex << f_8s24a8 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
void
mep_extract_sfmt_lmcpa (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a8;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a8 = ((EXTRACT_MSB0_INT (insn, 32, 24, 5)) << (3));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a8) = f_8s24a8;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_rm) = f_rm;
FLD (f_crn) = f_crn;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_lmcpa)\t"
- << " f_8s24a8:0x" << hex << f_8s24a8 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_rm:0x" << hex << f_rm << dec
<< " f_crn:0x" << hex << f_crn << dec
<< endl;
void
mep_extract_sfmt_sbcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
UINT f_crn;
UINT f_rm;
- INT f_8s24;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24 = EXTRACT_MSB0_INT (insn, 32, 24, 8);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24) = f_8s24;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_sbcpm0)\t"
- << " f_8s24:0x" << hex << f_8s24 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
}
void
-mep_extract_sfmt_lbcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
- mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
- UINT f_crn;
- UINT f_rm;
- INT f_8s24;
-
- f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24 = EXTRACT_MSB0_INT (insn, 32, 24, 8);
-
- /* Record the fields for the semantic handler. */
- FLD (f_8s24) = f_8s24;
- FLD (f_rm) = f_rm;
- FLD (f_crn) = f_crn;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_lbcpm0)\t"
- << " f_8s24:0x" << hex << f_8s24 << dec
- << " f_rm:0x" << hex << f_rm << dec
- << " f_crn:0x" << hex << f_crn << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_mb0) = 12;
- FLD (in_me0) = 13;
- FLD (in_rma) = f_rm;
- FLD (out_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mep_extract_sfmt_shcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a2;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a2 = ((EXTRACT_MSB0_INT (insn, 32, 24, 7)) << (1));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a2) = f_8s24a2;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_shcpm0)\t"
- << " f_8s24a2:0x" << hex << f_8s24a2 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
}
void
-mep_extract_sfmt_lhcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
- mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
- UINT f_crn;
- UINT f_rm;
- SI f_8s24a2;
-
- f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a2 = ((EXTRACT_MSB0_INT (insn, 32, 24, 7)) << (1));
-
- /* Record the fields for the semantic handler. */
- FLD (f_8s24a2) = f_8s24a2;
- FLD (f_rm) = f_rm;
- FLD (f_crn) = f_crn;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_lhcpm0)\t"
- << " f_8s24a2:0x" << hex << f_8s24a2 << dec
- << " f_rm:0x" << hex << f_rm << dec
- << " f_crn:0x" << hex << f_crn << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_mb0) = 12;
- FLD (in_me0) = 13;
- FLD (in_rma) = f_rm;
- FLD (out_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mep_extract_sfmt_swcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a4;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a4 = ((EXTRACT_MSB0_INT (insn, 32, 24, 6)) << (2));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a4) = f_8s24a4;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_swcpm0)\t"
- << " f_8s24a4:0x" << hex << f_8s24a4 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
void
mep_extract_sfmt_lwcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a4;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a4 = ((EXTRACT_MSB0_INT (insn, 32, 24, 6)) << (2));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a4) = f_8s24a4;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_rm) = f_rm;
FLD (f_crn) = f_crn;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_lwcpm0)\t"
- << " f_8s24a4:0x" << hex << f_8s24a4 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_rm:0x" << hex << f_rm << dec
<< " f_crn:0x" << hex << f_crn << dec
<< endl;
void
mep_extract_sfmt_smcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a8;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a8 = ((EXTRACT_MSB0_INT (insn, 32, 24, 5)) << (3));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a8) = f_8s24a8;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_smcpm0)\t"
- << " f_8s24a8:0x" << hex << f_8s24a8 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
void
mep_extract_sfmt_lmcpm0 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a8;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a8 = ((EXTRACT_MSB0_INT (insn, 32, 24, 5)) << (3));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a8) = f_8s24a8;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_rm) = f_rm;
FLD (f_crn) = f_crn;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_lmcpm0)\t"
- << " f_8s24a8:0x" << hex << f_8s24a8 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_rm:0x" << hex << f_rm << dec
<< " f_crn:0x" << hex << f_crn << dec
<< endl;
void
mep_extract_sfmt_sbcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- INT f_8s24;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24 = EXTRACT_MSB0_INT (insn, 32, 24, 8);
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24) = f_8s24;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_sbcpm1)\t"
- << " f_8s24:0x" << hex << f_8s24 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
}
void
-mep_extract_sfmt_lbcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
- mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
- UINT f_crn;
- UINT f_rm;
- INT f_8s24;
-
- f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24 = EXTRACT_MSB0_INT (insn, 32, 24, 8);
-
- /* Record the fields for the semantic handler. */
- FLD (f_8s24) = f_8s24;
- FLD (f_rm) = f_rm;
- FLD (f_crn) = f_crn;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_lbcpm1)\t"
- << " f_8s24:0x" << hex << f_8s24 << dec
- << " f_rm:0x" << hex << f_rm << dec
- << " f_crn:0x" << hex << f_crn << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_mb1) = 14;
- FLD (in_me1) = 15;
- FLD (in_rma) = f_rm;
- FLD (out_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mep_extract_sfmt_shcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a2;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a2 = ((EXTRACT_MSB0_INT (insn, 32, 24, 7)) << (1));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a2) = f_8s24a2;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_shcpm1)\t"
- << " f_8s24a2:0x" << hex << f_8s24a2 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
}
void
-mep_extract_sfmt_lhcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
- mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
- UINT f_crn;
- UINT f_rm;
- SI f_8s24a2;
-
- f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
- f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a2 = ((EXTRACT_MSB0_INT (insn, 32, 24, 7)) << (1));
-
- /* Record the fields for the semantic handler. */
- FLD (f_8s24a2) = f_8s24a2;
- FLD (f_rm) = f_rm;
- FLD (f_crn) = f_crn;
- FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
- if (UNLIKELY(current_cpu->trace_extract_p))
- {
- current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_lhcpm1)\t"
- << " f_8s24a2:0x" << hex << f_8s24a2 << dec
- << " f_rm:0x" << hex << f_rm << dec
- << " f_crn:0x" << hex << f_crn << dec
- << endl;
- }
-
- /* Record the fields for profiling. */
- if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
- {
- FLD (in_mb1) = 14;
- FLD (in_me1) = 15;
- FLD (in_rma) = f_rm;
- FLD (out_rma) = f_rm;
- }
-#undef FLD
-}
-
-void
mep_extract_sfmt_swcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a4;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a4 = ((EXTRACT_MSB0_INT (insn, 32, 24, 6)) << (2));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a4) = f_8s24a4;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_swcpm1)\t"
- << " f_8s24a4:0x" << hex << f_8s24a4 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
void
mep_extract_sfmt_lwcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a4;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a4 = ((EXTRACT_MSB0_INT (insn, 32, 24, 6)) << (2));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a4) = f_8s24a4;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_rm) = f_rm;
FLD (f_crn) = f_crn;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_lwcpm1)\t"
- << " f_8s24a4:0x" << hex << f_8s24a4 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_rm:0x" << hex << f_rm << dec
<< " f_crn:0x" << hex << f_crn << dec
<< endl;
void
mep_extract_sfmt_smcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a8;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a8 = ((EXTRACT_MSB0_INT (insn, 32, 24, 5)) << (3));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a8) = f_8s24a8;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_crn) = f_crn;
FLD (f_rm) = f_rm;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_smcpm1)\t"
- << " f_8s24a8:0x" << hex << f_8s24a8 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_crn:0x" << hex << f_crn << dec
<< " f_rm:0x" << hex << f_rm << dec
<< endl;
void
mep_extract_sfmt_lmcpm1 (mep_scache* abuf, mep_basic_cpu* current_cpu, PCADDR pc, mep_insn_word base_insn, mep_insn_word entire_insn){
mep_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
UINT f_crn;
UINT f_rm;
- SI f_8s24a8;
+ SI f_cdisp10;
f_crn = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4);
- f_8s24a8 = ((EXTRACT_MSB0_INT (insn, 32, 24, 5)) << (3));
+ f_cdisp10 = ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) & (512))) ? ((((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10))) - (1024))) : ((((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) & (128))) ? (((EXTRACT_MSB0_UINT (insn, 32, 22, 10)) ^ (768))) : (EXTRACT_MSB0_UINT (insn, 32, 22, 10)));
/* Record the fields for the semantic handler. */
- FLD (f_8s24a8) = f_8s24a8;
+ FLD (f_cdisp10) = f_cdisp10;
FLD (f_rm) = f_rm;
FLD (f_crn) = f_crn;
FLD (i_rma) = & current_cpu->hardware.h_gpr[f_rm];
{
current_cpu->trace_stream
<< "0x" << hex << pc << dec << " (sfmt_lmcpm1)\t"
- << " f_8s24a8:0x" << hex << f_8s24a8 << dec
+ << " f_cdisp10:0x" << hex << f_cdisp10 << dec
<< " f_rm:0x" << hex << f_rm << dec
<< " f_crn:0x" << hex << f_crn << dec
<< endl;
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
This file is part of the Red Hat simulators.
/* Enum declaration for instructions in cpu family mep. */
typedef enum mep_insn_type {
- MEP_INSN_X_INVALID, MEP_INSN_SB, MEP_INSN_SH, MEP_INSN_SW
- , MEP_INSN_LB, MEP_INSN_LH, MEP_INSN_LW, MEP_INSN_LBU
- , MEP_INSN_LHU, MEP_INSN_SW_SP, MEP_INSN_LW_SP, MEP_INSN_SB_TP
- , MEP_INSN_SH_TP, MEP_INSN_SW_TP, MEP_INSN_LB_TP, MEP_INSN_LH_TP
- , MEP_INSN_LW_TP, MEP_INSN_LBU_TP, MEP_INSN_LHU_TP, MEP_INSN_SB16
- , MEP_INSN_SH16, MEP_INSN_SW16, MEP_INSN_LB16, MEP_INSN_LH16
- , MEP_INSN_LW16, MEP_INSN_LBU16, MEP_INSN_LHU16, MEP_INSN_SW24
- , MEP_INSN_LW24, MEP_INSN_EXTB, MEP_INSN_EXTH, MEP_INSN_EXTUB
- , MEP_INSN_EXTUH, MEP_INSN_SSARB, MEP_INSN_MOV, MEP_INSN_MOVI8
- , MEP_INSN_MOVI16, MEP_INSN_MOVU24, MEP_INSN_MOVU16, MEP_INSN_MOVH
- , MEP_INSN_ADD3, MEP_INSN_ADD, MEP_INSN_ADD3I, MEP_INSN_ADVCK3
- , MEP_INSN_SUB, MEP_INSN_SBVCK3, MEP_INSN_NEG, MEP_INSN_SLT3
- , MEP_INSN_SLTU3, MEP_INSN_SLT3I, MEP_INSN_SLTU3I, MEP_INSN_SL1AD3
- , MEP_INSN_SL2AD3, MEP_INSN_ADD3X, MEP_INSN_SLT3X, MEP_INSN_SLTU3X
- , MEP_INSN_OR, MEP_INSN_AND, MEP_INSN_XOR, MEP_INSN_NOR
- , MEP_INSN_OR3, MEP_INSN_AND3, MEP_INSN_XOR3, MEP_INSN_SRA
- , MEP_INSN_SRL, MEP_INSN_SLL, MEP_INSN_SRAI, MEP_INSN_SRLI
- , MEP_INSN_SLLI, MEP_INSN_SLL3, MEP_INSN_FSFT, MEP_INSN_BRA
- , MEP_INSN_BEQZ, MEP_INSN_BNEZ, MEP_INSN_BEQI, MEP_INSN_BNEI
- , MEP_INSN_BLTI, MEP_INSN_BGEI, MEP_INSN_BEQ, MEP_INSN_BNE
- , MEP_INSN_BSR12, MEP_INSN_BSR24, MEP_INSN_JMP, MEP_INSN_JMP24
- , MEP_INSN_JSR, MEP_INSN_RET, MEP_INSN_REPEAT, MEP_INSN_EREPEAT
- , MEP_INSN_STC_LP, MEP_INSN_STC_HI, MEP_INSN_STC_LO, MEP_INSN_STC
- , MEP_INSN_LDC_LP, MEP_INSN_LDC_HI, MEP_INSN_LDC_LO, MEP_INSN_LDC
- , MEP_INSN_DI, MEP_INSN_EI, MEP_INSN_RETI, MEP_INSN_HALT
- , MEP_INSN_SLEEP, MEP_INSN_SWI, MEP_INSN_BREAK, MEP_INSN_SYNCM
- , MEP_INSN_STCB, MEP_INSN_LDCB, MEP_INSN_BSETM, MEP_INSN_BCLRM
- , MEP_INSN_BNOTM, MEP_INSN_BTSTM, MEP_INSN_TAS, MEP_INSN_CACHE
- , MEP_INSN_MUL, MEP_INSN_MULU, MEP_INSN_MULR, MEP_INSN_MULRU
- , MEP_INSN_MADD, MEP_INSN_MADDU, MEP_INSN_MADDR, MEP_INSN_MADDRU
- , MEP_INSN_DIV, MEP_INSN_DIVU, MEP_INSN_DRET, MEP_INSN_DBREAK
- , MEP_INSN_LDZ, MEP_INSN_ABS, MEP_INSN_AVE, MEP_INSN_MIN
- , MEP_INSN_MAX, MEP_INSN_MINU, MEP_INSN_MAXU, MEP_INSN_CLIP
- , MEP_INSN_CLIPU, MEP_INSN_SADD, MEP_INSN_SSUB, MEP_INSN_SADDU
- , MEP_INSN_SSUBU, MEP_INSN_SWCP, MEP_INSN_LWCP, MEP_INSN_SMCP
- , MEP_INSN_LMCP, MEP_INSN_SWCPI, MEP_INSN_LWCPI, MEP_INSN_SMCPI
- , MEP_INSN_LMCPI, MEP_INSN_SWCP16, MEP_INSN_LWCP16, MEP_INSN_SMCP16
- , MEP_INSN_LMCP16, MEP_INSN_SBCPA, MEP_INSN_LBCPA, MEP_INSN_SHCPA
- , MEP_INSN_LHCPA, MEP_INSN_SWCPA, MEP_INSN_LWCPA, MEP_INSN_SMCPA
- , MEP_INSN_LMCPA, MEP_INSN_SBCPM0, MEP_INSN_LBCPM0, MEP_INSN_SHCPM0
- , MEP_INSN_LHCPM0, MEP_INSN_SWCPM0, MEP_INSN_LWCPM0, MEP_INSN_SMCPM0
- , MEP_INSN_LMCPM0, MEP_INSN_SBCPM1, MEP_INSN_LBCPM1, MEP_INSN_SHCPM1
- , MEP_INSN_LHCPM1, MEP_INSN_SWCPM1, MEP_INSN_LWCPM1, MEP_INSN_SMCPM1
- , MEP_INSN_LMCPM1, MEP_INSN_BCPEQ, MEP_INSN_BCPNE, MEP_INSN_BCPAT
- , MEP_INSN_BCPAF, MEP_INSN_SYNCCP, MEP_INSN_JSRV, MEP_INSN_BSRV
- , MEP_INSN_SIM_SYSCALL, MEP_INSN_RI_0, MEP_INSN_RI_1, MEP_INSN_RI_2
- , MEP_INSN_RI_3, MEP_INSN_RI_4, MEP_INSN_RI_5, MEP_INSN_RI_6
- , MEP_INSN_RI_7, MEP_INSN_RI_8, MEP_INSN_RI_9, MEP_INSN_RI_10
- , MEP_INSN_RI_11, MEP_INSN_RI_12, MEP_INSN_RI_13, MEP_INSN_RI_14
- , MEP_INSN_RI_15, MEP_INSN_RI_17, MEP_INSN_RI_20, MEP_INSN_RI_21
- , MEP_INSN_RI_22, MEP_INSN_RI_23, MEP_INSN_RI_24, MEP_INSN_RI_25
- , MEP_INSN_RI_26, MEP_INSN_RI_16, MEP_INSN_RI_18, MEP_INSN_RI_19
+ MEP_INSN_X_INVALID, MEP_INSN_STCB_R, MEP_INSN_LDCB_R, MEP_INSN_PREF
+ , MEP_INSN_PREFD, MEP_INSN_CASB3, MEP_INSN_CASH3, MEP_INSN_CASW3
+ , MEP_INSN_SBCP, MEP_INSN_LBCP, MEP_INSN_LBUCP, MEP_INSN_SHCP
+ , MEP_INSN_LHCP, MEP_INSN_LHUCP, MEP_INSN_LBUCPA, MEP_INSN_LHUCPA
+ , MEP_INSN_LBUCPM0, MEP_INSN_LHUCPM0, MEP_INSN_LBUCPM1, MEP_INSN_LHUCPM1
+ , MEP_INSN_UCI, MEP_INSN_DSP, MEP_INSN_SB, MEP_INSN_SH
+ , MEP_INSN_SW, MEP_INSN_LB, MEP_INSN_LH, MEP_INSN_LW
+ , MEP_INSN_LBU, MEP_INSN_LHU, MEP_INSN_SW_SP, MEP_INSN_LW_SP
+ , MEP_INSN_SB_TP, MEP_INSN_SH_TP, MEP_INSN_SW_TP, MEP_INSN_LB_TP
+ , MEP_INSN_LH_TP, MEP_INSN_LW_TP, MEP_INSN_LBU_TP, MEP_INSN_LHU_TP
+ , MEP_INSN_SB16, MEP_INSN_SH16, MEP_INSN_SW16, MEP_INSN_LB16
+ , MEP_INSN_LH16, MEP_INSN_LW16, MEP_INSN_LBU16, MEP_INSN_LHU16
+ , MEP_INSN_SW24, MEP_INSN_LW24, MEP_INSN_EXTB, MEP_INSN_EXTH
+ , MEP_INSN_EXTUB, MEP_INSN_EXTUH, MEP_INSN_SSARB, MEP_INSN_MOV
+ , MEP_INSN_MOVI8, MEP_INSN_MOVI16, MEP_INSN_MOVU24, MEP_INSN_MOVU16
+ , MEP_INSN_MOVH, MEP_INSN_ADD3, MEP_INSN_ADD, MEP_INSN_ADD3I
+ , MEP_INSN_ADVCK3, MEP_INSN_SUB, MEP_INSN_SBVCK3, MEP_INSN_NEG
+ , MEP_INSN_SLT3, MEP_INSN_SLTU3, MEP_INSN_SLT3I, MEP_INSN_SLTU3I
+ , MEP_INSN_SL1AD3, MEP_INSN_SL2AD3, MEP_INSN_ADD3X, MEP_INSN_SLT3X
+ , MEP_INSN_SLTU3X, MEP_INSN_OR, MEP_INSN_AND, MEP_INSN_XOR
+ , MEP_INSN_NOR, MEP_INSN_OR3, MEP_INSN_AND3, MEP_INSN_XOR3
+ , MEP_INSN_SRA, MEP_INSN_SRL, MEP_INSN_SLL, MEP_INSN_SRAI
+ , MEP_INSN_SRLI, MEP_INSN_SLLI, MEP_INSN_SLL3, MEP_INSN_FSFT
+ , MEP_INSN_BRA, MEP_INSN_BEQZ, MEP_INSN_BNEZ, MEP_INSN_BEQI
+ , MEP_INSN_BNEI, MEP_INSN_BLTI, MEP_INSN_BGEI, MEP_INSN_BEQ
+ , MEP_INSN_BNE, MEP_INSN_BSR12, MEP_INSN_BSR24, MEP_INSN_JMP
+ , MEP_INSN_JMP24, MEP_INSN_JSR, MEP_INSN_RET, MEP_INSN_REPEAT
+ , MEP_INSN_EREPEAT, MEP_INSN_STC_LP, MEP_INSN_STC_HI, MEP_INSN_STC_LO
+ , MEP_INSN_STC, MEP_INSN_LDC_LP, MEP_INSN_LDC_HI, MEP_INSN_LDC_LO
+ , MEP_INSN_LDC, MEP_INSN_DI, MEP_INSN_EI, MEP_INSN_RETI
+ , MEP_INSN_HALT, MEP_INSN_SLEEP, MEP_INSN_SWI, MEP_INSN_BREAK
+ , MEP_INSN_SYNCM, MEP_INSN_STCB, MEP_INSN_LDCB, MEP_INSN_BSETM
+ , MEP_INSN_BCLRM, MEP_INSN_BNOTM, MEP_INSN_BTSTM, MEP_INSN_TAS
+ , MEP_INSN_CACHE, MEP_INSN_MUL, MEP_INSN_MULU, MEP_INSN_MULR
+ , MEP_INSN_MULRU, MEP_INSN_MADD, MEP_INSN_MADDU, MEP_INSN_MADDR
+ , MEP_INSN_MADDRU, MEP_INSN_DIV, MEP_INSN_DIVU, MEP_INSN_DRET
+ , MEP_INSN_DBREAK, MEP_INSN_LDZ, MEP_INSN_ABS, MEP_INSN_AVE
+ , MEP_INSN_MIN, MEP_INSN_MAX, MEP_INSN_MINU, MEP_INSN_MAXU
+ , MEP_INSN_CLIP, MEP_INSN_CLIPU, MEP_INSN_SADD, MEP_INSN_SSUB
+ , MEP_INSN_SADDU, MEP_INSN_SSUBU, MEP_INSN_SWCP, MEP_INSN_LWCP
+ , MEP_INSN_SMCP, MEP_INSN_LMCP, MEP_INSN_SWCPI, MEP_INSN_LWCPI
+ , MEP_INSN_SMCPI, MEP_INSN_LMCPI, MEP_INSN_SWCP16, MEP_INSN_LWCP16
+ , MEP_INSN_SMCP16, MEP_INSN_LMCP16, MEP_INSN_SBCPA, MEP_INSN_LBCPA
+ , MEP_INSN_SHCPA, MEP_INSN_LHCPA, MEP_INSN_SWCPA, MEP_INSN_LWCPA
+ , MEP_INSN_SMCPA, MEP_INSN_LMCPA, MEP_INSN_SBCPM0, MEP_INSN_LBCPM0
+ , MEP_INSN_SHCPM0, MEP_INSN_LHCPM0, MEP_INSN_SWCPM0, MEP_INSN_LWCPM0
+ , MEP_INSN_SMCPM0, MEP_INSN_LMCPM0, MEP_INSN_SBCPM1, MEP_INSN_LBCPM1
+ , MEP_INSN_SHCPM1, MEP_INSN_LHCPM1, MEP_INSN_SWCPM1, MEP_INSN_LWCPM1
+ , MEP_INSN_SMCPM1, MEP_INSN_LMCPM1, MEP_INSN_BCPEQ, MEP_INSN_BCPNE
+ , MEP_INSN_BCPAT, MEP_INSN_BCPAF, MEP_INSN_SYNCCP, MEP_INSN_JSRV
+ , MEP_INSN_BSRV, MEP_INSN_SIM_SYSCALL, MEP_INSN_RI_0, MEP_INSN_RI_1
+ , MEP_INSN_RI_2, MEP_INSN_RI_3, MEP_INSN_RI_4, MEP_INSN_RI_5
+ , MEP_INSN_RI_6, MEP_INSN_RI_7, MEP_INSN_RI_8, MEP_INSN_RI_9
+ , MEP_INSN_RI_10, MEP_INSN_RI_11, MEP_INSN_RI_12, MEP_INSN_RI_13
+ , MEP_INSN_RI_14, MEP_INSN_RI_15, MEP_INSN_RI_17, MEP_INSN_RI_20
+ , MEP_INSN_RI_21, MEP_INSN_RI_22, MEP_INSN_RI_23, MEP_INSN_RI_26
} MEP_INSN_TYPE;
unsigned char in_psw;
} sfmt_jmp24;
struct { /* */
- SI* i_rn;
- UINT f_16u16;
- UINT f_rn;
- unsigned char in_rn;
- } sfmt_stcb;
- struct { /* */
unsigned char in_epc;
unsigned char in_npc;
unsigned char in_opt;
} sfmt_sw_sp;
struct { /* */
SI* i_rma;
- SI* i_rn;
+ UINT f_12s20;
+ UINT f_crn;
UINT f_rm;
- UINT f_rn;
unsigned char in_rma;
- unsigned char out_rn;
- } sfmt_tas;
+ } sfmt_sbcp;
struct { /* */
SI* i_rm;
UINT f_rm;
unsigned char in_rn;
} sfmt_beqz;
struct { /* */
+ SI* i_rma;
+ SI* i_rn;
+ UINT f_rm;
+ UINT f_rn;
+ unsigned char in_rma;
+ unsigned char out_rn;
+ } sfmt_ldcb_r;
+ struct { /* */
+ SI* i_rma;
+ SI* i_rn;
+ UINT f_rm;
+ UINT f_rn;
+ unsigned char in_rma;
+ unsigned char in_rn;
+ } sfmt_stcb_r;
+ struct { /* */
SI* i_rn;
UINT f_csrn;
UINT f_rn;
struct { /* */
SI* i_rm;
SI* i_rn;
- UINT f_16u16;
- UINT f_rm;
- UINT f_rn;
- unsigned char in_rm;
- unsigned char out_rn;
- } sfmt_sltu3x;
- struct { /* */
- SI* i_rm;
- SI* i_rn;
INT f_16s16;
UINT f_rm;
UINT f_rn;
unsigned char in_rnc;
} sfmt_sb16;
struct { /* */
- SI* i_rma;
- SI f_8s24a8;
- UINT f_crn;
- UINT f_rm;
- unsigned char in_mb1;
- unsigned char in_me1;
- unsigned char in_rma;
- unsigned char out_rma;
- } sfmt_smcpm1;
- struct { /* */
- SI* i_rma;
- SI f_8s24a4;
- UINT f_crn;
+ SI* i_rm;
+ SI* i_rn;
UINT f_rm;
- unsigned char in_mb1;
- unsigned char in_me1;
- unsigned char in_rma;
- unsigned char out_rma;
- } sfmt_swcpm1;
+ UINT f_rn;
+ unsigned char in_rm;
+ unsigned char in_rn;
+ unsigned char in_sar;
+ unsigned char out_rn;
+ } sfmt_fsft;
struct { /* */
- SI* i_rma;
- SI f_8s24a2;
- UINT f_crn;
+ SI* i_rm;
+ SI* i_rn;
+ UINT f_16u16;
UINT f_rm;
- unsigned char in_mb1;
- unsigned char in_me1;
- unsigned char in_rma;
- unsigned char out_rma;
- } sfmt_shcpm1;
+ UINT f_rn;
+ unsigned char in_rm;
+ unsigned char in_rn;
+ unsigned char out_rn;
+ } sfmt_uci;
struct { /* */
SI* i_rma;
- INT f_8s24;
+ SI f_cdisp10;
UINT f_crn;
UINT f_rm;
unsigned char in_mb1;
unsigned char in_me1;
unsigned char in_rma;
unsigned char out_rma;
- } sfmt_sbcpm1;
+ } sfmt_lbucpm1;
struct { /* */
SI* i_rma;
- SI f_8s24a8;
+ SI f_cdisp10;
UINT f_crn;
UINT f_rm;
unsigned char in_mb0;
unsigned char in_me0;
unsigned char in_rma;
unsigned char out_rma;
- } sfmt_smcpm0;
- struct { /* */
- SI* i_rma;
- SI f_8s24a4;
- UINT f_crn;
- UINT f_rm;
- unsigned char in_mb0;
- unsigned char in_me0;
- unsigned char in_rma;
- unsigned char out_rma;
- } sfmt_swcpm0;
- struct { /* */
- SI* i_rma;
- SI f_8s24a2;
- UINT f_crn;
- UINT f_rm;
- unsigned char in_mb0;
- unsigned char in_me0;
- unsigned char in_rma;
- unsigned char out_rma;
- } sfmt_shcpm0;
- struct { /* */
- SI* i_rma;
- INT f_8s24;
- UINT f_crn;
- UINT f_rm;
- unsigned char in_mb0;
- unsigned char in_me0;
- unsigned char in_rma;
- unsigned char out_rma;
- } sfmt_sbcpm0;
- struct { /* */
- SI* i_rm;
- SI* i_rn;
- UINT f_rm;
- UINT f_rn;
- unsigned char in_rm;
- unsigned char in_rn;
- unsigned char in_sar;
- unsigned char out_rn;
- } sfmt_fsft;
+ } sfmt_lbucpm0;
struct { /* */
SI* i_rn;
SI f_17s16a2;
unsigned char out_rl;
} sfmt_add3;
struct { /* */
+ SI* i_rl5;
+ SI* i_rm;
+ SI* i_rn;
+ UINT f_rl5;
+ UINT f_rm;
+ UINT f_rn;
+ unsigned char in_rl5;
+ unsigned char in_rm;
+ unsigned char in_rn;
+ unsigned char out_rl5;
+ } sfmt_casb3;
+ struct { /* */
SI* i_rm;
SI* i_rn;
UINT f_rm;
using mep_basic::mep_sem_fn;
extern mep_sem_fn mep_sem_x_invalid;
+extern mep_sem_fn mep_sem_stcb_r;
+extern mep_sem_fn mep_sem_ldcb_r;
+extern mep_sem_fn mep_sem_pref;
+extern mep_sem_fn mep_sem_prefd;
+extern mep_sem_fn mep_sem_casb3;
+extern mep_sem_fn mep_sem_cash3;
+extern mep_sem_fn mep_sem_casw3;
+extern mep_sem_fn mep_sem_sbcp;
+extern mep_sem_fn mep_sem_lbcp;
+extern mep_sem_fn mep_sem_lbucp;
+extern mep_sem_fn mep_sem_shcp;
+extern mep_sem_fn mep_sem_lhcp;
+extern mep_sem_fn mep_sem_lhucp;
+extern mep_sem_fn mep_sem_lbucpa;
+extern mep_sem_fn mep_sem_lhucpa;
+extern mep_sem_fn mep_sem_lbucpm0;
+extern mep_sem_fn mep_sem_lhucpm0;
+extern mep_sem_fn mep_sem_lbucpm1;
+extern mep_sem_fn mep_sem_lhucpm1;
+extern mep_sem_fn mep_sem_uci;
+extern mep_sem_fn mep_sem_dsp;
extern mep_sem_fn mep_sem_sb;
extern mep_sem_fn mep_sem_sh;
extern mep_sem_fn mep_sem_sw;
extern mep_sem_fn mep_sem_ri_21;
extern mep_sem_fn mep_sem_ri_22;
extern mep_sem_fn mep_sem_ri_23;
-extern mep_sem_fn mep_sem_ri_24;
-extern mep_sem_fn mep_sem_ri_25;
extern mep_sem_fn mep_sem_ri_26;
-extern mep_sem_fn mep_sem_ri_16;
-extern mep_sem_fn mep_sem_ri_18;
-extern mep_sem_fn mep_sem_ri_19;
#endif /* MEP_DECODE_H */
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
This file is part of the Red Hat simulators.
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
- MACH_BASE, MACH_MEP, MACH_H1, MACH_MAX
+ MACH_BASE, MACH_MEP, MACH_H1, MACH_C5
+ , MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
inline int get_volatile_attr () { return (bools & (1<<CGEN_INSN_VOLATILE)) != 0; }
};
-#define MACH_MEP_INSN_CHUNK_BITSIZE 16
+#define MACH_C5_INSN_CHUNK_BITSIZE 16
} // end mep namespace
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
This file is part of the Red Hat simulators.
}
UINT
+mep_mep_model::model_stcb_r_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_stcb_r.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rn);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 1, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ {
+ cycles += model_u_stcb_before (current_cpu, idesc, 3);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_stcb_r_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_stcb_r.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rn);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 1, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_stcb_after (current_cpu, idesc, 3, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_ldcb_r_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_ldcb_before (current_cpu, idesc, 1);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ {
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rn);
+ cycles += model_u_ldcb_gpr_before (current_cpu, idesc, 3, out_loadreg);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_ldcb_r_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_ldcb_after (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rn);
+ cycles += model_u_ldcb_gpr_after (current_cpu, idesc, 3, referenced, out_loadreg);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_pref_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_pref_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_prefd_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lhu16.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_prefd_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lhu16.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_casb3_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rl5);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rl5);
+ cycles += model_u_load_gpr_before (current_cpu, idesc, 1, out_loadreg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_casb3_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rl5);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rl5);
+ cycles += model_u_load_gpr_after (current_cpu, idesc, 1, referenced, out_loadreg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_cash3_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rl5);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rl5);
+ cycles += model_u_load_gpr_before (current_cpu, idesc, 1, out_loadreg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_cash3_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rl5);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rl5);
+ cycles += model_u_load_gpr_after (current_cpu, idesc, 1, referenced, out_loadreg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_casw3_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rl5);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rl5);
+ cycles += model_u_load_gpr_before (current_cpu, idesc, 1, out_loadreg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_casw3_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rl5);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT out_loadreg = -1;
+ out_loadreg = FLD (out_rl5);
+ cycles += model_u_load_gpr_after (current_cpu, idesc, 1, referenced, out_loadreg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_sbcp_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_sbcp_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lbcp_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lbcp_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lbucp_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lbucp_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_shcp_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_shcp_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lhcp_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lhcp_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lhucp_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lhucp_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lbucpa_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lbucpa_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lhucpa_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lhucpa_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lbucpm0_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lbucpm0_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lhucpm0_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lhucpm0_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lbucpm1_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lbucpm1_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lhucpm1_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 1);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_lhucpm1_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rma);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_uci_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_uci.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rm);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rn);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 1, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_uci_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_uci.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rm);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rn);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 1, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_dsp_before (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_uci.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rm);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 0, in_usereg);
+ }
+ {
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rn);
+ cycles += model_u_use_gpr_before (current_cpu, idesc, 1, in_usereg);
+ }
+ {
+ cycles += model_u_exec_before (current_cpu, idesc, 2);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
+mep_mep_model::model_dsp_after (mep_basic_cpu *current_cpu, mep_scache *sem)
+{
+#define FLD(f) abuf->fields.sfmt_uci.f
+ const mep_scache* abuf = sem;
+ const mep_idesc* idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rm);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 0, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ INT in_usereg = -1;
+ in_usereg = FLD (in_rn);
+ cycles += model_u_use_gpr_after (current_cpu, idesc, 1, referenced, in_usereg);
+ }
+ {
+ int referenced = 0;
+ unsigned long long insn_referenced = abuf->written;
+ cycles += model_u_exec_after (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+UINT
mep_mep_model::model_sb_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
#define FLD(f) abuf->fields.sfmt_sb16.f
UINT
mep_mep_model::model_mov_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_mov_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_movu16_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_movu16_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_movh_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_movh_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_neg_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_neg_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_sltu3x_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_sltu3x_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_or3_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_or3_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_and3_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_and3_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_xor3_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_xor3_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_stcb_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_stcb.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_stcb_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_stcb.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_ldcb_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_ldcb_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_tas_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_tas_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_cache_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_cache_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_ldz_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_ldz_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_swcpi_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_swcpi_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lwcpi_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lwcpi_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_smcpi_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_smcpi_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lmcpi_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lmcpi_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_sbcpa_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_sbcpa_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lbcpa_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lbcpa_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_shcpa_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_shcpa_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lhcpa_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lhcpa_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_swcpa_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_swcpa_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lwcpa_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lwcpa_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_smcpa_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_smcpa_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lmcpa_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lmcpa_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_sbcpm0_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_sbcpm0_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lbcpm0_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lbcpm0_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_shcpm0_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_shcpm0_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lhcpm0_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lhcpm0_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_swcpm0_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_swcpm0_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lwcpm0_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lwcpm0_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_smcpm0_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_smcpm0_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lmcpm0_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lmcpm0_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_sbcpm1_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_sbcpm1_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lbcpm1_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lbcpm1_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_shcpm1_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_shcpm1_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lhcpm1_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lhcpm1_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_swcpm1_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_swcpm1_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lwcpm1_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lwcpm1_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_smcpm1_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_smcpm1_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lmcpm1_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
UINT
mep_mep_model::model_lmcpm1_after (mep_basic_cpu *current_cpu, mep_scache *sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
const mep_scache* abuf = sem;
const mep_idesc* idesc = abuf->idesc;
int cycles = 0;
}
UINT
-mep_mep_model::model_ri_24_before (mep_basic_cpu *current_cpu, mep_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mep_scache* abuf = sem;
- const mep_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- cycles += model_u_exec_before (current_cpu, idesc, 0);
- }
- {
- cycles += model_u_branch_before (current_cpu, idesc, 1);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mep_mep_model::model_ri_24_after (mep_basic_cpu *current_cpu, mep_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mep_scache* abuf = sem;
- const mep_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- cycles += model_u_exec_after (current_cpu, idesc, 0, referenced);
- }
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- referenced |= 1 << 0;
- cycles += model_u_branch_after (current_cpu, idesc, 1, referenced);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mep_mep_model::model_ri_25_before (mep_basic_cpu *current_cpu, mep_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mep_scache* abuf = sem;
- const mep_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- cycles += model_u_exec_before (current_cpu, idesc, 0);
- }
- {
- cycles += model_u_branch_before (current_cpu, idesc, 1);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mep_mep_model::model_ri_25_after (mep_basic_cpu *current_cpu, mep_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mep_scache* abuf = sem;
- const mep_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- cycles += model_u_exec_after (current_cpu, idesc, 0, referenced);
- }
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- referenced |= 1 << 0;
- cycles += model_u_branch_after (current_cpu, idesc, 1, referenced);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
mep_mep_model::model_ri_26_before (mep_basic_cpu *current_cpu, mep_scache *sem)
{
#define FLD(f) abuf->fields.fmt_empty.f
#undef FLD
}
-UINT
-mep_mep_model::model_ri_16_before (mep_basic_cpu *current_cpu, mep_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mep_scache* abuf = sem;
- const mep_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- cycles += model_u_exec_before (current_cpu, idesc, 0);
- }
- {
- cycles += model_u_branch_before (current_cpu, idesc, 1);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mep_mep_model::model_ri_16_after (mep_basic_cpu *current_cpu, mep_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mep_scache* abuf = sem;
- const mep_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- cycles += model_u_exec_after (current_cpu, idesc, 0, referenced);
- }
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- referenced |= 1 << 0;
- cycles += model_u_branch_after (current_cpu, idesc, 1, referenced);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mep_mep_model::model_ri_18_before (mep_basic_cpu *current_cpu, mep_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mep_scache* abuf = sem;
- const mep_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- cycles += model_u_exec_before (current_cpu, idesc, 0);
- }
- {
- cycles += model_u_branch_before (current_cpu, idesc, 1);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mep_mep_model::model_ri_18_after (mep_basic_cpu *current_cpu, mep_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mep_scache* abuf = sem;
- const mep_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- cycles += model_u_exec_after (current_cpu, idesc, 0, referenced);
- }
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- referenced |= 1 << 0;
- cycles += model_u_branch_after (current_cpu, idesc, 1, referenced);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mep_mep_model::model_ri_19_before (mep_basic_cpu *current_cpu, mep_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mep_scache* abuf = sem;
- const mep_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- cycles += model_u_exec_before (current_cpu, idesc, 0);
- }
- {
- cycles += model_u_branch_before (current_cpu, idesc, 1);
- }
- return cycles;
-#undef FLD
-}
-
-UINT
-mep_mep_model::model_ri_19_after (mep_basic_cpu *current_cpu, mep_scache *sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- const mep_scache* abuf = sem;
- const mep_idesc* idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- cycles += model_u_exec_after (current_cpu, idesc, 0, referenced);
- }
- {
- int referenced = 0;
- unsigned long long insn_referenced = abuf->written;
- referenced |= 1 << 0;
- cycles += model_u_branch_after (current_cpu, idesc, 1, referenced);
- }
- return cycles;
-#undef FLD
-}
-
/* We assume UNIT_NONE == 0 because the tables don't always terminate
entries with it. */
const mep_mep_model::insn_timing mep_mep_model::timing[] = {
{ MEP_INSN_X_INVALID, 0, 0, { { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_STCB_R, & mep_mep_model::model_stcb_r_before, & mep_mep_model::model_stcb_r_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 }, { mep_mep_model::UNIT_U_STCB, 0, 0 } } },
+ { MEP_INSN_LDCB_R, & mep_mep_model::model_ldcb_r_before, & mep_mep_model::model_ldcb_r_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_LDCB, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 }, { mep_mep_model::UNIT_U_LDCB_GPR, 0, 0 } } },
+ { MEP_INSN_PREF, & mep_mep_model::model_pref_before, & mep_mep_model::model_pref_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_PREFD, & mep_mep_model::model_prefd_before, & mep_mep_model::model_prefd_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_CASB3, & mep_mep_model::model_casb3_before, & mep_mep_model::model_casb3_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_LOAD_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_CASH3, & mep_mep_model::model_cash3_before, & mep_mep_model::model_cash3_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_LOAD_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_CASW3, & mep_mep_model::model_casw3_before, & mep_mep_model::model_casw3_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_LOAD_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_SBCP, & mep_mep_model::model_sbcp_before, & mep_mep_model::model_sbcp_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_LBCP, & mep_mep_model::model_lbcp_before, & mep_mep_model::model_lbcp_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_LBUCP, & mep_mep_model::model_lbucp_before, & mep_mep_model::model_lbucp_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_SHCP, & mep_mep_model::model_shcp_before, & mep_mep_model::model_shcp_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_LHCP, & mep_mep_model::model_lhcp_before, & mep_mep_model::model_lhcp_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_LHUCP, & mep_mep_model::model_lhucp_before, & mep_mep_model::model_lhucp_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_LBUCPA, & mep_mep_model::model_lbucpa_before, & mep_mep_model::model_lbucpa_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_LHUCPA, & mep_mep_model::model_lhucpa_before, & mep_mep_model::model_lhucpa_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_LBUCPM0, & mep_mep_model::model_lbucpm0_before, & mep_mep_model::model_lbucpm0_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_LHUCPM0, & mep_mep_model::model_lhucpm0_before, & mep_mep_model::model_lhucpm0_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_LBUCPM1, & mep_mep_model::model_lbucpm1_before, & mep_mep_model::model_lbucpm1_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_LHUCPM1, & mep_mep_model::model_lhucpm1_before, & mep_mep_model::model_lhucpm1_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_UCI, & mep_mep_model::model_uci_before, & mep_mep_model::model_uci_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
+ { MEP_INSN_DSP, & mep_mep_model::model_dsp_before, & mep_mep_model::model_dsp_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
{ MEP_INSN_SB, & mep_mep_model::model_sb_before, & mep_mep_model::model_sb_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
{ MEP_INSN_SH, & mep_mep_model::model_sh_before, & mep_mep_model::model_sh_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
{ MEP_INSN_SW, & mep_mep_model::model_sw_before, & mep_mep_model::model_sw_after, { { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_USE_GPR, 0, 0 }, { mep_mep_model::UNIT_U_EXEC, 1, 1 } } },
{ MEP_INSN_RI_21, & mep_mep_model::model_ri_21_before, & mep_mep_model::model_ri_21_after, { { mep_mep_model::UNIT_U_EXEC, 1, 1 }, { mep_mep_model::UNIT_U_BRANCH, 0, 0 } } },
{ MEP_INSN_RI_22, & mep_mep_model::model_ri_22_before, & mep_mep_model::model_ri_22_after, { { mep_mep_model::UNIT_U_EXEC, 1, 1 }, { mep_mep_model::UNIT_U_BRANCH, 0, 0 } } },
{ MEP_INSN_RI_23, & mep_mep_model::model_ri_23_before, & mep_mep_model::model_ri_23_after, { { mep_mep_model::UNIT_U_EXEC, 1, 1 }, { mep_mep_model::UNIT_U_BRANCH, 0, 0 } } },
- { MEP_INSN_RI_24, & mep_mep_model::model_ri_24_before, & mep_mep_model::model_ri_24_after, { { mep_mep_model::UNIT_U_EXEC, 1, 1 }, { mep_mep_model::UNIT_U_BRANCH, 0, 0 } } },
- { MEP_INSN_RI_25, & mep_mep_model::model_ri_25_before, & mep_mep_model::model_ri_25_after, { { mep_mep_model::UNIT_U_EXEC, 1, 1 }, { mep_mep_model::UNIT_U_BRANCH, 0, 0 } } },
{ MEP_INSN_RI_26, & mep_mep_model::model_ri_26_before, & mep_mep_model::model_ri_26_after, { { mep_mep_model::UNIT_U_EXEC, 1, 1 }, { mep_mep_model::UNIT_U_BRANCH, 0, 0 } } },
- { MEP_INSN_RI_16, & mep_mep_model::model_ri_16_before, & mep_mep_model::model_ri_16_after, { { mep_mep_model::UNIT_U_EXEC, 1, 1 }, { mep_mep_model::UNIT_U_BRANCH, 0, 0 } } },
- { MEP_INSN_RI_18, & mep_mep_model::model_ri_18_before, & mep_mep_model::model_ri_18_after, { { mep_mep_model::UNIT_U_EXEC, 1, 1 }, { mep_mep_model::UNIT_U_BRANCH, 0, 0 } } },
- { MEP_INSN_RI_19, & mep_mep_model::model_ri_19_before, & mep_mep_model::model_ri_19_after, { { mep_mep_model::UNIT_U_EXEC, 1, 1 }, { mep_mep_model::UNIT_U_BRANCH, 0, 0 } } },
};
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
This file is part of the Red Hat simulators.
protected:
// These methods call the appropriate unit modeller(s) for each insn.
+ UINT model_stcb_r_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_stcb_r_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_ldcb_r_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_ldcb_r_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_pref_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_pref_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_prefd_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_prefd_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_casb3_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_casb3_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_cash3_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_cash3_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_casw3_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_casw3_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_sbcp_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_sbcp_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lbcp_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lbcp_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lbucp_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lbucp_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_shcp_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_shcp_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lhcp_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lhcp_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lhucp_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lhucp_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lbucpa_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lbucpa_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lhucpa_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lhucpa_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lbucpm0_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lbucpm0_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lhucpm0_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lhucpm0_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lbucpm1_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lbucpm1_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lhucpm1_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_lhucpm1_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_uci_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_uci_after (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_dsp_before (mep_basic_cpu *current_cpu, mep_scache *sem);
+ UINT model_dsp_after (mep_basic_cpu *current_cpu, mep_scache *sem);
UINT model_sb_before (mep_basic_cpu *current_cpu, mep_scache *sem);
UINT model_sb_after (mep_basic_cpu *current_cpu, mep_scache *sem);
UINT model_sh_before (mep_basic_cpu *current_cpu, mep_scache *sem);
UINT model_ri_22_after (mep_basic_cpu *current_cpu, mep_scache *sem);
UINT model_ri_23_before (mep_basic_cpu *current_cpu, mep_scache *sem);
UINT model_ri_23_after (mep_basic_cpu *current_cpu, mep_scache *sem);
- UINT model_ri_24_before (mep_basic_cpu *current_cpu, mep_scache *sem);
- UINT model_ri_24_after (mep_basic_cpu *current_cpu, mep_scache *sem);
- UINT model_ri_25_before (mep_basic_cpu *current_cpu, mep_scache *sem);
- UINT model_ri_25_after (mep_basic_cpu *current_cpu, mep_scache *sem);
UINT model_ri_26_before (mep_basic_cpu *current_cpu, mep_scache *sem);
UINT model_ri_26_after (mep_basic_cpu *current_cpu, mep_scache *sem);
- UINT model_ri_16_before (mep_basic_cpu *current_cpu, mep_scache *sem);
- UINT model_ri_16_after (mep_basic_cpu *current_cpu, mep_scache *sem);
- UINT model_ri_18_before (mep_basic_cpu *current_cpu, mep_scache *sem);
- UINT model_ri_18_after (mep_basic_cpu *current_cpu, mep_scache *sem);
- UINT model_ri_19_before (mep_basic_cpu *current_cpu, mep_scache *sem);
- UINT model_ri_19_after (mep_basic_cpu *current_cpu, mep_scache *sem);
/* Enum declaration for unit types. */
typedef enum unit_number {
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
This file is part of the Red Hat simulators.
#undef FLD
}
+// ********** stcb_r: stcb $rn,($rma)
+
+sem_status
+mep_sem_stcb_r (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_stcb_r.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 2;
+
+current_cpu->do_stcb (* FLD (i_rn), ANDSI (* FLD (i_rma), 65535));
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** ldcb_r: ldcb $rn,($rma)
+
+sem_status
+mep_sem_ldcb_r (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 2;
+
+ {
+ SI opval = current_cpu->do_ldcb (ANDSI (* FLD (i_rma), 65535));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rn) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rn) = opval;
+ }
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** pref: pref $cimm4,($rma)
+
+sem_status
+mep_sem_pref (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 2;
+
+{
+current_cpu->check_option_dcache (pc);
+current_cpu->do_cache_prefetch (FLD (f_rn), * FLD (i_rma), pc);
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** prefd: pref $cimm4,$sdisp16($rma)
+
+sem_status
+mep_sem_prefd (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lhu16.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_dcache (pc);
+current_cpu->do_cache_prefetch (FLD (f_rn), ADDSI (* FLD (i_rma), EXTSISI (FLD (f_16s16))), pc);
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** casb3: casb3 $rl5,$rn,($rm)
+
+sem_status
+mep_sem_casb3 (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->do_casb3 (FLD (f_rl5), * FLD (i_rn), * FLD (i_rm), pc);
+ {
+ SI opval = * FLD (i_rl5);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rl5) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rl5) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** cash3: cash3 $rl5,$rn,($rm)
+
+sem_status
+mep_sem_cash3 (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->do_cash3 (FLD (f_rl5), * FLD (i_rn), * FLD (i_rm), pc);
+ {
+ SI opval = * FLD (i_rl5);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rl5) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rl5) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** casw3: casw3 $rl5,$rn,($rm)
+
+sem_status
+mep_sem_casw3 (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_casb3.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->do_casw3 (FLD (f_rl5), * FLD (i_rn), * FLD (i_rm), pc);
+ {
+ SI opval = * FLD (i_rl5);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rl5) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rl5) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** sbcp: sbcp $crn,$cdisp12($rma)
+
+sem_status
+mep_sem_sbcp (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+current_cpu->check_write_to_text (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20))));
+ {
+ QI opval = ANDSI (current_cpu->h_cr_get (FLD (f_crn)), 255);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "memory" << '[' << "0x" << hex << (UDI) ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20))) << dec << ']' << ":=0x" << hex << (SI) opval << dec << " ";
+ current_cpu->SETMEMQI (pc, ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20))), opval);
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lbcp: lbcp $crn,$cdisp12($rma)
+
+sem_status
+mep_sem_lbcp (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = EXTQISI (current_cpu->GETMEMQI (pc, ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20)))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lbucp: lbucp $crn,$cdisp12($rma)
+
+sem_status
+mep_sem_lbucp (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTQISI (current_cpu->GETMEMQI (pc, ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20)))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** shcp: shcp $crn,$cdisp12($rma)
+
+sem_status
+mep_sem_shcp (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+current_cpu->check_write_to_text (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20))));
+ {
+ HI opval = ANDSI (current_cpu->h_cr_get (FLD (f_crn)), 65535);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "memory" << '[' << "0x" << hex << (UDI) ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20))) << dec << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->SETMEMHI (pc, ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20))), opval);
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lhcp: lhcp $crn,$cdisp12($rma)
+
+sem_status
+mep_sem_lhcp (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = EXTHISI (current_cpu->GETMEMHI (pc, ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20)))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lhucp: lhucp $crn,$cdisp12($rma)
+
+sem_status
+mep_sem_lhucp (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_sbcp.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTHISI (current_cpu->GETMEMHI (pc, ADDSI (* FLD (i_rma), EXTSISI (FLD (f_12s20)))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lbucpa: lbucpa $crn,($rma+),$cdisp10
+
+sem_status
+mep_sem_lbucpa (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTQISI (current_cpu->GETMEMQI (pc, * FLD (i_rma)));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+ {
+ SI opval = ADDSI (* FLD (i_rma), FLD (f_cdisp10));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rma) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lhucpa: lhucpa $crn,($rma+),$cdisp10a2
+
+sem_status
+mep_sem_lhucpa (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTHISI (current_cpu->GETMEMHI (pc, ANDSI (* FLD (i_rma), INVSI (1))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+ {
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rma) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lbucpm0: lbucpm0 $crn,($rma+),$cdisp10
+
+sem_status
+mep_sem_lbucpm0 (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTQISI (current_cpu->GETMEMQI (pc, * FLD (i_rma)));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+ {
+ SI opval = ({ SI tmp_modulo_mask;
+ tmp_modulo_mask = ({ SI tmp_temp;
+ tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
+; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rma) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lhucpm0: lhucpm0 $crn,($rma+),$cdisp10a2
+
+sem_status
+mep_sem_lhucpm0 (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTHISI (current_cpu->GETMEMHI (pc, ANDSI (* FLD (i_rma), INVSI (1))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+ {
+ SI opval = ({ SI tmp_modulo_mask;
+ tmp_modulo_mask = ({ SI tmp_temp;
+ tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
+; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rma) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lbucpm1: lbucpm1 $crn,($rma+),$cdisp10
+
+sem_status
+mep_sem_lbucpm1 (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTQISI (current_cpu->GETMEMQI (pc, * FLD (i_rma)));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+ {
+ SI opval = ({ SI tmp_modulo_mask;
+ tmp_modulo_mask = ({ SI tmp_temp;
+ tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
+; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rma) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** lhucpm1: lhucpm1 $crn,($rma+),$cdisp10a2
+
+sem_status
+mep_sem_lhucpm1 (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = ZEXTHISI (current_cpu->GETMEMHI (pc, ANDSI (* FLD (i_rma), INVSI (1))));
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr_set (FLD (f_crn), opval);
+ }
+ {
+ SI opval = ({ SI tmp_modulo_mask;
+ tmp_modulo_mask = ({ SI tmp_temp;
+ tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
+; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rma) = opval;
+ }
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** uci: uci $rn,$rm,$uimm16
+
+sem_status
+mep_sem_uci (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_uci.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+ {
+ SI opval = current_cpu->do_UCI (* FLD (i_rn), * FLD (i_rm), ZEXTSISI (FLD (f_16u16)), pc);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rn) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rn) = opval;
+ }
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** dsp: dsp $rn,$rm,$uimm16
+
+sem_status
+mep_sem_dsp (mep_basic_cpu* current_cpu, mep_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_uci.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mep_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+ {
+ SI opval = current_cpu->do_DSP (* FLD (i_rn), * FLD (i_rm), ZEXTSISI (FLD (f_16u16)), pc);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "gpr" << '[' << FLD (f_rn) << ']' << ":=0x" << hex << opval << dec << " ";
+ * FLD (i_rn) = opval;
+ }
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
// ********** sb: sb $rnc,($rma)
sem_status
sem_status
mep_sem_mov (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_movu16 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_movh (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_neg (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_sltu3x (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_or3 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_and3 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_xor3 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_stcb (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_stcb.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_ldcb (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_uci.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_tas (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_cache (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_tas.f
+#define FLD(f) abuf->fields.sfmt_ldcb_r.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_ldz (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sltu3x.f
+#define FLD(f) abuf->fields.sfmt_add3x.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_swcpi (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_lwcpi (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_smcpi (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
sem_status
mep_sem_lmcpi (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
#undef FLD
}
-// ********** sbcpa: sbcpa $crn,($rma+),$cdisp8
+// ********** sbcpa: sbcpa $crn,($rma+),$cdisp10
sem_status
mep_sem_sbcpa (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->SETMEMQI (pc, * FLD (i_rma), opval);
}
{
- SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24)));
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lbcpa: lbcpa $crn,($rma+),$cdisp8
+// ********** lbcpa: lbcpa $crn,($rma+),$cdisp10
sem_status
mep_sem_lbcpa (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->h_cr_set (FLD (f_crn), opval);
}
{
- SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24)));
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** shcpa: shcpa $crn,($rma+),$cdisp8a2
+// ********** shcpa: shcpa $crn,($rma+),$cdisp10a2
sem_status
mep_sem_shcpa (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->SETMEMHI (pc, ANDSI (* FLD (i_rma), INVSI (1)), opval);
}
{
- SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a2)));
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lhcpa: lhcpa $crn,($rma+),$cdisp8a2
+// ********** lhcpa: lhcpa $crn,($rma+),$cdisp10a2
sem_status
mep_sem_lhcpa (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->h_cr_set (FLD (f_crn), opval);
}
{
- SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a2)));
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** swcpa: swcpa $crn,($rma+),$cdisp8a4
+// ********** swcpa: swcpa $crn,($rma+),$cdisp10a4
sem_status
mep_sem_swcpa (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->SETMEMSI (pc, ANDSI (* FLD (i_rma), INVSI (3)), opval);
}
{
- SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a4)));
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lwcpa: lwcpa $crn,($rma+),$cdisp8a4
+// ********** lwcpa: lwcpa $crn,($rma+),$cdisp10a4
sem_status
mep_sem_lwcpa (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->h_cr_set (FLD (f_crn), opval);
}
{
- SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a4)));
+ SI opval = ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10)));
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** smcpa: smcpa $crn64,($rma+),$cdisp8a8
+// ********** smcpa: smcpa $crn64,($rma+),$cdisp10a8
sem_status
mep_sem_smcpa (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->check_option_cp (pc);
current_cpu->check_option_cp64 (pc);
current_cpu->check_write_to_text (* FLD (i_rma));
-current_cpu->do_smcpa (FLD (f_rm), FLD (f_8s24a8), current_cpu->hardware.h_cr64[FLD (f_crn)], pc);
+current_cpu->do_smcpa (FLD (f_rm), FLD (f_cdisp10), current_cpu->hardware.h_cr64[FLD (f_crn)], pc);
{
SI opval = * FLD (i_rma);
if (UNLIKELY(current_cpu->trace_result_p))
#undef FLD
}
-// ********** lmcpa: lmcpa $crn64,($rma+),$cdisp8a8
+// ********** lmcpa: lmcpa $crn64,($rma+),$cdisp10a8
sem_status
mep_sem_lmcpa (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
current_cpu->check_option_cp (pc);
current_cpu->check_option_cp64 (pc);
{
- DI opval = current_cpu->do_lmcpa (FLD (f_rm), FLD (f_8s24a8), pc);
+ DI opval = current_cpu->do_lmcpa (FLD (f_rm), FLD (f_cdisp10), pc);
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "cr64" << '[' << FLD (f_crn) << ']' << ":=0x" << hex << opval << dec << " ";
current_cpu->hardware.h_cr64[FLD (f_crn)] = opval;
#undef FLD
}
-// ********** sbcpm0: sbcpm0 $crn,($rma+),$cdisp8
+// ********** sbcpm0: sbcpm0 $crn,($rma+),$cdisp10
sem_status
mep_sem_sbcpm0 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lbcpm0: lbcpm0 $crn,($rma+),$cdisp8
+// ********** lbcpm0: lbcpm0 $crn,($rma+),$cdisp10
sem_status
mep_sem_lbcpm0 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** shcpm0: shcpm0 $crn,($rma+),$cdisp8a2
+// ********** shcpm0: shcpm0 $crn,($rma+),$cdisp10a2
sem_status
mep_sem_shcpm0 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a2))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lhcpm0: lhcpm0 $crn,($rma+),$cdisp8a2
+// ********** lhcpm0: lhcpm0 $crn,($rma+),$cdisp10a2
sem_status
mep_sem_lhcpm0 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a2))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** swcpm0: swcpm0 $crn,($rma+),$cdisp8a4
+// ********** swcpm0: swcpm0 $crn,($rma+),$cdisp10a4
sem_status
mep_sem_swcpm0 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a4))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lwcpm0: lwcpm0 $crn,($rma+),$cdisp8a4
+// ********** lwcpm0: lwcpm0 $crn,($rma+),$cdisp10a4
sem_status
mep_sem_lwcpm0 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a4))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** smcpm0: smcpm0 $crn64,($rma+),$cdisp8a8
+// ********** smcpm0: smcpm0 $crn64,($rma+),$cdisp10a8
sem_status
mep_sem_smcpm0 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a8))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lmcpm0: lmcpm0 $crn64,($rma+),$cdisp8a8
+// ********** lmcpm0: lmcpm0 $crn64,($rma+),$cdisp10a8
sem_status
mep_sem_lmcpm0 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm0.f
+#define FLD(f) abuf->fields.sfmt_lbucpm0.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 12)), current_cpu->h_csr_get (((UINT) 13)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a8))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 13)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 12)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** sbcpm1: sbcpm1 $crn,($rma+),$cdisp8
+// ********** sbcpm1: sbcpm1 $crn,($rma+),$cdisp10
sem_status
mep_sem_sbcpm1 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lbcpm1: lbcpm1 $crn,($rma+),$cdisp8
+// ********** lbcpm1: lbcpm1 $crn,($rma+),$cdisp10
sem_status
mep_sem_lbcpm1 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_sbcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** shcpm1: shcpm1 $crn,($rma+),$cdisp8a2
+// ********** shcpm1: shcpm1 $crn,($rma+),$cdisp10a2
sem_status
mep_sem_shcpm1 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a2))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lhcpm1: lhcpm1 $crn,($rma+),$cdisp8a2
+// ********** lhcpm1: lhcpm1 $crn,($rma+),$cdisp10a2
sem_status
mep_sem_lhcpm1 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_shcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a2))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** swcpm1: swcpm1 $crn,($rma+),$cdisp8a4
+// ********** swcpm1: swcpm1 $crn,($rma+),$cdisp10a4
sem_status
mep_sem_swcpm1 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a4))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lwcpm1: lwcpm1 $crn,($rma+),$cdisp8a4
+// ********** lwcpm1: lwcpm1 $crn,($rma+),$cdisp10a4
sem_status
mep_sem_lwcpm1 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_swcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a4))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** smcpm1: smcpm1 $crn64,($rma+),$cdisp8a8
+// ********** smcpm1: smcpm1 $crn64,($rma+),$cdisp10a8
sem_status
mep_sem_smcpm1 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a8))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** lmcpm1: lmcpm1 $crn64,($rma+),$cdisp8a8
+// ********** lmcpm1: lmcpm1 $crn64,($rma+),$cdisp10a8
sem_status
mep_sem_lmcpm1 (mep_basic_cpu* current_cpu, mep_scache* sem)
{
-#define FLD(f) abuf->fields.sfmt_smcpm1.f
+#define FLD(f) abuf->fields.sfmt_lbucpm1.f
sem_status status = SEM_STATUS_NORMAL;
mep_scache* abuf = sem;
unsigned long long written = 0;
tmp_modulo_mask = ({ SI tmp_temp;
tmp_temp = ORSI (current_cpu->h_csr_get (((UINT) 14)), current_cpu->h_csr_get (((UINT) 15)));
; SRLSI (-1, current_cpu->do_ldz (tmp_temp)); });
-; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_8s24a8))))); });
+; ((EQSI (ANDSI (* FLD (i_rma), tmp_modulo_mask), current_cpu->h_csr_get (((UINT) 15)))) ? (ORSI (ANDSI (* FLD (i_rma), INVSI (tmp_modulo_mask)), current_cpu->h_csr_get (((UINT) 14)))) : (ADDSI (* FLD (i_rma), EXTSISI (FLD (f_cdisp10))))); });
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "gpr" << '[' << FLD (f_rm) << ']' << ":=0x" << hex << opval << dec << " ";
* FLD (i_rma) = opval;
#undef FLD
}
-// ********** ri-24: --reserved--
-
-sem_status
-mep_sem_ri_24 (mep_basic_cpu* current_cpu, mep_scache* sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- sem_status status = SEM_STATUS_NORMAL;
- mep_scache* abuf = sem;
- unsigned long long written = 0;
- PCADDR pc = abuf->addr;
- PCADDR npc = pc + 2;
-
- {
- USI opval = current_cpu->ri_exception (pc);
- if (UNLIKELY(current_cpu->trace_result_p))
- current_cpu->trace_stream << "pc" << ":=0x" << hex << opval << dec << " ";
- current_cpu->branch (opval, npc, status);
- }
-
- current_cpu->done_cti_insn (npc, status);
- return status;
-#undef FLD
-}
-
-// ********** ri-25: --reserved--
-
-sem_status
-mep_sem_ri_25 (mep_basic_cpu* current_cpu, mep_scache* sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- sem_status status = SEM_STATUS_NORMAL;
- mep_scache* abuf = sem;
- unsigned long long written = 0;
- PCADDR pc = abuf->addr;
- PCADDR npc = pc + 2;
-
- {
- USI opval = current_cpu->ri_exception (pc);
- if (UNLIKELY(current_cpu->trace_result_p))
- current_cpu->trace_stream << "pc" << ":=0x" << hex << opval << dec << " ";
- current_cpu->branch (opval, npc, status);
- }
-
- current_cpu->done_cti_insn (npc, status);
- return status;
-#undef FLD
-}
-
// ********** ri-26: --reserved--
sem_status
#undef FLD
}
-// ********** ri-16: --reserved--
-
-sem_status
-mep_sem_ri_16 (mep_basic_cpu* current_cpu, mep_scache* sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- sem_status status = SEM_STATUS_NORMAL;
- mep_scache* abuf = sem;
- unsigned long long written = 0;
- PCADDR pc = abuf->addr;
- PCADDR npc = pc + 2;
-
- {
- USI opval = current_cpu->ri_exception (pc);
- if (UNLIKELY(current_cpu->trace_result_p))
- current_cpu->trace_stream << "pc" << ":=0x" << hex << opval << dec << " ";
- current_cpu->branch (opval, npc, status);
- }
-
- current_cpu->done_cti_insn (npc, status);
- return status;
-#undef FLD
-}
-
-// ********** ri-18: --reserved--
-
-sem_status
-mep_sem_ri_18 (mep_basic_cpu* current_cpu, mep_scache* sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- sem_status status = SEM_STATUS_NORMAL;
- mep_scache* abuf = sem;
- unsigned long long written = 0;
- PCADDR pc = abuf->addr;
- PCADDR npc = pc + 2;
-
- {
- USI opval = current_cpu->ri_exception (pc);
- if (UNLIKELY(current_cpu->trace_result_p))
- current_cpu->trace_stream << "pc" << ":=0x" << hex << opval << dec << " ";
- current_cpu->branch (opval, npc, status);
- }
-
- current_cpu->done_cti_insn (npc, status);
- return status;
-#undef FLD
-}
-
-// ********** ri-19: --reserved--
-
-sem_status
-mep_sem_ri_19 (mep_basic_cpu* current_cpu, mep_scache* sem)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
- sem_status status = SEM_STATUS_NORMAL;
- mep_scache* abuf = sem;
- unsigned long long written = 0;
- PCADDR pc = abuf->addr;
- PCADDR npc = pc + 2;
-
- {
- USI opval = current_cpu->ri_exception (pc);
- if (UNLIKELY(current_cpu->trace_result_p))
- current_cpu->trace_stream << "pc" << ":=0x" << hex << opval << dec << " ";
- current_cpu->branch (opval, npc, status);
- }
-
- current_cpu->done_cti_insn (npc, status);
- return status;
-#undef FLD
-}
-
add_watchable_pin ("cache-index-invalidate", &cache_index_invalidate_pin);
add_watchable_pin ("cache-index-flush-and-invalidate", &cache_index_flush_and_invalidate_pin);
add_watchable_pin ("cache-prefetch", &cache_prefetch_pin);
+ add_watchable_pin ("cache-write-hint", &cache_write_hint_pin);
add_watchable_pin ("data-cache-invalidate-all", &data_cache_invalidate_all_pin);
add_watchable_pin ("insn-cache-invalidate-all", &insn_cache_invalidate_all_pin);
add_watchable_pin ("cache-operation-status", &cache_operation_status_pin);
check_option_dcache (pc);
cache_index_flush_and_invalidate_pin.drive (value);
break;
+ case 5:
+ if (core_type () == CORE_C5)
+ {
+ check_option_dcache (pc);
+ cache_write_hint_pin.drive (value);
+ }
+ break;
case 6: // address
- if (core_type () == CORE_H1)
+ if (core_type () == CORE_H1
+ || core_type () == CORE_C5)
{
check_option_dcache (pc);
cache_invalidate_pin.drive (value);
}
VOID
-mep_cpu::do_cache_prefetch (USI& op, int& rma, PCADDR& pc)
+mep_cpu::do_cache_prefetch (USI& op, int rma, PCADDR& pc)
{
- // Only implemented on the H1 core.
- if (core_type () != CORE_H1)
+ // Only implemented on the H1 and C5 cores.
+ if (core_type () != CORE_H1
+ && core_type () != CORE_C5)
{
invalid_insn (pc);
return;
sleeping_p = true;
}
+// C5 Instructions
+
+VOID
+mep_cpu::do_casb3 (SI rl, SI rn, UINT word_addr, UINT pc)
+{
+ SI temp;
+
+ // Compare and swap byte:
+ // temp <- Rl
+ // Rl <- ZeroExt (MemByte (Rm))
+ // if (temp == Rl)
+ // MemByte (Rm) <- Rn [0..7]
+ // else
+ // MemByte (Rm) <- Rl [0..7]
+
+ temp = h_gpr_get (rl);
+ h_gpr_set (rl, ZEXTQISI (GETMEMQI (pc, word_addr)));
+
+ if (temp == h_gpr_get (rl))
+ SETMEMQI (pc, word_addr, rn);
+ else
+ SETMEMQI (pc, word_addr, rl);
+}
+
+VOID
+mep_cpu::do_cash3 (SI rl, SI rn, UINT word_addr, UINT pc)
+{
+ SI temp;
+
+ temp = h_gpr_get (rl);
+ h_gpr_set (rl, ZEXTHISI (GETMEMHI (pc, word_addr)));
+
+ if (temp == h_gpr_get (rl))
+ SETMEMHI (pc, word_addr, rn);
+ else
+ SETMEMHI (pc, word_addr, rl);
+}
+
+VOID
+mep_cpu::do_casw3 (SI rl, SI rn, UINT word_addr, UINT pc)
+{
+ SI temp;
+
+ temp = h_gpr_get (rl);
+ h_gpr_set (rl, GETMEMSI (pc, word_addr));
+
+ if (temp == h_gpr_get (rl))
+ SETMEMSI (pc, word_addr, rn);
+ else
+ SETMEMSI (pc, word_addr, rl);
+}
+
// UCI/DSP pin protocols
SI
SI do_ldcb (UINT word_addr);
VOID do_stcb (SI rn, UINT word_addr);
VOID do_cache (USI& op, int& addr, PCADDR& pc);
- VOID do_cache_prefetch (USI& op, int& addr, PCADDR& pc);
+ VOID do_cache_prefetch (USI& op, int addr, PCADDR& pc);
VOID do_smcp (USI rma, DI crn, PCADDR &pc);
VOID do_smcpa (UINT rma_ix, SI cdisp8a8, DI crn, PCADDR &pc);
VOID do_sleep ();
VOID check_write_to_text (UINT address);
+ // C5 instructions
+ VOID do_casb3 (SI rl, SI rn, UINT word_addr, UINT pc);
+ VOID do_cash3 (SI rl, SI rn, UINT word_addr, UINT pc);
+ VOID do_casw3 (SI rl, SI rn, UINT word_addr, UINT pc);
+
// Methods for checking if an instruction class is activated.
VOID check_option_abs (PCADDR &pc) { check_option (ABS, pc); }
VOID check_option_ave (PCADDR &pc) { check_option (AVE, pc); }
static const int CORE_C2 = 0x02;
static const int CORE_C3 = 0x03;
static const int CORE_C4 = 0x04;
+ static const int CORE_C5 = 0x50;
static const int CORE_H1 = 0x10;
int core_type () const { return (h_csr_get (17) >> 8) & 0xff; }
- int machine () const { return core_type () == CORE_H1 ? bfd_mach_mep_h1 : bfd_mach_mep; }
- const char *machine_name () const { return core_type () == CORE_H1 ? "h1" : "mep"; }
+ int machine () const { switch (core_type ()) {
+ case CORE_H1 : return bfd_mach_mep_h1;
+ case CORE_C5 : return bfd_mach_mep_c5;
+ default: return bfd_mach_mep; } }
+ const char *machine_name () const { switch (core_type ()) {
+ case CORE_H1 : return "h1";
+ case CORE_C5 : return "c5";
+ default: return "mep"; } }
private:
bool hw_debugger_p;
output_pin cache_flush_and_invalidate_pin;
output_pin cache_index_flush_and_invalidate_pin;
output_pin cache_prefetch_pin;
+ output_pin cache_write_hint_pin;
output_pin data_cache_invalidate_all_pin;
output_pin insn_cache_invalidate_all_pin;
AUTOMAKE_OPTIONS = foreign
pkglib_LTLIBRARIES = libmepfamily.la
INCLUDES = -I. -I../.. -I../../../include -I$(srcdir)/../../../include -I$(srcdir)/toshapi
-TOSHAPI_SOURCES =
+TOSHAPI_SOURCES =
libmepfamily_la_SOURCES = dsu.cxx dmac.cxx intc.cxx components.cxx \
mm_int.cxx timer.cxx gbif.cxx lbif.cxx gbmif.cxx toshapi.cxx $(TOSHAPI_SOURCES)
#define MEP_CORE_C2 0x02
#define MEP_CORE_C3 0x03
#define MEP_CORE_C4 0x04
+#define MEP_CORE_C5 0x08
#define MEP_CORE_H1 0x10
class mep_dsu;
big_int_4 get_ibc0_te () { return ibc0_te; }
void set_ibc0_te (big_int_4 value, big_int_4 mask)
{
- if (core_type == MEP_CORE_C4 || core_type == MEP_CORE_H1)
+ if (core_type == MEP_CORE_C4 || core_type == MEP_CORE_H1
+ || core_type == MEP_CORE_C5)
ibc0_te = value & mask;
}
big_int_4 get_dbc0_te () { return dbc0_te; }
void set_dbc0_te (big_int_4 value, big_int_4 mask)
{
- if (core_type == MEP_CORE_C4 || core_type == MEP_CORE_H1)
+ if (core_type == MEP_CORE_C4 || core_type == MEP_CORE_H1
+ || core_type == MEP_CORE_C5)
dbc0_te = value & mask;
}
mk_default (const string name, SessionCfg *sess)
{
MepBoardCfg *b = new MepBoardCfg (name, "default", sess);
- b->set_core_type (MEP_CORE_C4);
+ b->set_core_type (MEP_CORE_C5);
b->set_cpu ("mep-ext1");
b->add_irq_board ();
b->set_imem_size (32);
conn_pin (my_cpu, "cache-flush-and-invalidate", my_cache, "flush-and-invalidate");
conn_pin (my_cpu, "cache-index-flush-and-invalidate", my_cache, "flush-and-invalidate-set");
conn_pin (my_cpu, "cache-prefetch", my_cache, "prefetch");
+ conn_pin (my_cpu, "cache-write-hint", my_cache, "write-hint");
conn_pin (my_cpu, "data-cache-invalidate-all", my_cache, "invalidate-all");
if (bit_insn_probe)
#define MEP_CORE_C2 0x02
#define MEP_CORE_C3 0x03
#define MEP_CORE_C4 0x04
+#define MEP_CORE_C5 0x08
#define MEP_CORE_H1 0x10
class MepBoardCfg :
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