{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
env->vstart = 0; \
+ /* mask destination register are always tail-agnostic */ \
+ /* set tail elements to 1s */ \
+ if (vta_all_1s) { \
+ for (; i < total_elems; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
+ } \
}
GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
env->vstart = 0; \
+ /* mask destination register are always tail-agnostic */ \
+ /* set tail elements to 1s */ \
+ if (vta_all_1s) { \
+ for (; i < total_elems; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
+ } \
}
GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)