drm/amd/display: Implement voltage limitation stub

add new function to get the voltage at the end of
dcn_validate_bandwidth, to check against the
highest voltage we allow.

Created a stub to allow for optimizations

Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Sun peng Li <Sunpeng.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 061c6e3..383f4f8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -705,6 +705,13 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v,
                hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
 }
 
+
+unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev)
+{
+       /* we are ok with all levels */
+       return 4;
+}
+
 bool dcn_validate_bandwidth(
                struct dc *dc,
                struct dc_state *context,
@@ -732,6 +739,7 @@ bool dcn_validate_bandwidth(
 
        memset(v, 0, sizeof(*v));
        kernel_fpu_begin();
+
        v->sr_exit_time = dc->dcn_soc->sr_exit_time;
        v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
        v->urgent_latency = dc->dcn_soc->urgent_latency;
@@ -1268,7 +1276,7 @@ bool dcn_validate_bandwidth(
        PERFORMANCE_TRACE_END();
        BW_VAL_TRACE_FINISH();
 
-       if (bw_limit_pass && v->voltage_level != 5)
+       if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->ctx->asic_id.hw_internal_rev))
                return true;
        else
                return false;