arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node

Uart5 is treated as dedicated debug uart.Change the
compatible as "qcom,geni-uart" in SoC DT to make it generic
and later update it as "qcom,geni-debug-uart" in sc7280-idp
Add interconnects and power-domains. Split the pinctrl
functions and correct the gpio pins.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1632399378-12229-6-git-send-email-rajpat@codeaurora.org

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 5297479..c93e218 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -279,6 +279,7 @@
 };
 
 &uart5 {
+       compatible = "qcom,geni-debug-uart";
        status = "okay";
 };
 
@@ -347,18 +348,14 @@
        bias-pull-up;
 };
 
-&qup_uart5_default {
-       tx {
-               pins = "gpio46";
-               drive-strength = <2>;
-               bias-disable;
-       };
+&qup_uart5_tx {
+       drive-strength = <2>;
+       bias-disable;
+};
 
-       rx {
-               pins = "gpio47";
-               drive-strength = <2>;
-               bias-pull-up;
-       };
+&qup_uart5_rx {
+       drive-strength = <2>;
+       bias-pull-up;
 };
 
 &sdc1_on {

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index ec6faa5..1cb20bd 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -900,13 +900,18 @@
                        };
 
                        uart5: serial@994000 {
-                               compatible = "qcom,geni-debug-uart";
+                               compatible = "qcom,geni-uart";
                                reg = <0 0x00994000 0 0x4000>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
                                clock-names = "se";
                                pinctrl-names = "default";
-                               pinctrl-0 = <&qup_uart5_default>;
+                               pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
                                interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+                               power-domains = <&rpmhpd SC7280_CX>;
+                               operating-points-v2 = <&qup_opp_table>;
+                               interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+                                               <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+                               interconnect-names = "qup-core", "qup-config";
                                status = "disabled";
                        };
 
@@ -2405,9 +2410,24 @@
                                function = "qup04";
                        };
 
-                       qup_uart5_default: qup-uart5-default {
-                               pins = "gpio46", "gpio47";
-                               function = "qup13";
+                       qup_uart5_cts: qup-uart5-cts {
+                               pins = "gpio20";
+                               function = "qup05";
+                       };
+
+                       qup_uart5_rts: qup-uart5-rts {
+                               pins = "gpio21";
+                               function = "qup05";
+                       };
+
+                       qup_uart5_tx: qup-uart5-tx {
+                               pins = "gpio22";
+                               function = "qup05";
+                       };
+
+                       qup_uart5_rx: qup-uart5-rx {
+                               pins = "gpio23";
+                               function = "qup05";
                        };
 
                        qup_uart6_cts: qup-uart6-cts {