port ( base_clk : in std_logic;
reset_n : in std_logic;
cpu_clk : out std_logic;
- ppu_clk : out std_logic
+ ppu_clk : out std_logic;
+ vga_clk : out std_logic
);
end clock_divider;
architecture rtl of clock_divider is
-constant cpu_division : integer := 12;
-constant ppu_division : integer := 4;
-
-signal loop4 : std_logic_vector (1 downto 0);
+signal loop2 : std_logic_vector (0 downto 0);
signal loop6 : std_logic_vector (2 downto 0);
-signal tmp : std_logic;
+signal cpu_cnt_rst_n : std_logic;
+signal cpu_clk_new : std_logic;
+signal cpu_clk_old : std_logic;
+signal cpu_we_n : std_logic;
+
+component counter_register
+ generic (
+ dsize : integer := 8;
+ inc : integer := 1
+ );
+ port ( clk : in std_logic;
+ rst_n : in std_logic;
+ ce_n : in std_logic;
+ we_n : in std_logic;
+ d : in std_logic_vector(dsize - 1 downto 0);
+ q : out std_logic_vector(dsize - 1 downto 0)
+ );
+end component;
+
+component d_flip_flop_bit
+ port (
+ clk : in std_logic;
+ res_n : in std_logic;
+ set_n : in std_logic;
+ we_n : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+ );
+end component;
begin
+ ---base clock 25 MHz = VGA clock.
+ cpu_clk_old <= not cpu_clk_new;
+ cpu_clk <= cpu_clk_new;
+ ppu_clk <= loop2(0);
+ vga_clk <= base_clk;
+
+ cpu_cnt_rst_n <= '0' when reset_n = '0' else
+ '0' when loop6 = "110" else
+ '1';
+ cpu_we_n <= '0' when loop6 = "101" else
+ '1';
+
+ ppu_clk_cnt : counter_register generic map (1) port map
+ (base_clk, reset_n, '0', '1', (others=>'0'), loop2);
+
+ cpu_clk_cnt : counter_register generic map (3) port map
+ (base_clk, cpu_cnt_rst_n, '0', '1', (others=>'0'), loop6);
- ppu_clk <= not loop4(1);
- cpu_clk <= tmp;
-
- main_p : process (reset_n, base_clk)
- variable i : integer;
- begin
- if (reset_n'event) then
- if (reset_n = '0') then
- loop4 <= (others => '1');
- loop6 <= "101";
- tmp <= '0';
- end if;
- elsif (base_clk'event and base_clk = '1') then
- loop4 <= loop4 + '1';
- loop6 <= loop6 + '1';
- if (loop6 = "101") then
- loop6 <= (others => '0');
- tmp <= not tmp;
- end if;
- end if;
- end process;
+ cpu_clk_cnt2 : d_flip_flop_bit port map
+ (base_clk, reset_n, '1', cpu_we_n, cpu_clk_old, cpu_clk_new);
end rtl;
port ( base_clk : in std_logic;
reset_n : in std_logic;
cpu_clk : out std_logic;
- ppu_clk : out std_logic
+ ppu_clk : out std_logic;
+ vga_clk : out std_logic
);
end component;
constant base_clock_time : time := 46 ns;
constant reset_time : time := 100 ns;
- signal bbase, rreset_n, ccpu, pppu : std_logic;
+ signal bbase, rreset_n, ccpu, pppu, vvga : std_logic;
begin
- dut: clock_divider port map (bbase, rreset_n, ccpu, pppu);
+ dut: clock_divider port map (bbase, rreset_n, ccpu, pppu, vvga);
clock_p: process
begin
port ( base_clk : in std_logic;
reset_n : in std_logic;
cpu_clk : out std_logic;
- ppu_clk : out std_logic
+ ppu_clk : out std_logic;
+ vga_clk : out std_logic
);
end component;
end component;
---clock frequency = 21,477,270 (21 MHz)
- constant base_clock_time : time := 46 ns;
- constant vga_clk_time : time := 40 ns;
+ --constant base_clock_time : time := 46 ns;
+ --base clock frequency shares vga clock.
+ constant base_clock_time : time := 40 ns;
constant data_size : integer := 8;
constant addr_size : integer := 16;
constant size14 : integer := 14;
wait for base_clock_time / 2;
end process;
- --- generate test vga clock.
- vga_clock_p : process
- begin
- vga_clk <= '1';
- wait for vga_clk_time / 2;
- vga_clk <= '0';
- wait for vga_clk_time / 2;
- end process;
-
--ppu/cpu clock generator
clock_inst : clock_divider port map
- (base_clk, rst_n, cpu_clk, ppu_clk);
+ (base_clk, rst_n, cpu_clk, ppu_clk, vga_clk);
--mos 6502 cpu instance
cpu_inst : mos6502 generic map (data_size, addr_size)