mmc: sdhci-of-arasan: Add intel Thunder Bay SOC support to the arasan eMMC driver

Intel Thunder Bay SoC eMMC controller is based on Arasan
eMMC 5.1 host controller IP

Signed-off-by: Rashmi A <rashmi.a@intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20210829182443.30802-2-rashmi.a@intel.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 737e2bf..6a2e5a4 100644 (file)
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -191,6 +191,13 @@ static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
        .hiword_update = false,
 };
 
+static const struct sdhci_arasan_soc_ctl_map thunderbay_soc_ctl_map = {
+       .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
+       .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
+       .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
+       .hiword_update = false,
+};
+
 static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
        .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
        .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
@@ -456,6 +463,15 @@ static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
                        SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
 };
 
+static const struct sdhci_pltfm_data sdhci_arasan_thunderbay_pdata = {
+       .ops = &sdhci_arasan_cqe_ops,
+       .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
+       .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+               SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
+               SDHCI_QUIRK2_STOP_WITH_TC |
+               SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
+};
+
 #ifdef CONFIG_PM_SLEEP
 /**
  * sdhci_arasan_suspend - Suspend method for the driver
@@ -1132,6 +1148,12 @@ static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
        .clk_ops = &arasan_clk_ops,
 };
 
+static const struct sdhci_arasan_of_data sdhci_arasan_thunderbay_data = {
+       .soc_ctl_map = &thunderbay_soc_ctl_map,
+       .pdata = &sdhci_arasan_thunderbay_pdata,
+       .clk_ops = &arasan_clk_ops,
+};
+
 static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
        .ops = &sdhci_arasan_cqe_ops,
        .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
@@ -1265,6 +1287,10 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
                .compatible = "intel,keembay-sdhci-5.1-sdio",
                .data = &intel_keembay_sdio_data,
        },
+       {
+               .compatible = "intel,thunderbay-sdhci-5.1",
+               .data = &sdhci_arasan_thunderbay_data,
+       },
        /* Generic compatible below here */
        {
                .compatible = "arasan,sdhci-8.9a",
@@ -1626,7 +1652,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
 
        if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
            of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
-           of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
+           of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio") ||
+           of_device_is_compatible(np, "intel,thunderbay-sdhci-5.1")) {
                sdhci_arasan_update_clockmultiplier(host, 0x0);
                sdhci_arasan_update_support64b(host, 0x0);