- zp, xy mode supported.

- ldy zp, x supported.
- pg boundary test case for t1 cycle added.

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index 10f430e..b273a8b 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -335,8 +335,18 @@ end procedure;
             end if;
         end if;
     elsif (zp_n = '0') then
-        abh <= "00000000";
-        abl <= bal;
+        if (zp_xy_n <= '0') then
+            a_sel <= ADDR_ADC;
+            addr1 <= bal;
+            addr2 <= index_bus;
+            addr_c_in <= '0';
+
+            abh <= "00000000";
+            abl <= addr_out;
+        else
+            abh <= "00000000";
+            abl <= bal;
+        end if;
 
     elsif (abs_xy_n = '0') then
         if (pg_next_n = '0') then

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index c78ebaf..20e7689 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -506,6 +506,33 @@ begin
     end if;
 end  procedure;
 
+procedure a2_zp_xy (is_x : in boolean) is
+begin
+    if exec_cycle = T1 then
+        fetch_low;
+    elsif exec_cycle = T2 then
+        fetch_stop;
+        --output BAL only
+        fetch_stop;
+        dbuf_int_oe_n <= '0';
+        dl_al_we_n <= '1';
+
+        --calc zp.
+        dl_al_oe_n <= '0';
+        zp_n <= '0';
+        next_cycle <= T3;
+    elsif exec_cycle = T3 then
+        --t3 zp, xy 
+        zp_xy_n <= '0';
+        if (is_x = true) then
+            back_oe(x_cmd, '0');
+        else
+            back_oe(y_cmd, '0');
+        end if;
+        next_cycle <= T0;
+    end if;
+end  procedure;
+
 procedure a2_indir_y is
 begin
     if exec_cycle = T1 then
@@ -1351,6 +1378,11 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#b5#, dsize) then
                     --zp, x
                     d_print("lda");
+                    a2_zp_xy(true);
+                    if exec_cycle = T3 then
+                        front_we(acc_cmd, '0');
+                        set_nz_from_bus;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#ad#, dsize) then
                     --abs
@@ -1477,6 +1509,11 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#b4#, dsize) then
                     --zp, x
                     d_print("ldy");
+                    a2_zp_xy(true);
+                    if exec_cycle = T3 then
+                        front_we(y_cmd, '0');
+                        set_nz_from_bus;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#ac#, dsize) then
                     --abs

diff --git a/tools/test-image/sample1.asm b/tools/test-image/sample1.asm
index 535a863..2fb4e63 100644 (file)
--- a/tools/test-image/sample1.asm
+++ b/tools/test-image/sample1.asm
@@ -181,13 +181,16 @@ boundary_2_3:
        lda     #$01\r
        lda     #$01\r
        lda     #$01\r
+\r
+       ror\r
        lda     #$01\r
-       lda     #$01\r
-       lda     #$01\r
-    ror\r
+       lda     #$de\r
+       sta     $13\r
+\r
+\r
 ;;this is pch increment at next T1 cycle. \r
-    ;;;@83fe\r
-       lda $09, x\r
+    ;;;@83ff\r
+       ldy $09, x\r
 \r
     nop\r
     nop\r