static TCGv_i32 cpu_msr;
static TCGv_i64 cpu_ear;
static TCGv_i32 cpu_esr;
-static TCGv_i64 cpu_edr;
static TCGv_i32 env_imm;
static TCGv_i32 env_btaken;
static TCGv_i32 cpu_btarget;
cpu_env, offsetof(CPUMBState, btr));
break;
case SR_EDR:
- tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]);
+ tcg_gen_st_i32(cpu_R[dc->ra],
+ cpu_env, offsetof(CPUMBState, edr));
break;
case 0x800:
tcg_gen_st_i32(cpu_R[dc->ra],
cpu_env, offsetof(CPUMBState, btr));
break;
case SR_EDR:
- tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr);
+ tcg_gen_ld_i32(cpu_R[dc->rd],
+ cpu_env, offsetof(CPUMBState, edr));
break;
case 0x800:
tcg_gen_ld_i32(cpu_R[dc->rd],
}
/* Registers that aren't modeled are reported as 0 */
- qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 "
+ qemu_fprintf(f, "redr=%x rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 "
"rtlblo=0 rtlbhi=0\n", env->edr);
qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr);
for (i = 0; i < 32; i++) {
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
cpu_esr =
tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr");
- cpu_edr =
- tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr");
}
void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,