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ARM: dts: imx6: add mmdc ipg clock
authorAnson Huang <Anson.Huang@nxp.com>
Fri, 31 Aug 2018 07:53:18 +0000 (15:53 +0800)
committerShawn Guo <shawnguo@kernel.org>
Mon, 5 Nov 2018 02:19:09 +0000 (10:19 +0800)
i.MX6 SoCs has MMDC clock gates in CCM CCGR, add
clock property for MMDC driver's clock operation.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6qdl.dtsi
arch/arm/boot/dts/imx6sl.dtsi
arch/arm/boot/dts/imx6sll.dtsi
arch/arm/boot/dts/imx6sx.dtsi
arch/arm/boot/dts/imx6ul.dtsi

index e4daf15..f782dc0 100644 (file)
                        mmdc0: mmdc@21b0000 { /* MMDC0 */
                                compatible = "fsl,imx6q-mmdc";
                                reg = <0x021b0000 0x4000>;
+                               clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
                        };
 
                        mmdc1: mmdc@21b4000 { /* MMDC1 */
index 7a3ae71..9bbc5b0 100644 (file)
                        mmdc: mmdc@21b0000 {
                                compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
                                reg = <0x021b0000 0x4000>;
+                               clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
                        };
 
                        rngb: rngb@21b4000 {
index ed9a980..e462f76 100644 (file)
                        mmdc: memory-controller@21b0000 {
                                compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
                                reg = <0x021b0000 0x4000>;
+                               clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
                        };
 
                        ocotp: ocotp-ctrl@21bc000 {
index 95a3c1c..84b7687 100644 (file)
                        mmdc: mmdc@21b0000 {
                                compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
                                reg = <0x021b0000 0x4000>;
+                               clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
                        };
 
                        fec2: ethernet@21b4000 {
index 083d344..c71d2d6 100644 (file)
                        mmdc: mmdc@21b0000 {
                                compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
                                reg = <0x021b0000 0x4000>;
+                               clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
                        };
 
                        weim: weim@21b8000 {