Fix Book-E opcodes

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 47e8c23..f26d6ff 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,32 @@
+2002-09-13  Nick Clifton  <nickc@redhat.com>
+
+       * ppc-opc.c (MFDEC2): Include Book-E.
+        (PPCCHLK64): New opcode mask.
+        (evsubw, evsubiw, evmr, evnot, isellt, iselgt, iseleq, mfpid,
+        mfcsrr0, mfcsrr1, mfdear, mfesr, mfivpr, mfusprg0, mftbl,
+        mftbu, mfpir, mfdbsr, mfdbcr0, mfdbcr1, mfdbcr2, mfiac1,
+        mfiac2, mfiac3, mfiac4, mfdac1, mfdac2, mfdvc1, mfdvc2, mftsr,
+        mftcr, mfivor0, mfivor1, mfivor2, mfivor3, mfivor4, mfivor5,
+        mfivor6, mfivor7, mfivor8, mfivor9, mfivor10, mfivor11,
+        mfivor12, mfivor13, mfivor14, mfivor15, mfbbear, mfmcsrr0,
+        mfmcsrr1, mfmcsr, mtpid, mtdecar, mtcsrr0, mtcsrr1, mtdear,
+        mtesr, mtivpr, mtusprg0, mtsprg4, mtsprg5, mtsprg6, mtsprg7,
+        mtdbsr, mtdbcr0, mtdbcr1, mtdbcr2, mtiac1, mtiac2, mtiac3,
+        mtiac4, mtdac1, mtdac2, mtdvc1, mtdvc2, mttsr, mttcr, mtivor0,
+        mtivor1, mtivor2, mtivor3, mtivor4, mtivor5, mtivor6, mtivor7,
+        mtivor8, mtivor9, mtivor10, mtivor11, mtivor12, mtivor13,
+        mtivor14, mtivor15, mtbbear, mtmcsrr0, mtmcsrr1, mtmcsr): New
+        Book-E instructions.
+        (evfsneg): Fix opcode value.
+        (dcbtstlse, dcbtlse, icblce, dcblce, icbtsle): Use PPCCHLK64
+        mask.
+        (mcrxr64, tlbivaxe, tlbsxe, tlbsxe.): Restrict to 64-bit
+        Book-E.
+        (extsw): Restrict to 64-bit PPC instruction sets.
+        (extsw.): Does not exist in 64-bit Book-E.
+        (powerpc_macro): Remove mftbl, mftbu and mftb Book-E macros as
+        they are no longer needed.
+
 2002-09-12  Gary Hade  <garyhade@us.ibm.com>
 
        * ppc-dis.c (powerpc_dialect): Add missing PPC_OPCODE_CLASSIC.

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 1a8627f..623164c 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1766,7 +1766,7 @@ extract_tbr (insn, dialect, invalid)
 #define        M601    PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
 #define        MFDEC1  PPC_OPCODE_POWER
-#define        MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601
+#define        MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
 #define BOOKE  PPC_OPCODE_BOOKE
 #define BOOKE64        PPC_OPCODE_BOOKE64
 #define CLASSIC        PPC_OPCODE_CLASSIC
@@ -1776,6 +1776,7 @@ extract_tbr (insn, dialect, invalid)
 #define PPCBRLK        PPC_OPCODE_BRLOCK
 #define PPCPMR PPC_OPCODE_PMR
 #define PPCCHLK        PPC_OPCODE_CACHELCK
+#define PPCCHLK64      PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
 #define PPCRFMCI       PPC_OPCODE_RFMCI
 \f
 /* The opcode table.
@@ -2089,7 +2090,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "evaddw",    VX(4, 512), VX_MASK,    PPCSPE,         { RD, RA, RB } },
 { "evaddiw",   VX(4, 514), VX_MASK,    PPCSPE,         { RD, RB, UIMM } },
 { "evsubfw",   VX(4, 516), VX_MASK,    PPCSPE,         { RD, RA, RB } },
+{ "evsubw",    VX(4, 516), VX_MASK,    PPCSPE,         { RD, RB, RA } },
 { "evsubifw",  VX(4, 518), VX_MASK,    PPCSPE,         { RD, UIMM, RB } },
+{ "evsubiw",   VX(4, 518), VX_MASK,    PPCSPE,         { RD, RB, UIMM } },
 { "evabs",     VX(4, 520), VX_MASK,    PPCSPE,         { RD, RA } },
 { "evneg",     VX(4, 521), VX_MASK,    PPCSPE,         { RD, RA } },
 { "evextsb",   VX(4, 522), VX_MASK,    PPCSPE,         { RD, RA } },
@@ -2102,11 +2105,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "evand",     VX(4, 529), VX_MASK,    PPCSPE,         { RD, RA, RB } },
 { "evandc",    VX(4, 530), VX_MASK,    PPCSPE,         { RD, RA, RB } },
+{ "evmr",      VX(4, 535), VX_MASK,    PPCSPE,         { RS, RA, BBA } },
 { "evor",      VX(4, 535), VX_MASK,    PPCSPE,         { RD, RA, RB } },
 { "evorc",     VX(4, 539), VX_MASK,    PPCSPE,         { RD, RA, RB } },
 { "evxor",     VX(4, 534), VX_MASK,    PPCSPE,         { RD, RA, RB } },
 { "eveqv",     VX(4, 537), VX_MASK,    PPCSPE,         { RD, RA, RB } },
 { "evnand",    VX(4, 542), VX_MASK,    PPCSPE,         { RD, RA, RB } },
+{ "evnot",     VX(4, 536), VX_MASK,    PPCSPE,         { RS, RA, BBA } },
 { "evnor",     VX(4, 536), VX_MASK,    PPCSPE,         { RD, RA, RB } },
 
 { "evrlw",     VX(4, 552), VX_MASK,    PPCSPE,         { RD, RA, RB } },
@@ -2171,7 +2176,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "evfsabs",   VX(4, 644), VX_MASK,    PPCSPE,         { RD, RA } },
 { "evfsnabs",  VX(4, 645), VX_MASK,    PPCSPE,         { RD, RA } },
-{ "evfsneg",   VX(4, 656), VX_MASK,    PPCSPE,         { RD, RA } },
+{ "evfsneg",   VX(4, 646), VX_MASK,    PPCSPE,         { RD, RA } },
 { "evfsadd",   VX(4, 640), VX_MASK,    PPCSPE,         { RD, RA, RB } },
 { "evfssub",   VX(4, 641), VX_MASK,    PPCSPE,         { RD, RA, RB } },
 { "evfsmul",   VX(4, 648), VX_MASK,    PPCSPE,         { RD, RA, RB } },
@@ -3255,7 +3260,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mulhwu",  XO(31,11,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
 { "mulhwu.", XO(31,11,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
 
-{ "isel",    XISEL(31,15),XISEL_MASK,  PPCISEL,        { RT, RA, RB, CRB } },
+{ "isellt",  X(31,15),      X_MASK,    PPCISEL,        { RT, RA, RB } },
+{ "iselgt",  X(31,47),      X_MASK,    PPCISEL,        { RT, RA, RB } },
+{ "iseleq",  X(31,79),      X_MASK,    PPCISEL,        { RT, RA, RB } },
+{ "isel",    XISEL(31,15),  XISEL_MASK,        PPCISEL,        { RT, RA, RB, CRB } },
 
 { "mfcr",    X(31,19), XRARB_MASK,     COM,            { RT } },
 
@@ -3406,7 +3414,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "addeo.",  XO(31,138,1,1), XO_MASK,  PPCCOM,         { RT, RA, RB } },
 { "aeo.",    XO(31,138,1,1), XO_MASK,  PWRCOM,         { RT, RA, RB } },
 
-{ "dcbtstlse",X(31,142),X_MASK,                PPCCHLK,        { CT, RA, RB }},
+{ "dcbtstlse",X(31,142),X_MASK,                PPCCHLK64,      { CT, RA, RB }},
 
 { "mtcr",    XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM,     { RS }},
 { "mtcrf",   X(31,144),        XFXFXM_MASK,    COM,            { FXM, RS } },
@@ -3434,7 +3442,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "wrteei",  X(31,163),        XE_MASK,        BOOKE,          { E } },
 
 { "dcbtls",  X(31,166),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
-{ "dcbtlse", X(31,174),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
+{ "dcbtlse", X(31,174),        X_MASK,         PPCCHLK64,      { CT, RA, RB }},
 
 { "mtmsrd",  X(31,178),        XRLARB_MASK,    PPC64,          { RS, MTMSRD_L } },
 
@@ -3514,7 +3522,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mullwo.", XO(31,235,1,1), XO_MASK,  PPCCOM,         { RT, RA, RB } },
 { "mulso.",  XO(31,235,1,1), XO_MASK,  PWRCOM,         { RT, RA, RB } },
 
-{ "icblce",  X(31,238),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
+{ "icblce",  X(31,238),        X_MASK,         PPCCHLK64,      { CT, RA, RB }},
 { "mtsrin",  X(31,242),        XRA_MASK,       PPC32,          { RS, RB } },
 { "mtsri",   X(31,242),        XRA_MASK,       POWER32,        { RS, RB } },
 
@@ -3577,19 +3585,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "lhzuxe",  X(31,319),        X_MASK,         BOOKE64,        { RT, RAL, RB } },
 
-{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403,       { RT } },
-{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403,       { RT } },
-{ "mfbr0",   XSPR(31,323,128), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr1",   XSPR(31,323,129), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr2",   XSPR(31,323,130), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr3",   XSPR(31,323,131), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr4",   XSPR(31,323,132), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr5",   XSPR(31,323,133), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr6",   XSPR(31,323,134), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr7",   XSPR(31,323,135), XSPR_MASK, PPC403,      { RT } },
-{ "mfbear",  XSPR(31,323,144), XSPR_MASK, PPC403,      { RT } },
-{ "mfbesr",  XSPR(31,323,145), XSPR_MASK, PPC403,      { RT } },
-{ "mfiocr",  XSPR(31,323,160), XSPR_MASK, PPC403,      { RT } },
+{ "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,     { RT } },
+{ "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,     { RT } },
+{ "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,     { RT } },
+{ "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,     { RT } },
+{ "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,     { RT } },
+{ "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,     { RT } },
 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,     { RT } },
 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,     { RT } },
 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,     { RT } },
@@ -3610,9 +3618,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,     { RT } },
 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,     { RT } },
 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,     { RT } },
-{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403,      { RT } },
-{ "mfdcr",   X(31,323),        X_MASK,         PPC403,         { RT, SPR } },
-{ "mfdcr",   X(31,323),        X_MASK,         BOOKE,          { RT, SPR } },
+{ "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,     { RT } },
+{ "mfdcr",    X(31,323),       X_MASK,         PPC403,         { RT, SPR } },
+{ "mfdcr",    X(31,323),       X_MASK,         BOOKE,          { RT, SPR } },
 
 { "div",     XO(31,331,0,0), XO_MASK,  M601,           { RT, RA, RB } },
 { "div.",    XO(31,331,0,1), XO_MASK,  M601,           { RT, RA, RB } },
@@ -3621,94 +3629,137 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mfpmr",   X(31,334),        X_MASK,         PPCPMR,         { RT, PMRN }},
 
-{ "mfmq",     XSPR(31,339,0),   XSPR_MASK, M601,       { RT } },
-{ "mfxer",    XSPR(31,339,1),   XSPR_MASK, COM,                { RT } },
-{ "mfrtcu",   XSPR(31,339,4),   XSPR_MASK, COM,                { RT } },
-{ "mfrtcl",   XSPR(31,339,5),   XSPR_MASK, COM,                { RT } },
-{ "mfdec",    XSPR(31,339,6),   XSPR_MASK, MFDEC1,     { RT } },
-{ "mflr",     XSPR(31,339,8),   XSPR_MASK, COM,                { RT } },
-{ "mfctr",    XSPR(31,339,9),   XSPR_MASK, COM,                { RT } },
-{ "mftid",    XSPR(31,339,17),  XSPR_MASK, POWER,      { RT } },
-{ "mfdsisr",  XSPR(31,339,18),  XSPR_MASK, COM,                { RT } },
-{ "mfdar",    XSPR(31,339,19),  XSPR_MASK, COM,                { RT } },
-{ "mfdec",    XSPR(31,339,22),  XSPR_MASK, MFDEC2,     { RT } },
-{ "mfsdr0",   XSPR(31,339,24),  XSPR_MASK, POWER,      { RT } },
-{ "mfsdr1",   XSPR(31,339,25),  XSPR_MASK, COM,                { RT } },
-{ "mfsrr0",   XSPR(31,339,26),  XSPR_MASK, COM,                { RT } },
-{ "mfsrr1",   XSPR(31,339,27),  XSPR_MASK, COM,                { RT } },
-{ "mfcmpa",   XSPR(31,339,144), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmpb",   XSPR(31,339,145), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmpc",   XSPR(31,339,146), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmpd",   XSPR(31,339,147), XSPR_MASK, PPC860,     { RT } },
-{ "mficr",    XSPR(31,339,148), XSPR_MASK, PPC860,     { RT } },
-{ "mfder",    XSPR(31,339,149), XSPR_MASK, PPC860,     { RT } },
-{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860,     { RT } },
-{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmpe",   XSPR(31,339,152), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmpf",   XSPR(31,339,153), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmpg",   XSPR(31,339,154), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmph",   XSPR(31,339,155), XSPR_MASK, PPC860,     { RT } },
-{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860,     { RT } },
-{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860,     { RT } },
-{ "mfictrl",  XSPR(31,339,158), XSPR_MASK, PPC860,     { RT } },
-{ "mfbar",    XSPR(31,339,159), XSPR_MASK, PPC860,     { RT } },
-{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC,     { RT } },
-{ "mfsprg4",  XSPR(31,339,260), XSPR_MASK, PPC405,     { RT } },
-{ "mfsprg5",  XSPR(31,339,261), XSPR_MASK, PPC405,     { RT } },
-{ "mfsprg6",  XSPR(31,339,262), XSPR_MASK, PPC405,     { RT } },
-{ "mfsprg7",  XSPR(31,339,263), XSPR_MASK, PPC405,     { RT } },
-{ "mfsprg",   XSPR(31,339,272), XSPRG_MASK, PPC,       { RT, SPRG } },
-{ "mfsprg0",  XSPR(31,339,272), XSPR_MASK, PPC,                { RT } },
-{ "mfsprg1",  XSPR(31,339,273), XSPR_MASK, PPC,                { RT } },
-{ "mfsprg2",  XSPR(31,339,274), XSPR_MASK, PPC,                { RT } },
-{ "mfsprg3",  XSPR(31,339,275), XSPR_MASK, PPC,                { RT } },
-{ "mfasr",    XSPR(31,339,280), XSPR_MASK, PPC64,      { RT } },
-{ "mfear",    XSPR(31,339,282), XSPR_MASK, PPC,                { RT } },
-{ "mfpvr",    XSPR(31,339,287), XSPR_MASK, PPC,                { RT } },
-{ "mfspefscr",XSPR(31,339,512), XSPR_MASK, PPCSPE,     { RT } },
-{ "mfibatu",  XSPR(31,339,528), XSPRBAT_MASK, PPC,     { RT, SPRBAT } },
-{ "mfibatl",  XSPR(31,339,529), XSPRBAT_MASK, PPC,     { RT, SPRBAT } },
-{ "mfdbatu",  XSPR(31,339,536), XSPRBAT_MASK, PPC,     { RT, SPRBAT } },
-{ "mfdbatl",  XSPR(31,339,537), XSPRBAT_MASK, PPC,     { RT, SPRBAT } },
-{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860,     { RT } },
-{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860,     { RT } },
-{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860,     { RT } },
-{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860,     { RT } },
-{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860,     { RT } },
-{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860,     { RT } },
-{ "mfdpdr",   XSPR(31,339,630), XSPR_MASK, PPC860,     { RT } },
-{ "mfdpir",   XSPR(31,339,631), XSPR_MASK, PPC860,     { RT } },
-{ "mfimmr",   XSPR(31,339,638), XSPR_MASK, PPC860,     { RT } },
-{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860,     { RT } },
-{ "mfmi_ap",  XSPR(31,339,786), XSPR_MASK, PPC860,     { RT } },
-{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860,     { RT } },
-{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860,     { RT } },
-{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860,     { RT } },
-{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860,     { RT } },
-{ "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860,     { RT } },
-{ "mfmd_ap",  XSPR(31,339,794), XSPR_MASK, PPC860,     { RT } },
-{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860,     { RT } },
-{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860,     { RT } },
-{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860,     { RT } },
-{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860,     { RT } },
-{ "mfm_tw",   XSPR(31,339,799), XSPR_MASK, PPC860,     { RT } },
-{ "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860,    { RT } },
-{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860,   { RT } },
-{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860,   { RT } },
-{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860,   { RT } },
-{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860,   { RT } },
-{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860,   { RT } },
-{ "mfzpr",     XSPR(31,339,944), XSPR_MASK, PPC403,    { RT } },
-{ "mfpid",     XSPR(31,339,945), XSPR_MASK, PPC403,    { RT } },
-{ "mfccr0",    XSPR(31,339,947), XSPR_MASK, PPC405,    { RT } },
-{ "mficdbdr",  XSPR(31,339,979), XSPR_MASK, PPC403,    { RT } },
-{ "mfummcr0",  XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
-{ "mfupmc1",   XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
-{ "mfupmc2",   XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
-{ "mfusia",    XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
-{ "mfummcr1",  XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
-{ "mfupmc3",   XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
-{ "mfupmc4",   XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
+{ "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,    { RT } },
+{ "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,     { RT } },
+{ "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,     { RT } },
+{ "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,     { RT } },
+{ "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,  { RT } },
+{ "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,     { RT } },
+{ "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,     { RT } },
+{ "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,   { RT } },
+{ "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,     { RT } },
+{ "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,     { RT } },
+{ "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,  { RT } },
+{ "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,   { RT } },
+{ "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,     { RT } },
+{ "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,     { RT } },
+{ "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,     { RT } },
+{ "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,  { RT } },
+{ "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,  { RT } },
+{ "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,  { RT } },
+{ "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,  { RT } },
+{ "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,  { RT } },
+{ "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,  { RT } },
+{ "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,  { RT } },
+{ "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,  { RT } },
+{ "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405,  { RT } },
+{ "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405,  { RT } },
+{ "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405,  { RT } },
+{ "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405,  { RT } },
+{ "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
+{ "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfsprg",     XSPR(31,339,272),  XSPRG_MASK, PPC,    { RT, SPRG } },
+{ "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,     { RT } },
+{ "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,     { RT } },
+{ "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,     { RT } },
+{ "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,     { RT } },
+{ "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,   { RT } },
+{ "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,     { RT } },
+{ "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,     { RT } },
+{ "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
+{ "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
+{ "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,  { RT } },
+{ "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
+{ "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
+{ "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
+{ "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
+{ "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
+{ "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,  { RT } },
+{ "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,  { RT } },
+{ "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,  { RT } },
+{ "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,  { RT } },
+{ "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,  { RT } },
+{ "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
+{ "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
+{ "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
+{ "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,  { RT } },
+{ "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,  { RT } },
+{ "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,  { RT } },
+{ "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,  { RT } },
+{ "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,  { RT } },
+{ "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
+{ "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
+{ "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
+{ "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
+{ "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
+{ "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
+{ "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
+{ "mfzpr",     XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },
+{ "mfpid",     XSPR(31,339,945),  XSPR_MASK, PPC403,   { RT } },
+{ "mfccr0",    XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },
 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,  { RT } },
 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,  { RT } },
 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,  { RT } },
@@ -3725,35 +3776,36 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfpmc3",    XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
 { "mfdbcr1",   XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
 { "mfpmc4",    XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
-{ "mfesr",   XSPR(31,339,980), XSPR_MASK, PPC403,      { RT } },
-{ "mfdear",  XSPR(31,339,981), XSPR_MASK, PPC403,      { RT } },
-{ "mfevpr",  XSPR(31,339,982), XSPR_MASK, PPC403,      { RT } },
-{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403,      { RT } },
-{ "mftsr",   XSPR(31,339,984), XSPR_MASK, PPC403,      { RT } },
-{ "mftcr",   XSPR(31,339,986), XSPR_MASK, PPC403,      { RT } },
-{ "mfpit",   XSPR(31,339,987), XSPR_MASK, PPC403,      { RT } },
-{ "mftbhi",  XSPR(31,339,988), XSPR_MASK, PPC403,      { RT } },
-{ "mftblo",  XSPR(31,339,989), XSPR_MASK, PPC403,      { RT } },
-{ "mfsrr2",  XSPR(31,339,990), XSPR_MASK, PPC403,      { RT } },
-{ "mfsrr3",  XSPR(31,339,991), XSPR_MASK, PPC403,      { RT } },
-{ "mfdbsr",  XSPR(31,339,1008), XSPR_MASK, PPC403,     { RT } },
-{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405,     { RT } },
-{ "mfiac1",  XSPR(31,339,1012), XSPR_MASK, PPC403,     { RT } },
-{ "mfiac2",  XSPR(31,339,1013), XSPR_MASK, PPC403,     { RT } },
-{ "mfdac1",  XSPR(31,339,1014), XSPR_MASK, PPC403,     { RT } },
-{ "mfdac2",  XSPR(31,339,1015), XSPR_MASK, PPC403,     { RT } },
-{ "mfdccr",  XSPR(31,339,1018), XSPR_MASK, PPC403,     { RT } },
-{ "mficcr",  XSPR(31,339,1019), XSPR_MASK, PPC403,     { RT } },
-{ "mfpbl1",  XSPR(31,339,1020), XSPR_MASK, PPC403,     { RT } },
-{ "mfpbu1",  XSPR(31,339,1021), XSPR_MASK, PPC403,     { RT } },
-{ "mfpbl2",  XSPR(31,339,1022), XSPR_MASK, PPC403,     { RT } },
-{ "mfpbu2",  XSPR(31,339,1023), XSPR_MASK, PPC403,     { RT } },
-{ "mfl2cr",    XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
-{ "mfictc",    XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
-{ "mfthrm1",   XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
-{ "mfthrm2",   XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
-{ "mfthrm3",   XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
-{ "mfspr",   X(31,339),        X_MASK,         COM,            { RT, SPR } },
+{ "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
+{ "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,  { RT } },
+{ "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,  { RT } },
+{ "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,  { RT } },
+{ "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,  { RT } },
+{ "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,  { RT } },
+{ "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,  { RT } },
+{ "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,  { RT } },
+{ "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,  { RT } },
+{ "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,  { RT } },
+{ "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,  { RT } },
+{ "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,  { RT } },
+{ "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,  { RT } },
+{ "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,  { RT } },
+{ "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,  { RT } },
+{ "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,  { RT } },
+{ "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,  { RT } },
+{ "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,  { RT } },
+{ "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
+{ "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,  { RT } },
+{ "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,  { RT } },
+{ "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
+{ "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,  { RT } },
+{ "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
+{ "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,  { RT } },
+{ "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
+{ "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,  { RT } },
+{ "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
+{ "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,  { RT } },
+{ "mfspr",      X(31,339),        X_MASK,    COM,      { RT, SPR } },
 
 { "lwax",    X(31,341),        X_MASK,         PPC64,          { RT, RA, RB } },
 
@@ -3783,6 +3835,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mftbl",   XSPR(31,371,268), XSPR_MASK, CLASSIC,     { RT } },
 { "mftbu",   XSPR(31,371,269), XSPR_MASK, CLASSIC,     { RT } },
+{ "mftb",    X(31,371),        X_MASK,         BOOKE,          { RT, TBR } },
 { "mftb",    X(31,371),        X_MASK,         CLASSIC,        { RT, TBR } },
 
 { "lwaux",   X(31,373),        X_MASK,         PPC64,          { RT, RAL, RB } },
@@ -3801,7 +3854,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "adde64",  XO(31,394,0,0), XO_MASK,  BOOKE64,        { RT, RA, RB } },
 { "adde64o", XO(31,394,1,0), XO_MASK,  BOOKE64,        { RT, RA, RB } },
 
-{ "dcblce",  X(31,398),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
+{ "dcblce",  X(31,398),        X_MASK,         PPCCHLK64,      { CT, RA, RB }},
 
 { "slbmte",  X(31,402), XRA_MASK,      PPC64,          { RS, RB } },
 
@@ -3836,19 +3889,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mr.",     XRC(31,444,1), X_MASK,    COM,            { RA, RS, RBS } },
 { "or.",     XRC(31,444,1), X_MASK,    COM,            { RA, RS, RB } },
 
-{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403,       { RT } },
-{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403,       { RT } },
-{ "mtbr0",   XSPR(31,451,128), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr1",   XSPR(31,451,129), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr2",   XSPR(31,451,130), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr3",   XSPR(31,451,131), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr4",   XSPR(31,451,132), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr5",   XSPR(31,451,133), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr6",   XSPR(31,451,134), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr7",   XSPR(31,451,135), XSPR_MASK, PPC403,      { RT } },
-{ "mtbear",  XSPR(31,451,144), XSPR_MASK, PPC403,      { RT } },
-{ "mtbesr",  XSPR(31,451,145), XSPR_MASK, PPC403,      { RT } },
-{ "mtiocr",  XSPR(31,451,160), XSPR_MASK, PPC403,      { RT } },
+{ "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,     { RT } },
+{ "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,     { RT } },
+{ "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,     { RT } },
+{ "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,     { RT } },
+{ "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,     { RT } },
+{ "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,     { RT } },
 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,     { RT } },
 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,     { RT } },
 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,     { RT } },
@@ -3869,9 +3922,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,     { RT } },
 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,     { RT } },
 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403,      { RT } },
-{ "mtdcr",   X(31,451),        X_MASK,         PPC403,         { SPR, RS } },
-{ "mtdcr",   X(31,451),        X_MASK,         BOOKE,          { SPR, RS } },
+{ "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,     { RT } },
+{ "mtdcr",    X(31,451),       X_MASK,         PPC403,         { SPR, RS } },
+{ "mtdcr",    X(31,451),       X_MASK,         BOOKE,          { SPR, RS } },
 
 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,       { RT, RA } },
 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,      { RT, RA } },
@@ -3889,111 +3942,157 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "divwuo",  XO(31,459,1,0), XO_MASK,  PPC,            { RT, RA, RB } },
 { "divwuo.", XO(31,459,1,1), XO_MASK,  PPC,            { RT, RA, RB } },
 
-{ "mtmq",    XSPR(31,467,0),   XSPR_MASK,    M601,     { RS } },
-{ "mtxer",   XSPR(31,467,1),   XSPR_MASK,    COM,      { RS } },
-{ "mtlr",    XSPR(31,467,8),   XSPR_MASK,    COM,      { RS } },
-{ "mtctr",   XSPR(31,467,9),   XSPR_MASK,    COM,      { RS } },
-{ "mttid",   XSPR(31,467,17),  XSPR_MASK,    POWER,    { RS } },
-{ "mtdsisr", XSPR(31,467,18),  XSPR_MASK,    COM,      { RS } },
-{ "mtdar",   XSPR(31,467,19),  XSPR_MASK,    COM,      { RS } },
-{ "mtrtcu",  XSPR(31,467,20),  XSPR_MASK,    COM,      { RS } },
-{ "mtrtcl",  XSPR(31,467,21),  XSPR_MASK,    COM,      { RS } },
-{ "mtdec",   XSPR(31,467,22),  XSPR_MASK,    COM,      { RS } },
-{ "mtsdr0",  XSPR(31,467,24),  XSPR_MASK,    POWER,    { RS } },
-{ "mtsdr1",  XSPR(31,467,25),  XSPR_MASK,    COM,      { RS } },
-{ "mtsrr0",  XSPR(31,467,26),  XSPR_MASK,    COM,      { RS } },
-{ "mtsrr1",  XSPR(31,467,27),  XSPR_MASK,    COM,      { RS } },
-{ "mtcmpa",   XSPR(31,467,144), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmpb",   XSPR(31,467,145), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmpc",   XSPR(31,467,146), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmpd",   XSPR(31,467,147), XSPR_MASK, PPC860,     { RT } },
-{ "mticr",    XSPR(31,467,148), XSPR_MASK, PPC860,     { RT } },
-{ "mtder",    XSPR(31,467,149), XSPR_MASK, PPC860,     { RT } },
-{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860,     { RT } },
-{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmpe",   XSPR(31,467,152), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmpf",   XSPR(31,467,153), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmpg",   XSPR(31,467,154), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmph",   XSPR(31,467,155), XSPR_MASK, PPC860,     { RT } },
-{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860,     { RT } },
-{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860,     { RT } },
-{ "mtictrl",  XSPR(31,467,158), XSPR_MASK, PPC860,     { RT } },
-{ "mtbar",    XSPR(31,467,159), XSPR_MASK, PPC860,     { RT } },
-{ "mtvrsave",XSPR(31,467,256), XSPR_MASK,    PPCVEC,   { RT } },
-{ "mtsprg",  XSPR(31,467,272), XSPRG_MASK,   PPC,      { SPRG, RS } },
-{ "mtsprg0", XSPR(31,467,272), XSPR_MASK,    PPC,      { RT } },
-{ "mtsprg1", XSPR(31,467,273), XSPR_MASK,    PPC,      { RT } },
-{ "mtsprg2", XSPR(31,467,274), XSPR_MASK,    PPC,      { RT } },
-{ "mtsprg3", XSPR(31,467,275), XSPR_MASK,    PPC,      { RT } },
-{ "mtsprg4", XSPR(31,467,276), XSPR_MASK,    PPC405,   { RT } },
-{ "mtsprg5", XSPR(31,467,277), XSPR_MASK,    PPC405,   { RT } },
-{ "mtsprg6", XSPR(31,467,278), XSPR_MASK,    PPC405,   { RT } },
-{ "mtsprg7", XSPR(31,467,279), XSPR_MASK,    PPC405,   { RT } },
-{ "mtasr",   XSPR(31,467,280), XSPR_MASK,    PPC64,    { RS } },
-{ "mtear",   XSPR(31,467,282), XSPR_MASK,    PPC,      { RS } },
-{ "mttbl",   XSPR(31,467,284), XSPR_MASK,    PPC,      { RS } },
-{ "mttbu",   XSPR(31,467,285), XSPR_MASK,    PPC,      { RS } },
-{ "mtspefscr",XSPR(31,467,512),XSPR_MASK,    PPCSPE,   { RT } },
-{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC,      { SPRBAT, RS } },
-{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC,      { SPRBAT, RS } },
-{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC,      { SPRBAT, RS } },
-{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC,      { SPRBAT, RS } },
-{ "mtzpr",   XSPR(31,467,944), XSPR_MASK, PPC403,      { RT } },
-{ "mtpid",   XSPR(31,467,945), XSPR_MASK, PPC403,      { RT } },
-{ "mtccr0",  XSPR(31,467,947), XSPR_MASK, PPC405,      { RT } },
-{ "mtiac3",  XSPR(31,467,948), XSPR_MASK, PPC405,      { RT } },
-{ "mtiac4",  XSPR(31,467,949), XSPR_MASK, PPC405,      { RT } },
-{ "mtdvc1",  XSPR(31,467,950), XSPR_MASK, PPC405,      { RT } },
-{ "mtdvc2",  XSPR(31,467,951), XSPR_MASK, PPC405,      { RT } },
-{ "mtsgr",   XSPR(31,467,953), XSPR_MASK, PPC403,      { RT } },
-{ "mtdcwr",  XSPR(31,467,954), XSPR_MASK, PPC403,      { RT } },
-{ "mtsler",  XSPR(31,467,955), XSPR_MASK, PPC405,      { RT } },
-{ "mtsu0r",  XSPR(31,467,956), XSPR_MASK, PPC405,      { RT } },
-{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405,      { RT } },
-{ "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403,      { RT } },
-{ "mtesr",   XSPR(31,467,980), XSPR_MASK, PPC403,      { RT } },
-{ "mtdear",  XSPR(31,467,981), XSPR_MASK, PPC403,      { RT } },
-{ "mtevpr",  XSPR(31,467,982), XSPR_MASK, PPC403,      { RT } },
-{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403,      { RT } },
-{ "mttsr",   XSPR(31,467,984), XSPR_MASK, PPC403,      { RT } },
-{ "mttcr",   XSPR(31,467,986), XSPR_MASK, PPC403,      { RT } },
-{ "mtpit",   XSPR(31,467,987), XSPR_MASK, PPC403,      { RT } },
-{ "mttbhi",  XSPR(31,467,988), XSPR_MASK, PPC403,      { RT } },
-{ "mttblo",  XSPR(31,467,989), XSPR_MASK, PPC403,      { RT } },
-{ "mtsrr2",  XSPR(31,467,990), XSPR_MASK, PPC403,      { RT } },
-{ "mtsrr3",  XSPR(31,467,991), XSPR_MASK, PPC403,      { RT } },
-{ "mtdbsr",  XSPR(31,467,1008), XSPR_MASK, PPC403,     { RT } },
-{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405,     { RT } },
-{ "mtiac1",  XSPR(31,467,1012), XSPR_MASK, PPC403,     { RT } },
-{ "mtiac2",  XSPR(31,467,1013), XSPR_MASK, PPC403,     { RT } },
-{ "mtdac1",  XSPR(31,467,1014), XSPR_MASK, PPC403,     { RT } },
-{ "mtdac2",  XSPR(31,467,1015), XSPR_MASK, PPC403,     { RT } },
-{ "mtdccr",  XSPR(31,467,1018), XSPR_MASK, PPC403,     { RT } },
-{ "mticcr",  XSPR(31,467,1019), XSPR_MASK, PPC403,     { RT } },
-{ "mtpbl1",  XSPR(31,467,1020), XSPR_MASK, PPC403,     { RT } },
-{ "mtpbu1",  XSPR(31,467,1021), XSPR_MASK, PPC403,     { RT } },
-{ "mtpbl2",  XSPR(31,467,1022), XSPR_MASK, PPC403,     { RT } },
-{ "mtpbu2",  XSPR(31,467,1023), XSPR_MASK, PPC403,     { RT } },
-{ "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,   { RT } },
-{ "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,   { RT } },
-{ "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,   { RT } },
-{ "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,   { RT } },
-{ "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,   { RT } },
-{ "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,   { RT } },
-{ "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,   { RT } },
-{ "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,   { RT } },
-{ "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,   { RT } },
-{ "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,   { RT } },
-{ "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,   { RT } },
-{ "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,   { RT } },
-{ "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,   { RT } },
-{ "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,   { RT } },
-{ "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,   { RT } },
-{ "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,   { RT } },
-{ "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,   { RT } },
-{ "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,   { RT } },
-{ "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,   { RT } },
-{ "mtspr",   X(31,467),               X_MASK,       COM,       { SPR, RS } },
+{ "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,     { RS } },
+{ "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,      { RS } },
+{ "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,      { RS } },
+{ "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,      { RS } },
+{ "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,    { RS } },
+{ "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,      { RS } },
+{ "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,      { RS } },
+{ "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,      { RS } },
+{ "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,      { RS } },
+{ "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,      { RS } },
+{ "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,    { RS } },
+{ "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,      { RS } },
+{ "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,      { RS } },
+{ "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,      { RS } },
+{ "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,   { RT } },
+{ "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,   { RT } },
+{ "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,   { RT } },
+{ "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,   { RT } },
+{ "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,   { RT } },
+{ "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,   { RT } },
+{ "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,   { RT } },
+{ "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,   { RT } },
+{ "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtsprg",    XSPR(31,467,272),  XSPRG_MASK,PPC,      { SPRG, RS } },
+{ "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,      { RT } },
+{ "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,      { RT } },
+{ "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,      { RT } },
+{ "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,      { RT } },
+{ "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405,   { RT } },
+{ "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405,   { RT } },
+{ "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405,   { RT } },
+{ "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405,   { RT } },
+{ "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,    { RS } },
+{ "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,      { RS } },
+{ "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,      { RS } },
+{ "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,      { RS } },
+{ "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
+{ "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
+{ "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtspefscr", XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RT } },
+{ "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
+{ "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
+{ "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
+{ "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
+{ "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
+{ "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
+{ "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
+{ "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
+{ "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RT } },
+{ "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RT } },
+{ "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RT } },
+{ "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RT } },
+{ "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RT } },
+{ "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RT } },
+{ "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RT } },
+{ "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,   { RT } },
+{ "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,   { RT } },
+{ "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,   { RT } },
+{ "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,   { RT } },
+{ "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,   { RT } },
+{ "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,   { RT } },
+{ "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,   { RT } },
+{ "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RT } },
+{ "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,   { RT } },
+{ "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RT } },
+{ "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,   { RT } },
+{ "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RT } },
+{ "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,   { RT } },
+{ "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RT } },
+{ "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,   { RT } },
+{ "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RT } },
+{ "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,   { RT } },
+{ "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RT } },
+{ "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RT } },
+{ "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,   { RT } },
+{ "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,   { RT } },
+{ "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,   { RT } },
+{ "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,   { RT } },
+{ "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,   { RT } },
+{ "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,   { RT } },
+{ "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,   { RT } },
+{ "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,   { RT } },
+{ "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,   { RT } },
+{ "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,   { RT } },
+{ "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,   { RT } },
+{ "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,   { RT } },
+{ "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,   { RT } },
+{ "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,   { RT } },
+{ "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,   { RT } },
+{ "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,   { RT } },
+{ "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,   { RT } },
+{ "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,   { RT } },
+{ "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RT } },
+{ "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,   { RT } },
+{ "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,   { RT } },
+{ "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RT } },
+{ "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,   { RT } },
+{ "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RT } },
+{ "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,   { RT } },
+{ "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RT } },
+{ "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,   { RT } },
+{ "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RT } },
+{ "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,   { RT } },
+{ "mtspr",     X(31,467),        X_MASK,    COM,       { SPR, RS } },
 
 { "dcbi",    X(31,470),        XRT_MASK,       PPC,            { RA, RB } },
 
@@ -4028,7 +4127,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "divwo",   XO(31,491,1,0), XO_MASK,  PPC,            { RT, RA, RB } },
 { "divwo.",  XO(31,491,1,1), XO_MASK,  PPC,            { RT, RA, RB } },
 
-{ "icbtlse", X(31,494),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
+{ "icbtlse", X(31,494),        X_MASK,         PPCCHLK64,      { CT, RA, RB }},
 
 { "slbia",   X(31,498),        0xffffffff,     PPC64,          { 0 } },
 
@@ -4039,7 +4138,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mcrxr",   X(31,512),        XRARB_MASK|(3<<21), COM,        { BF } },
 
 { "bblels",  X(31,518),        X_MASK,         PPCBRLK,        { 0 }},
-{ "mcrxr64", X(31,544),        XRARB_MASK|(3<<21), BOOKE,      { BF } },
+{ "mcrxr64", X(31,544),        XRARB_MASK|(3<<21), BOOKE64,    { BF } },
 
 { "clcs",    X(31,531), XRB_MASK,      M601,           { RT, RA } },
 
@@ -4152,7 +4251,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "stfduxe", X(31,767),        X_MASK,         BOOKE64,        { FRS, RAS, RB } },
 
 { "tlbivax", X(31,786),        XRT_MASK,       BOOKE,          { RA, RB } },
-{ "tlbivaxe",X(31,787),        XRT_MASK,       BOOKE,          { RA, RB } },
+{ "tlbivaxe",X(31,787),        XRT_MASK,       BOOKE64,        { RA, RB } },
 
 { "lhbrx",   X(31,790),        X_MASK,         COM,            { RT, RA, RB } },
 
@@ -4189,8 +4288,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "tlbsx",   XRC(31,914,0), X_MASK,    BOOKE,          { RA, RB } },
 { "tlbsx.",  XRC(31,914,1), X_MASK,    BOOKE,          { RA, RB } },
-{ "tlbsxe",  XRC(31,915,0), X_MASK,    BOOKE,          { RA, RB } },
-{ "tlbsxe.", XRC(31,915,1), X_MASK,    BOOKE,          { RA, RB } },
+{ "tlbsxe",  XRC(31,915,0), X_MASK,    BOOKE64,        { RA, RB } },
+{ "tlbsxe.", XRC(31,915,1), X_MASK,    BOOKE64,        { RA, RB } },
 
 { "slbmfee", X(31,915), XRA_MASK,      PPC64,          { RT, RB } },
 
@@ -4238,8 +4337,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stfiwx",  X(31,983),        X_MASK,         PPC,            { FRS, RA, RB } },
 
-{ "extsw",   XRC(31,986,0), XRB_MASK,  PPC | BOOKE64,  { RA, RS } },
-{ "extsw.",  XRC(31,986,1), XRB_MASK,  PPC | BOOKE64,  { RA, RS } },
+{ "extsw",   XRC(31,986,0), XRB_MASK,  PPC64 | BOOKE64,{ RA, RS } },
+{ "extsw.",  XRC(31,986,1), XRB_MASK,  PPC64,          { RA, RS } },
 
 { "icread",  X(31,998),        XRT_MASK,       PPC403,         { RA, RB } },
 
@@ -4557,10 +4656,6 @@ const struct powerpc_macro powerpc_macros[] = {
 { "clrrwi.", 3,   PPCCOM,      "rlwinm. %0,%1,0,0,31-(%2)" },
 { "clrlslwi",4,   PPCCOM,      "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
 { "clrlslwi.",4,  PPCCOM,      "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
-
-{ "mftbl",   1,   BOOKE,       "mfspr %0,tbl" },
-{ "mftbu",   1,   BOOKE,       "mfspr %0,tbu" },
-{ "mftb",    2,   BOOKE,       "mfspr %0,%1" },
 };
 
 const int powerpc_num_macros =