setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
+ setOperationAction(ISD::SETCC, MVT::i32, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+
setSchedulingPreference(SchedulingForRegPressure);
computeRegisterProperties();
}
CALL,
/// Return with a flag operand.
- RET_FLAG
+ RET_FLAG,
+
+ CMP,
+
+ SELECT
};
}
}
default: return 0;
case ARMISD::CALL: return "ARMISD::CALL";
case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
+ case ARMISD::SELECT: return "ARMISD::SELECT";
+ case ARMISD::CMP: return "ARMISD::CMP";
}
}
return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
}
+static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
+ SDOperand LHS = Op.getOperand(0);
+ SDOperand RHS = Op.getOperand(1);
+ ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
+ SDOperand TrueVal = Op.getOperand(2);
+ SDOperand FalseVal = Op.getOperand(3);
+
+ assert(CC == ISD::SETEQ);
+
+ SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
+ return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, Cmp);
+}
+
SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default:
return LowerCALL(Op, DAG);
case ISD::RET:
return LowerRET(Op, DAG);
+ case ISD::SELECT_CC:
+ return LowerSELECT_CC(Op, DAG);
}
}
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
[SDNPHasChain, SDNPOptInFlag]>;
+def armselect : SDNode<"ARMISD::SELECT", SDTIntBinOp, [SDNPInFlag, SDNPOutFlag]>;
+
+def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
+def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKUP $amt",
def andrr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
"and $dst, $a, $b",
[(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
+
+let isTwoAddress = 1 in {
+ def moveq : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true),
+ "moveq $dst, $true",
+ [(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false))]>;
+}
+
+def cmp : InstARM<(ops IntRegs:$a, IntRegs:$b),
+ "cmp $a, $b",
+ [(armcmp IntRegs:$a, IntRegs:$b)]>;
if (!Fast)
PM.add(createLoopStrengthReducePass());
+ if (!Fast)
+ PM.add(createCFGSimplificationPass());
+
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
--- /dev/null
+int %f(int %a) {
+entry:
+ %tmp = seteq int %a, 4 ; <bool> [#uses=1]
+ br bool %tmp, label %cond_false, label %cond_true
+
+cond_true: ; preds = %entry
+ br label %return
+
+cond_false: ; preds = %entry
+ br label %return
+
+return: ; preds = %cond_false, %cond_true
+ %retval.0 = phi int [ 2, %cond_true ], [ 3, %cond_false ] ; <int> [#uses=1]
+ ret int %retval.0
+}