drm/nvc0/gr: add support for nvcf chipset

untested, written from a trace, accel disabled by default until it is

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 07691c2..83d549d 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -1011,6 +1011,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
                switch (dev_priv->chipset) {
                case 0xc1: /* known broken */
                case 0xc8: /* never tested */
+               case 0xcf: /* never tested */
                        NV_INFO(dev, "acceleration disabled by default, pass "
                                     "noaccel=0 to force enable\n");
                        dev_priv->noaccel = true;

diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c
index 5b2f6f4..8432164 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvc0_graph.c
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.c
@@ -864,6 +864,9 @@ nvc0_graph_create(struct drm_device *dev)
        case 0xce: /* 4/4/0/0, 4 */
                priv->magic_not_rop_nr = 0x03;
                break;
+       case 0xcf: /* 4/0/0/0, 3 */
+               priv->magic_not_rop_nr = 0x03;
+               break;
        }
 
        if (!priv->magic_not_rop_nr) {

diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.h b/drivers/gpu/drm/nouveau/nvc0_graph.h
index 55689e9..636fe98 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvc0_graph.h
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.h
@@ -82,6 +82,7 @@ nvc0_graph_class(struct drm_device *dev)
        case 0xc3:
        case 0xc4:
        case 0xce: /* guess, mmio trace shows only 0x9097 state */
+       case 0xcf: /* guess, mmio trace shows only 0x9097 state */
                return 0x9097;
        case 0xc1:
                return 0x9197;

diff --git a/drivers/gpu/drm/nouveau/nvc0_grctx.c b/drivers/gpu/drm/nouveau/nvc0_grctx.c
index 31018ea..0c9737a 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvc0_grctx.c
+++ b/drivers/gpu/drm/nouveau/nvc0_grctx.c
@@ -1678,7 +1678,10 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
        nv_wr32(dev, 0x419c04, 0x00000006);
        nv_wr32(dev, 0x419c08, 0x00000002);
        nv_wr32(dev, 0x419c20, 0x00000000);
-       nv_wr32(dev, 0x419cb0, 0x00060048); //XXX: 0xce 0x00020048
+       if (chipset == 0xce || chipset == 0xcf)
+               nv_wr32(dev, 0x419cb0, 0x00020048);
+       else
+               nv_wr32(dev, 0x419cb0, 0x00060048);
        nv_wr32(dev, 0x419ce8, 0x00000000);
        nv_wr32(dev, 0x419cf4, 0x00000183);
        nv_wr32(dev, 0x419d20, chipset != 0xc1 ? 0x02180000 : 0x12180000);
@@ -1784,7 +1787,7 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
 
        if (1) {
                const u8 chipset_tp_max[] = { 16, 4, 0, 4, 8, 0, 0, 0,
-                                             16, 0, 0, 0, 0, 0, 8, 0 };
+                                             16, 0, 0, 0, 0, 0, 8, 4 };
                u8 max = chipset_tp_max[dev_priv->chipset & 0x0f];
                u8 tpnr[GPC_MAX];
                u8 data[TP_MAX];

diff --git a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc
index 0ec2add..06f5e26 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc
+++ b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc
@@ -77,6 +77,11 @@ chipsets:
 .b16 nvc0_gpc_mmio_tail
 .b16 nvc0_tpc_mmio_head
 .b16 nvc3_tpc_mmio_tail
+.b8  0xcf 0 0 0
+.b16 nvc0_gpc_mmio_head
+.b16 nvc0_gpc_mmio_tail
+.b16 nvc0_tpc_mmio_head
+.b16 nvcf_tpc_mmio_tail
 .b8  0 0 0 0
 
 // GPC mmio lists
@@ -134,8 +139,9 @@ mmctx_data(0x000750, 2)
 nvc0_tpc_mmio_tail:
 mmctx_data(0x000758, 1)
 mmctx_data(0x0002c4, 1)
-mmctx_data(0x0004bc, 1)
 mmctx_data(0x0006e0, 1)
+nvcf_tpc_mmio_tail:
+mmctx_data(0x0004bc, 1)
 nvc3_tpc_mmio_tail:
 mmctx_data(0x000544, 1)
 nvc1_tpc_mmio_tail:

diff --git a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h
index 1896c89..6f82032 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h
+++ b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h
@@ -25,23 +25,26 @@ uint32_t nvc0_grgpc_data[] = {
        0x00000000,
        0x00000000,
        0x000000c0,
-       0x011000b0,
-       0x01640114,
+       0x011c00bc,
+       0x01700120,
        0x000000c1,
-       0x011400b0,
-       0x01780114,
+       0x012000bc,
+       0x01840120,
        0x000000c3,
-       0x011000b0,
-       0x01740114,
+       0x011c00bc,
+       0x01800120,
        0x000000c4,
-       0x011000b0,
-       0x01740114,
+       0x011c00bc,
+       0x01800120,
        0x000000c8,
-       0x011000b0,
-       0x01640114,
+       0x011c00bc,
+       0x01700120,
        0x000000ce,
-       0x011000b0,
-       0x01740114,
+       0x011c00bc,
+       0x01800120,
+       0x000000cf,
+       0x011c00bc,
+       0x017c0120,
        0x00000000,
        0x00000380,
        0x14000400,
@@ -90,8 +93,8 @@ uint32_t nvc0_grgpc_data[] = {
        0x04000750,
        0x00000758,
        0x000002c4,
-       0x000004bc,
        0x000006e0,
+       0x000004bc,
        0x00000544,
 };
 

diff --git a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc
index a1a5991..e4f8c7e 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc
+++ b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc
@@ -56,6 +56,9 @@ chipsets:
 .b8  0xce 0 0 0
 .b16 nvc0_hub_mmio_head
 .b16 nvc0_hub_mmio_tail
+.b8  0xcf 0 0 0
+.b16 nvc0_hub_mmio_head
+.b16 nvc0_hub_mmio_tail
 .b8  0 0 0 0
 
 nvc0_hub_mmio_head:

diff --git a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h
index b3b541b..241d326 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h
+++ b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h
@@ -23,17 +23,19 @@ uint32_t nvc0_grhub_data[] = {
        0x00000000,
        0x00000000,
        0x000000c0,
-       0x012c0090,
+       0x01340098,
        0x000000c1,
-       0x01300090,
+       0x01380098,
        0x000000c3,
-       0x012c0090,
+       0x01340098,
        0x000000c4,
-       0x012c0090,
+       0x01340098,
        0x000000c8,
-       0x012c0090,
+       0x01340098,
        0x000000ce,
-       0x012c0090,
+       0x01340098,
+       0x000000cf,
+       0x01340098,
        0x00000000,
        0x0417e91c,
        0x04400204,
@@ -190,8 +192,6 @@ uint32_t nvc0_grhub_data[] = {
        0x00000000,
        0x00000000,
        0x00000000,
-       0x00000000,
-       0x00000000,
 };
 
 uint32_t nvc0_grhub_code[] = {