Fix PPCEMB for 32bit hosts.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3059 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 57e4662..435b838 100644 (file)
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -693,7 +693,7 @@ struct CPUPPCState {
     /* temporary fixed-point registers
      * used to emulate 64 bits target on 32 bits hosts
      */ 
-    target_ulong t0, t1, t2;
+    ppc_gpr_t t0, t1, t2;
 #endif
     ppc_avr_t t0_avr, t1_avr, t2_avr;
 

diff --git a/target-ppc/exec.h b/target-ppc/exec.h
index ee5183e..69807ad 100644 (file)
--- a/target-ppc/exec.h
+++ b/target-ppc/exec.h
@@ -43,15 +43,15 @@ register unsigned long T1 asm(AREG2);
 register unsigned long T2 asm(AREG3);
 #endif
 /* We may, sometime, need 64 bits registers on 32 bits target */
-#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB) || (HOST_LONG_BITS == 64)
-#define T0_64 T0
-#define T1_64 T1
-#define T2_64 T2
-#else
+#if TARGET_GPR_BITS > HOST_LONG_BITS
 /* no registers can be used */
 #define T0_64 (env->t0)
 #define T1_64 (env->t1)
 #define T2_64 (env->t2)
+#else
+#define T0_64 T0
+#define T1_64 T1
+#define T2_64 T2
 #endif
 /* Provision for Altivec */
 #define T0_avr (env->t0_avr)