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drm/amdgpu: retire indirect mmio reg support from cgs
authorHawking Zhang <Hawking.Zhang@amd.com>
Fri, 3 Apr 2020 09:37:39 +0000 (17:37 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 9 Apr 2020 14:43:18 +0000 (10:43 -0400)
not needed anymore

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
drivers/gpu/drm/amd/include/cgs_common.h

index 031b094..78ac6db 100644 (file)
@@ -60,8 +60,6 @@ static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
 {
        CGS_FUNC_ADEV;
        switch (space) {
-       case CGS_IND_REG__MMIO:
-               return RREG32_IDX(index);
        case CGS_IND_REG__PCIE:
                return RREG32_PCIE(index);
        case CGS_IND_REG__SMC:
@@ -77,6 +75,8 @@ static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
        case CGS_IND_REG__AUDIO_ENDPT:
                DRM_ERROR("audio endpt register access not implemented.\n");
                return 0;
+       default:
+               BUG();
        }
        WARN(1, "Invalid indirect register space");
        return 0;
@@ -88,8 +88,6 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
 {
        CGS_FUNC_ADEV;
        switch (space) {
-       case CGS_IND_REG__MMIO:
-               return WREG32_IDX(index, value);
        case CGS_IND_REG__PCIE:
                return WREG32_PCIE(index, value);
        case CGS_IND_REG__SMC:
@@ -105,6 +103,8 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
        case CGS_IND_REG__AUDIO_ENDPT:
                DRM_ERROR("audio endpt register access not implemented.\n");
                return;
+       default:
+               BUG();
        }
        WARN(1, "Invalid indirect register space");
 }
index a69deb3..60a6536 100644 (file)
@@ -32,7 +32,6 @@ struct cgs_device;
  * enum cgs_ind_reg - Indirect register spaces
  */
 enum cgs_ind_reg {
-       CGS_IND_REG__MMIO,
        CGS_IND_REG__PCIE,
        CGS_IND_REG__SMC,
        CGS_IND_REG__UVD_CTX,