[AArch64] Adjust the cost model for Exynos M3

Fix the modeling of long division and SIMD conversion from integer and
horizontal minimum and maximum.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324417 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64SchedExynosM3.td b/lib/Target/AArch64/AArch64SchedExynosM3.td
index ca75c22..4520115 100644 (file)
--- a/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ b/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -198,8 +198,8 @@ def : WriteRes<WriteID32, [M3UnitC,
                            M3UnitD]>  { let Latency = 12;
                                         let ResourceCycles = [1, 12]; }
 def : WriteRes<WriteID64, [M3UnitC,
-                           M3UnitD]>  { let Latency = 12;
-                                        let ResourceCycles = [1, 12]; }
+                           M3UnitD]>  { let Latency = 21;
+                                        let ResourceCycles = [1, 21]; }
 def : WriteRes<WriteIM32, [M3UnitC]>  { let Latency = 3; }
 def : WriteRes<WriteIM64, [M3UnitC]>  { let Latency = 4;
                                         let ResourceCycles = [2]; }
@@ -304,7 +304,7 @@ def M3WriteNEONY   : SchedWriteRes<[M3UnitFSQR,
                                                     let NumMicroOps = 1;
                                                     let ResourceCycles = [26]; }
 def M3WriteNEONZ   : SchedWriteRes<[M3UnitNMSC,
-                                    M3UnitNMSC]>  { let Latency = 4;
+                                    M3UnitNMSC]>  { let Latency = 5;
                                                     let NumMicroOps = 2; }
 def M3WriteFADD2   : SchedWriteRes<[M3UnitFADD]>  { let Latency = 2; }
 def M3WriteFCVT2   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 2; }
@@ -608,7 +608,7 @@ def : InstRW<[M3WriteNEONA],  (instregex "^FADDP")>;
 def : InstRW<[M3WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
 def : InstRW<[M3WriteFCVT3],  (instregex "^FCVT(L|N|XN)v")>;
 def : InstRW<[M3WriteFCVT2],  (instregex "^FCVT[AMNPZ][SU]v")>;
-def : InstRW<[M3WriteFCVT3],  (instregex "^[SU]CVTFv")>;
+def : InstRW<[M3WriteFCVT2],  (instregex "^[SU]CVTFv")>;
 def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>;
 def : InstRW<[M3WriteNEONV],  (instrs FDIVv4f32)>;
 def : InstRW<[M3WriteNEONW],  (instrs FDIVv2f64)>;