arm64: dts: qcom: sm6350: Add cpufreq-hw support

Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable
CPU clock scaling.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-8-konrad.dybcio@somainline.org

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index e01a2b5..fc4b1c3 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -42,6 +42,7 @@
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
                        next-level-cache = <&L2_0>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
                        L2_0: l2-cache {
                                compatible = "cache";
@@ -60,6 +61,7 @@
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
                        next-level-cache = <&L2_100>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
                        L2_100: l2-cache {
                                compatible = "cache";
@@ -75,6 +77,7 @@
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
                        next-level-cache = <&L2_200>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
                        L2_200: l2-cache {
                                compatible = "cache";
@@ -90,6 +93,7 @@
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
                        next-level-cache = <&L2_300>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
                        L2_300: l2-cache {
                                compatible = "cache";
@@ -105,6 +109,7 @@
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
                        next-level-cache = <&L2_400>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
                        L2_400: l2-cache {
                                compatible = "cache";
@@ -120,6 +125,7 @@
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
                        next-level-cache = <&L2_500>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
                        L2_500: l2-cache {
                                compatible = "cache";
@@ -136,6 +142,7 @@
                        capacity-dmips-mhz = <1894>;
                        dynamic-power-coefficient = <703>;
                        next-level-cache = <&L2_600>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        #cooling-cells = <2>;
                        L2_600: l2-cache {
                                compatible = "cache";
@@ -151,6 +158,7 @@
                        capacity-dmips-mhz = <1894>;
                        dynamic-power-coefficient = <703>;
                        next-level-cache = <&L2_700>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        #cooling-cells = <2>;
                        L2_700: l2-cache {
                                compatible = "cache";
@@ -621,6 +629,16 @@
                                clocks = <&xo_board>;
                        };
                };
+
+               cpufreq_hw: cpufreq@18323000 {
+                       compatible = "qcom,cpufreq-hw";
+                       reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
+                       reg-names = "freq-domain0", "freq-domain1";
+                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+                       clock-names = "xo", "alternate";
+
+                       #freq-domain-cells = <1>;
+               };
        };
 
        timer {