drm: rcar-du: Rename DORCR fields to make them 0-based

The DORCR fields were documented in the R-Car H1 datasheet with 1-based
named, and then got renamed to 0-based in Gen2. The 0-based names are
used for Gen3 and Gen4, making H1 an outlier. Rename the field macros to
make them 0-based, in order to increase readability of the code when
comparing it with the documentation.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index 1526022..b595074 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -175,7 +175,7 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
         * Use DS1PR and DS2PR to configure planes priorities and connects the
         * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
         */
-       rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
+       rcar_du_group_write(rgrp, DORCR, DORCR_PG0D_DS0 | DORCR_DPRS);
 
        /* Apply planes to CRTCs association. */
        mutex_lock(&rgrp->lock);
@@ -349,7 +349,7 @@ int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
        struct rcar_du_device *rcdu = rgrp->dev;
        u32 dorcr = rcar_du_group_read(rgrp, DORCR);
 
-       dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
+       dorcr &= ~(DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_MASK);
 
        /*
         * Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
@@ -357,9 +357,9 @@ int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
         * by default.
         */
        if (rcdu->dpad1_source == rgrp->index * 2)
-               dorcr |= DORCR_PG2D_DS1;
+               dorcr |= DORCR_PG1D_DS0;
        else
-               dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
+               dorcr |= DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_DS1;
 
        rcar_du_group_write(rgrp, DORCR, dorcr);
 

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
index 789ae92..6c750fa 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
@@ -511,19 +511,19 @@
  */
 
 #define DORCR                  0x11000
-#define DORCR_PG2T             (1 << 30)
-#define DORCR_DK2S             (1 << 28)
-#define DORCR_PG2D_DS1         (0 << 24)
-#define DORCR_PG2D_DS2         (1 << 24)
-#define DORCR_PG2D_FIX0                (2 << 24)
-#define DORCR_PG2D_DOOR                (3 << 24)
-#define DORCR_PG2D_MASK                (3 << 24)
-#define DORCR_DR1D             (1 << 21)
-#define DORCR_PG1D_DS1         (0 << 16)
-#define DORCR_PG1D_DS2         (1 << 16)
-#define DORCR_PG1D_FIX0                (2 << 16)
-#define DORCR_PG1D_DOOR                (3 << 16)
-#define DORCR_PG1D_MASK                (3 << 16)
+#define DORCR_PG1T             (1 << 30)
+#define DORCR_DK1S             (1 << 28)
+#define DORCR_PG1D_DS0         (0 << 24)
+#define DORCR_PG1D_DS1         (1 << 24)
+#define DORCR_PG1D_FIX0                (2 << 24)
+#define DORCR_PG1D_DOOR                (3 << 24)
+#define DORCR_PG1D_MASK                (3 << 24)
+#define DORCR_DR0D             (1 << 21)
+#define DORCR_PG0D_DS0         (0 << 16)
+#define DORCR_PG0D_DS1         (1 << 16)
+#define DORCR_PG0D_FIX0                (2 << 16)
+#define DORCR_PG0D_DOOR                (3 << 16)
+#define DORCR_PG0D_MASK                (3 << 16)
 #define DORCR_RGPV             (1 << 4)
 #define DORCR_DPRS             (1 << 0)