ravb: Update ravb_emac_init_gbeth()

This patch enables Receive/Transmit port of TOE and removes
the setting of promiscuous bit from EMAC configuration mode register.

This patch also update EMAC configuration mode comment from
"PAUSE prohibition" to "EMAC Mode: PAUSE prohibition; Duplex; TX;
RX; CRC Pass Through".

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index 69a7715..08062d7 100644 (file)
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -204,6 +204,7 @@ enum ravb_reg {
        TLFRCR  = 0x0758,
        RFCR    = 0x0760,
        MAFCR   = 0x0778,
+       CSR0    = 0x0800,       /* RZ/G2L only */
 };
 
 
@@ -964,6 +965,11 @@ enum CXR31_BIT {
        CXR31_SEL_LINK1 = 0x00000008,
 };
 
+enum CSR0_BIT {
+       CSR0_TPE        = 0x00000010,
+       CSR0_RPE        = 0x00000020,
+};
+
 #define DBAT_ENTRY_NUM 22
 #define RX_QUEUE_OFFSET        4
 #define NUM_RX_QUEUE   2

diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index 21fb83f..f3f676e 100644 (file)
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -519,10 +519,10 @@ static void ravb_emac_init_gbeth(struct net_device *ndev)
        /* Receive frame limit set register */
        ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR);
 
-       /* PAUSE prohibition */
+       /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */
        ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) |
                         ECMR_TE | ECMR_RE | ECMR_RCPT |
-                        ECMR_TXF | ECMR_RXF | ECMR_PRM, ECMR);
+                        ECMR_TXF | ECMR_RXF, ECMR);
 
        ravb_set_rate_gbeth(ndev);
 
@@ -534,6 +534,7 @@ static void ravb_emac_init_gbeth(struct net_device *ndev)
 
        /* E-MAC status register clear */
        ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR);
+       ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);
 
        /* E-MAC interrupt enable register */
        ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);