rtc: pcf2127: adapt time/date registers write sequence for PCF2131

The sequence for updating the time/date registers is slightly
different between PCF2127/29 and PCF2131.

For PCF2127/29, during write operations, the time counting
circuits (memory locations 03h through 09h) are automatically blocked.

For PCF2131, time/date registers write access requires setting the
STOP bit and sending the clear prescaler instruction (CPR). STOP then
needs to be released once write operation is completed.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Link: https://lore.kernel.org/r/20230622145800.2442116-14-hugo@hugovil.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index 83dcb1e..f6a549b 100644 (file)
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -33,6 +33,7 @@
 #define PCF2127_REG_CTRL1              0x00
 #define PCF2127_BIT_CTRL1_POR_OVRD             BIT(3)
 #define PCF2127_BIT_CTRL1_TSF1                 BIT(4)
+#define PCF2127_BIT_CTRL1_STOP                 BIT(5)
 /* Control register 2 */
 #define PCF2127_REG_CTRL2              0x01
 #define PCF2127_BIT_CTRL2_AIE                  BIT(1)
@@ -280,13 +281,45 @@ static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm)
        /* year */
        buf[i++] = bin2bcd(tm->tm_year - 100);
 
-       /* write register's data */
+       /* Write access to time registers:
+        * PCF2127/29: no special action required.
+        * PCF2131:    requires setting the STOP and CPR bits. STOP bit needs to
+        *             be cleared after time registers are updated.
+        */
+       if (pcf2127->cfg->type == PCF2131) {
+               err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
+                                        PCF2127_BIT_CTRL1_STOP,
+                                        PCF2127_BIT_CTRL1_STOP);
+               if (err) {
+                       dev_dbg(dev, "setting STOP bit failed\n");
+                       return err;
+               }
+
+               err = regmap_write(pcf2127->regmap, PCF2131_REG_SR_RESET,
+                                  PCF2131_SR_RESET_CPR_CMD);
+               if (err) {
+                       dev_dbg(dev, "sending CPR cmd failed\n");
+                       return err;
+               }
+       }
+
+       /* write time register's data */
        err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i);
        if (err) {
                dev_dbg(dev, "%s: err=%d", __func__, err);
                return err;
        }
 
+       if (pcf2127->cfg->type == PCF2131) {
+               /* Clear STOP bit (PCF2131 only) after write is completed. */
+               err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
+                                        PCF2127_BIT_CTRL1_STOP, 0);
+               if (err) {
+                       dev_dbg(dev, "clearing STOP bit failed\n");
+                       return err;
+               }
+       }
+
        return 0;
 }