drm/amdgpu: abstract setup vmid config for gfxhub/mmhub

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 3359b2c..626afc0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -195,31 +195,10 @@ static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 
 }
 
-int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
+static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 {
-       u32 tmp;
-       u32 i;
-
-       if (amdgpu_sriov_vf(adev)) {
-               /*
-                * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
-                * VF copy registers so vbios post doesn't program them, for
-                * SRIOV driver need to program them
-                */
-               WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
-                               adev->mc.vram_start >> 24);
-               WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
-                               adev->mc.vram_end >> 24);
-       }
-
-       /* GART Enable. */
-       gfxhub_v1_0_init_gart_aperture_regs(adev);
-       gfxhub_v1_0_init_system_aperture_regs(adev);
-       gfxhub_v1_0_init_tlb_regs(adev);
-       gfxhub_v1_0_init_cache_regs(adev);
-
-       gfxhub_v1_0_enable_system_domain(adev);
-       gfxhub_v1_0_disable_identity_aperture(adev);
+       int i;
+       uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
                tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
@@ -251,7 +230,31 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
                WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
                        upper_32_bits(adev->vm_manager.max_pfn - 1));
        }
+}
+
+int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
+{
+       if (amdgpu_sriov_vf(adev)) {
+               /*
+                * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+                * VF copy registers so vbios post doesn't program them, for
+                * SRIOV driver need to program them
+                */
+               WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
+                               adev->mc.vram_start >> 24);
+               WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
+                               adev->mc.vram_end >> 24);
+       }
+
+       /* GART Enable. */
+       gfxhub_v1_0_init_gart_aperture_regs(adev);
+       gfxhub_v1_0_init_system_aperture_regs(adev);
+       gfxhub_v1_0_init_tlb_regs(adev);
+       gfxhub_v1_0_init_cache_regs(adev);
 
+       gfxhub_v1_0_enable_system_domain(adev);
+       gfxhub_v1_0_disable_identity_aperture(adev);
+       gfxhub_v1_0_setup_vmid_config(adev);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index bd05425..a5b0177 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -205,31 +205,10 @@ static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
                mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
 }
 
-int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
+static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 {
-       u32 tmp;
-       u32 i;
-
-       if (amdgpu_sriov_vf(adev)) {
-               /*
-                * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
-                * VF copy registers so vbios post doesn't program them, for
-                * SRIOV driver need to program them
-                */
-               WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE),
-                       adev->mc.vram_start >> 24);
-               WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP),
-                       adev->mc.vram_end >> 24);
-       }
-
-       /* GART Enable. */
-       mmhub_v1_0_init_gart_aperture_regs(adev);
-       mmhub_v1_0_init_system_aperture_regs(adev);
-       mmhub_v1_0_init_tlb_regs(adev);
-       mmhub_v1_0_init_cache_regs(adev);
-
-       mmhub_v1_0_enable_system_domain(adev);
-       mmhub_v1_0_disable_identity_aperture(adev);
+       int i;
+       uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
                tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL)
@@ -263,6 +242,31 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
                WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
                        upper_32_bits(adev->vm_manager.max_pfn - 1));
        }
+}
+
+int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
+{
+       if (amdgpu_sriov_vf(adev)) {
+               /*
+                * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+                * VF copy registers so vbios post doesn't program them, for
+                * SRIOV driver need to program them
+                */
+               WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE),
+                       adev->mc.vram_start >> 24);
+               WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP),
+                       adev->mc.vram_end >> 24);
+       }
+
+       /* GART Enable. */
+       mmhub_v1_0_init_gart_aperture_regs(adev);
+       mmhub_v1_0_init_system_aperture_regs(adev);
+       mmhub_v1_0_init_tlb_regs(adev);
+       mmhub_v1_0_init_cache_regs(adev);
+
+       mmhub_v1_0_enable_system_domain(adev);
+       mmhub_v1_0_disable_identity_aperture(adev);
+       mmhub_v1_0_setup_vmid_config(adev);
 
        return 0;
 }