This patch disables SH-4 optimizations that rely on the FPU when
building for variants that don't have an FPU, such as SH-4AL.
Signed-off-by: Andrew Stubbs <ams@codesourcery.com>
Signed-off-by: Carmelo Amoroso <carmelo.amoroso@st.com>
#include <sysdep.h>
#include <endian.h>
-#ifdef __LITTLE_ENDIAN__
+#if defined (__LITTLE_ENDIAN__) && defined (__SH_FPU_ANY__)
#define MEMCPY_USES_FPU
/* Use paired single precision load or store mode for 64-bit tranfering.
* FPSCR.SZ=1,FPSCR.SZ=0 is well defined on both SH4-200 and SH4-300.
* Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball.
*/
-#include <string.h>
+#ifndef __SH_FPU_ANY__
+#include "../../generic/memmove.c"
+#else
+#include <string.h>
#define FPSCR_SR (1 << 20)
#define STORE_FPSCR(x) __asm__ volatile("sts fpscr, %0" : "=r"(x))
}
libc_hidden_def(memmove)
+#endif /*__SH_FPU_ANY__ */
#include <sysdep.h>
-#ifdef __LITTLE_ENDIAN__
+#if defined (__LITTLE_ENDIAN__) && defined (__SH_FPU_ANY__)
#define MEMSET_USES_FPU
/* Use paired single precision load or store mode for 64-bit tranfering.
* FPSCR.SZ=1,FPSCR.SZ=0 is well defined on both SH4-200 and SH4-300.